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dbrownell [Thu, 17 Sep 2009 18:56:17 +0000 (18:56 +0000)]

Minor fixes to NAND code and docs

Erase logic:
- command invocation
    + treat "nand erase N" (no offset/length) as "erase whole chip N"
    + catch a few more bogus parameter cases, like length == 0 (sigh)
- nand_erase() should be static
- on error
    + say which block failed, and if it was a bad block
    + don't give up after the first error; try to erase the rest
- on success, say which nand device was erased (name isn't unique)

Device list ("nand list"):
- say how many blocks there are
- split summary into two lines
- give example in the docs

Doc tweaks:
- Use @option{...} for DaVinci's supported hardware ECC options

For the record, I've observed that _sometimes_ erasing bad blocks causes
failure reports, and that manufacturer bad block markers aren't always
erasable (even when erasing their blocks doesn't trigger an error report).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2724 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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dbrownell [Thu, 17 Sep 2009 18:52:32 +0000 (18:52 +0000)]

Fix coredump seen in some code paths.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2723 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 17 Sep 2009 12:25:53 +0000 (12:25 +0000)]

michal smulski <michal.smulski@ooma.com> fix regression in jtag_add_pathmove() which broke arm11 in r1825. Other uses of jtag_add_pathmove are svn + xsvf + xscale...

git-svn-id: svn://svn.berlios.de/openocd/trunk@2722 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 17 Sep 2009 11:44:14 +0000 (11:44 +0000)]

prefix zy1000_reboot command to avoid name conflicts

git-svn-id: svn://svn.berlios.de/openocd/trunk@2721 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 17 Sep 2009 11:23:41 +0000 (11:23 +0000)]

srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_jtag added to reset_config. Could i.MX27 be a case where srst does not pull trst, but really srst gates jtag clock?

git-svn-id: svn://svn.berlios.de/openocd/trunk@2720 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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dbrownell [Thu, 17 Sep 2009 08:02:43 +0000 (08:02 +0000)]

The "arm9tdmi.c" file is more of a generic ARM9 support file:

- update comments to say so.
- update docs to clarify that the "arm9tdmi" command prefix
is a misnomer.
- bugfix some messages that wrongly assume only ARM9TDMI
based processors use this code.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2719 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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dbrownell [Thu, 17 Sep 2009 07:56:24 +0000 (07:56 +0000)]

Doc update: mention how ARM's WFI instruction affects
JTAG clocking by gating the core clock, and workarounds.
Most details are with the "halt" command, which is one
of the first places this issue will be noticed.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2718 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Wed, 16 Sep 2009 18:18:38 +0000 (18:18 +0000)]

Remove unused varables (moved to armv7a)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2717 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Wed, 16 Sep 2009 18:17:26 +0000 (18:17 +0000)]

Use a variable armv7a->debug_base instead of hardedcoded OMAP3530_DEBUG_BASE

git-svn-id: svn://svn.berlios.de/openocd/trunk@2716 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 16 Sep 2009 12:38:26 +0000 (12:38 +0000)]

Rolf Meeser <rolfm_9dq@yahoo.de> adds flash support for NXP's LPC2900 family (ARM968E).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2715 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Tue, 15 Sep 2009 16:20:39 +0000 (16:20 +0000)]

Define debug_base, debug_ap, memory_ap in armv7a_common_t

git-svn-id: svn://svn.berlios.de/openocd/trunk@2714 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Tue, 15 Sep 2009 15:50:09 +0000 (15:50 +0000)]

Updated mode string list.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2713 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Tue, 15 Sep 2009 15:41:14 +0000 (15:41 +0000)]

Definy symbolic values for VA to PA address translation operations

git-svn-id: svn://svn.berlios.de/openocd/trunk@2712 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Tue, 15 Sep 2009 14:20:37 +0000 (14:20 +0000)]

fix bug when using 32 instead of 64 bit value in callback, caught by -Wall

git-svn-id: svn://svn.berlios.de/openocd/trunk@2711 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Tue, 15 Sep 2009 09:41:09 +0000 (09:41 +0000)]

added embedded ice programming while srst is asserted todo item

git-svn-id: svn://svn.berlios.de/openocd/trunk@2710 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Mon, 14 Sep 2009 22:41:47 +0000 (22:41 +0000)]

Check return values to avoid infinite wait in loop on error.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2709 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Mon, 14 Sep 2009 22:36:27 +0000 (22:36 +0000)]

Cache invalidation when writing to memory

git-svn-id: svn://svn.berlios.de/openocd/trunk@2708 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 14 Sep 2009 13:54:49 +0000 (13:54 +0000)]

error message upon recursive invocation of reset from reset event handlers

git-svn-id: svn://svn.berlios.de/openocd/trunk@2707 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 14 Sep 2009 08:03:57 +0000 (08:03 +0000)]

fix email address

git-svn-id: svn://svn.berlios.de/openocd/trunk@2706 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 14 Sep 2009 07:48:28 +0000 (07:48 +0000)]

Rolf Meeser <rolfm_9dq@yahoo.de> warning fix in previous commit was wrong. target_code_size needs the real value later.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2705 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 14 Sep 2009 06:06:35 +0000 (06:06 +0000)]

fix warning

git-svn-id: svn://svn.berlios.de/openocd/trunk@2704 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 13 Sep 2009 20:07:13 +0000 (20:07 +0000)]

Magnus Lundin <lundin@mlu.mine.nu> Disable poll while core register initialization

git-svn-id: svn://svn.berlios.de/openocd/trunk@2703 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Sun, 13 Sep 2009 17:26:07 +0000 (17:26 +0000)]

More CortexA8 debug register definitions.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2702 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Sun, 13 Sep 2009 13:57:50 +0000 (13:57 +0000)]

Fix argument passing in cortex_a8_write_cp.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2701 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sat, 12 Sep 2009 13:05:20 +0000 (13:05 +0000)]

Dirk Behme <dirk.behme@googlemail.com> document post TAP reset event

git-svn-id: svn://svn.berlios.de/openocd/trunk@2700 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sat, 12 Sep 2009 08:11:45 +0000 (08:11 +0000)]

David Brownell <david-b@pacbell.net>
Update the board config for the DaVinci DM355 EVM so the reset-init
event handler does the rest of the work it should do:

- minor PLL setup bugfixes
- initialize the DDR2 controller
- probe both NAND banks
- initialize UART0
- enable the icache

git-svn-id: svn://svn.berlios.de/openocd/trunk@2699 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sat, 12 Sep 2009 08:10:19 +0000 (08:10 +0000)]

David Brownell <david-b@pacbell.net>
Cleanup some the downloaded ARM target algorithm code:

- Provide more complete disassembly of the DCC bulk write code

- Make code blocks "static const", in case GCC doesn't

- Fix some tabbing/layout issues

- Make some arm7_9_common.h flags be "bool" not "int"; and compact
the layout a bit (group most bools together)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2698 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 21:14:31 +0000 (21:14 +0000)]

David Brownell <david-b@pacbell.net> some early todo items on run_algorithm

git-svn-id: svn://svn.berlios.de/openocd/trunk@2697 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 18:34:15 +0000 (18:34 +0000)]

tap post reset event added. Allows omap3530 to send 100 runtest idle tickle's after a TAP_RESET.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2696 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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ntfreak [Fri, 11 Sep 2009 14:08:28 +0000 (14:08 +0000)]

- revert change made to sheevaplug.cfg in rev2573

git-svn-id: svn://svn.berlios.de/openocd/trunk@2695 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 08:04:50 +0000 (08:04 +0000)]

Nicolas Pitre <nico@cam.org> put feroceon target definition at the end so to avoid a
bunch of useless forward declarations.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2694 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 08:03:46 +0000 (08:03 +0000)]

Nicolas Pitre <nico@cam.org> Dragonite support

git-svn-id: svn://svn.berlios.de/openocd/trunk@2693 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 07:46:50 +0000 (07:46 +0000)]

spelling mistake

git-svn-id: svn://svn.berlios.de/openocd/trunk@2692 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 07:43:36 +0000 (07:43 +0000)]

do not use dynamically sized stack arrays, not compatible with embedded OS's

git-svn-id: svn://svn.berlios.de/openocd/trunk@2691 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 06:58:49 +0000 (06:58 +0000)]

registering a target event twice caused infinite loop. Same bug as in jtag/core.c copy & pasted.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2690 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 06:08:51 +0000 (06:08 +0000)]

syntax error fix

git-svn-id: svn://svn.berlios.de/openocd/trunk@2689 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 06:01:28 +0000 (06:01 +0000)]

Alexei Babich <a.babich@rez.ru> cleanup

git-svn-id: svn://svn.berlios.de/openocd/trunk@2688 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 11 Sep 2009 05:57:51 +0000 (05:57 +0000)]

Nicolas Pitre <nico@cam.org> tighten error checking in bulk_write

git-svn-id: svn://svn.berlios.de/openocd/trunk@2687 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 10 Sep 2009 13:35:08 +0000 (13:35 +0000)]

eol-style:native

git-svn-id: svn://svn.berlios.de/openocd/trunk@2686 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 10 Sep 2009 13:17:25 +0000 (13:17 +0000)]

Alexei Babich <a.babich@rez.ru> imx31 nand flash controller support

git-svn-id: svn://svn.berlios.de/openocd/trunk@2685 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 10 Sep 2009 13:17:05 +0000 (13:17 +0000)]

Alexei Babich <a.babich@rez.ru> fix problems with unecessary tailend byte accesses. Use 16 bit access on tailend of a memory read if possible.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2684 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 10 Sep 2009 08:06:22 +0000 (08:06 +0000)]

michal smulski <michal.smulski@ooma.com> telo target/board scripts

git-svn-id: svn://svn.berlios.de/openocd/trunk@2683 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 9 Sep 2009 16:11:33 +0000 (16:11 +0000)]

Rolf Meeser <rolfm_9dq@yahoo.de>
This patch adds target algorithm support for those flash devices that do not support DQ5 polling. So far they could only be programmed with host algorithm, but this was way too slow.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2682 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 9 Sep 2009 07:09:14 +0000 (07:09 +0000)]

- Fix bug-in-waiting when adding more than one TAP event type
- Infinite loop bugfix when running tap configure a second time

git-svn-id: svn://svn.berlios.de/openocd/trunk@2681 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 9 Sep 2009 06:28:49 +0000 (06:28 +0000)]

David Brownell <david-b@pacbell.net>
Optionally shave time off the armv4_5 run_algorithm() code:  let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.

Enable this by using BKPT to terminate execution instead of "branch
to here" loops.  Then pass zero as the exit address, except when
running on an ARMv4 core.  ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.

Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps.  Some other algorithms
could use this too (mostly flavors of flash operation).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 9 Sep 2009 06:27:47 +0000 (06:27 +0000)]

David Brownell <david-b@pacbell.net>
Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.

(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic. MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2679 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Tue, 8 Sep 2009 15:32:18 +0000 (15:32 +0000)]

Report correct core instruction state for ARMv/A targets

git-svn-id: svn://svn.berlios.de/openocd/trunk@2678 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Tue, 8 Sep 2009 15:31:24 +0000 (15:31 +0000)]

Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2677 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Tue, 8 Sep 2009 06:18:45 +0000 (06:18 +0000)]

David Brownell <david-b@pacbell.net>
Provide an "armv7a disassemble" command. Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Tue, 8 Sep 2009 06:17:33 +0000 (06:17 +0000)]

David Brownell <david-b@pacbell.net>
lean up some loose ends with the ARM disassembler

- Add a header comment describing its current state and uses
   and referencing the now-generally-available V7 arch spec

- Support some mode switch instructions:
    * Thumb to Jazelle (BXJ)
    * Thumb to ThumbEE (ENTERX)
    * ThumbEE to Thumb (LEAVEX)

- Improve that recent warning fix (and associated whitespace goof)

- Declare the rest of the internal code and data "static".  A
   compiler may use this, and it helps clarify the scope of these
   routines (e.g. what changes to them could affect).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2675 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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mlu [Mon, 7 Sep 2009 20:19:17 +0000 (20:19 +0000)]

Improved handling of instruction set state, helps for debugging Thumb state.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2674 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 19:35:10 +0000 (19:35 +0000)]

Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mips_m4k.c Swapping is already done in target.c

git-svn-id: svn://svn.berlios.de/openocd/trunk@2673 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 11:03:26 +0000 (11:03 +0000)]

use "armv4_5 core_state arm" instead of soft_reset_halt, fewer side effects

git-svn-id: svn://svn.berlios.de/openocd/trunk@2672 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 08:27:27 +0000 (08:27 +0000)]

Dirk Behme <dirk.behme@googlemail.com> retire jtag_speed usage

git-svn-id: svn://svn.berlios.de/openocd/trunk@2671 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 08:27:08 +0000 (08:27 +0000)]

Dirk Behme <dirk.behme@googlemail.com> Add default fall back freqency.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2670 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 08:23:24 +0000 (08:23 +0000)]

set ARM mode using explicit command rather than soft_reset_halt which has lots of side effects.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2669 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 08:22:02 +0000 (08:22 +0000)]

Matt Hsu <matt@0xlab.org> This patch simply enables the halting debug mode.
By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 08:21:18 +0000 (08:21 +0000)]

more debug output for breakpoints

git-svn-id: svn://svn.berlios.de/openocd/trunk@2667 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 05:20:45 +0000 (05:20 +0000)]

Matt Hsu <matt@0xlab.org> Tidy up the bit-offset operation for DSCR register

git-svn-id: svn://svn.berlios.de/openocd/trunk@2666 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 05:17:03 +0000 (05:17 +0000)]

David Brownell <david-b@pacbell.net> "set _TARGETNAME ..." cleanup

git-svn-id: svn://svn.berlios.de/openocd/trunk@2665 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 4 Sep 2009 05:14:32 +0000 (05:14 +0000)]

David Claffey <dnclaffey@gmail.com> get rid of reset recursion

git-svn-id: svn://svn.berlios.de/openocd/trunk@2664 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 3 Sep 2009 08:23:39 +0000 (08:23 +0000)]

David Brownell

Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.

Have davinci_nand do so. This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.

NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2663 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 2 Sep 2009 17:34:35 +0000 (17:34 +0000)]

David Claffey <dnclaffey@gmail.com> tested with the Atheros reference design "PB44"

git-svn-id: svn://svn.berlios.de/openocd/trunk@2662 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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duane [Wed, 2 Sep 2009 00:17:39 +0000 (00:17 +0000)]

Crusty Code fixes from the tcl directory re-arragements

git-svn-id: svn://svn.berlios.de/openocd/trunk@2661 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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ntfreak [Tue, 1 Sep 2009 10:08:41 +0000 (10:08 +0000)]

- fixes the incorrect info msg displayed during stellaris flash programming.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2660 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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ntfreak [Tue, 1 Sep 2009 10:08:00 +0000 (10:08 +0000)]

- fix a regression when using cortex_m3 emulated dcc channel

git-svn-id: svn://svn.berlios.de/openocd/trunk@2659 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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duane [Mon, 31 Aug 2009 12:21:12 +0000 (12:21 +0000)]

Warning fix

git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 31 Aug 2009 09:06:01 +0000 (09:06 +0000)]

Gary Carlson <gcarlson@carlson-minot.com> config file

git-svn-id: svn://svn.berlios.de/openocd/trunk@2657 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Mon, 31 Aug 2009 06:02:01 +0000 (06:02 +0000)]

Ferdinand Postema <ferdinand@postema.eu> config script for the MMnet1001 module from Propox.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2656 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 21:12:50 +0000 (21:12 +0000)]

David Brownell <david-b@pacbell.net> Minor code bugfix: check right variable.
Via code review by Steve Grubb <sgrubb@redhat.com>

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 20:08:07 +0000 (20:08 +0000)]

Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 20:05:40 +0000 (20:05 +0000)]

David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right bits, right value!

git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 20:04:17 +0000 (20:04 +0000)]

David Brownell <david-b@pacbell.net> Remove duplicate check for flash write status.
Via code review by Steve Grubb <sgrubb@redhat.com>

Also minor fixes for the message from "fill": the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 17:32:56 +0000 (17:32 +0000)]

David Brownell <david-b@pacbell.net> Minor doc updates:

- Itemize the list of private customization examples
for openocd.cfg

- Add "override defaults" as a customization, specifically
for the work area (back it up or relocate it)

- Highlight some work area location issues

git-svn-id: svn://svn.berlios.de/openocd/trunk@2651 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 17:30:14 +0000 (17:30 +0000)]

David Brownell <david-b@pacbell.net> start phasing out integers as target IDs

git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Sun, 30 Aug 2009 17:27:50 +0000 (17:27 +0000)]

David Brownell <david-b@pacbell.net> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one. Say, because
you're bugfixing a private copy...

git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 28 Aug 2009 17:18:36 +0000 (17:18 +0000)]

David Brownell <david-b@pacbell.net> fix warnings

git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 28 Aug 2009 13:43:26 +0000 (13:43 +0000)]

added arm11 timeout error messages

git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 28 Aug 2009 09:47:19 +0000 (09:47 +0000)]

restore ICE watchpoint registers when the *last* software breakpoint is removed

git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 28 Aug 2009 06:53:35 +0000 (06:53 +0000)]

David Brownell <david-b@pacbell.net> The Stellaris eval boards don't have TRST signals, so
defining ntrst_delay is pointless; don't.

At least the LM3S3748 eval board doesn't need nsrst_delay
either; remove that too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2645 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Fri, 28 Aug 2009 06:52:08 +0000 (06:52 +0000)]

David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

- ARMv5J "BXJ" (for Java/Jazelle)
- ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested. This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include: UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 27 Aug 2009 10:37:01 +0000 (10:37 +0000)]

arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 27 Aug 2009 07:37:07 +0000 (07:37 +0000)]

arm11 single stepping wip - at least we know the next PC now

git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 27 Aug 2009 07:35:47 +0000 (07:35 +0000)]

arm11 single stepping wip

git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Thu, 27 Aug 2009 06:50:36 +0000 (06:50 +0000)]

refactor arm simulator to allow arm11 code to use it as well - no observable changes otherwise.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:27:33 +0000 (19:27 +0000)]

some arm11 stuff that isn't done yet.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2639 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:25:44 +0000 (19:25 +0000)]

Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> cortex-a8: Wait for the CPU to be halted/started

With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:24:45 +0000 (19:24 +0000)]

Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Print the value that the method didn't like

git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:23:35 +0000 (19:23 +0000)]

Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Only dap_ap_select when we are going to do a memory access
in the fast reg case.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:22:28 +0000 (19:22 +0000)]

Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the documentation

git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:21:26 +0000 (19:21 +0000)]

Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:20:25 +0000 (19:20 +0000)]

Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:16:08 +0000 (19:16 +0000)]

Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before executing a new instruction wait for the previous
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 19:06:56 +0000 (19:06 +0000)]

David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit loop on no-tap. Keep
"next iteration" step with the rest of the loop overhead.

Cleanup: remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 10:13:51 +0000 (10:13 +0000)]

added missing check on jtag_execute

git-svn-id: svn://svn.berlios.de/openocd/trunk@2630 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 10:03:54 +0000 (10:03 +0000)]

Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then simulation will fail. This is expected.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2629 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 08:32:03 +0000 (08:32 +0000)]

reduce arm11 output noise

git-svn-id: svn://svn.berlios.de/openocd/trunk@2628 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 07:11:16 +0000 (07:11 +0000)]

Michael Schwingen <rincewind@discworld.dascon.de> news about xscale

git-svn-id: svn://svn.berlios.de/openocd/trunk@2627 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Wed, 26 Aug 2009 06:26:29 +0000 (06:26 +0000)]

David Brownell <david-b@pacbell.net> Clock updates/fixes for the Stellaris flash driver:

- Bugfixes:
   * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
      + except new Tempest parts where it's 16 MHz (and calibrated!)
      + or some old Sandstorm ones, where 15 MHz was valid
   * crystal config:
      + read and use the crystal config, don't assume 6 MHz
      + know when that field is 4 bits vs 5
   * an RCC2 register may be overriding the original RCC
      + more clock source options
      + bigger dividers
      + fractional dividers on Tempest (NYET handled)
   * there's a 30 KHz osc on newer chips (for deep sleep)
   * there's a 32768 Hz osc on newer chips (for hibernation)

- Cosmetic
   * say "rev A0" not "vA.0", to match vendor docs
   * don't always report master clock as an "estimate":
      + give the error bound if it's approximate, like "±30%"
      + else don't say anything
   * fix whitespace and caps in some messages
   * these are not AT91SAM chips!!

Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.

That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor.  What's less clear is which chips are "old" like that.

Lightly tested, on a DustDevil part.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2626 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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oharboe [Tue, 25 Aug 2009 20:03:35 +0000 (20:03 +0000)]

David Brownell <david-b@pacbell.net> Various updates to 0.3.0 NEWS

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