From: Ulf Wetzker <ulf.wetzker@eas.iis.fraunhofer.de>
Date: Mon, 27 May 2013 11:41:46 +0000 (+0200)
Subject: at91sam3: Added support for at91sam3s8a, b and c
X-Git-Tag: v0.8.0-rc1~383
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=refs%2Fchanges%2F24%2F1424%2F3

at91sam3: Added support for at91sam3s8a, b and c

Only the support for at91sam3s8b is tested on real hardware.

Change-Id: I4ce23bc2f6131d9cf3ff1b301ab9e470d20845ab
Signed-off-by: Ulf Wetzker <ulf.wetzker@eas.iis.fraunhofer.de>
Reviewed-on: http://openocd.zylin.com/1424
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---

diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 3369dda992..1bb549e3b5 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -979,6 +979,102 @@ static const struct sam3_chip_details all_sam3_details[] = {
 			},
 		},
 	},
+	{
+		.chipid_cidr    = 0x288B0A60,
+		.name           = "at91sam3s8a",
+		.total_flash_size     = 256 * 2048,
+		.total_sram_size      = 64 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+		{
+/*		.bank[0] = { */
+			{
+				.probed = 0,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 6,	/* workaround silicon bug */
+				.present = 1,
+				.size_bytes = 256 * 2048,
+				.nsectors   = 16,
+				.sector_size = 32768,
+				.page_size   = 256,
+			},
+/*		.bank[1] = { */
+			{
+				.present = 0,
+				.probed = 0,
+				.bank_number = 1,
+
+			},
+		},
+	},
+	{
+		.chipid_cidr    = 0x289B0A60,
+		.name           = "at91sam3s8b",
+		.total_flash_size     = 256 * 2048,
+		.total_sram_size      = 64 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+		{
+/*		.bank[0] = { */
+			{
+				.probed = 0,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 6,	/* workaround silicon bug */
+				.present = 1,
+				.size_bytes = 256 * 2048,
+				.nsectors   = 16,
+				.sector_size = 32768,
+				.page_size   = 256,
+			},
+/*		.bank[1] = { */
+			{
+				.present = 0,
+				.probed = 0,
+				.bank_number = 1,
+
+			},
+		},
+	},
+	{
+		.chipid_cidr    = 0x28AB0A60,
+		.name           = "at91sam3s8c",
+		.total_flash_size     = 256 * 2048,
+		.total_sram_size      = 64 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+		{
+/*		.bank[0] = { */
+			{
+				.probed = 0,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 6,	/* workaround silicon bug */
+				.present = 1,
+				.size_bytes = 256 * 2048,
+				.nsectors   = 16,
+				.sector_size = 32768,
+				.page_size   = 256,
+			},
+/*		.bank[1] = { */
+			{
+				.present = 0,
+				.probed = 0,
+				.bank_number = 1,
+
+			},
+		},
+	},
 
 	/* Start at91sam3n* series */
 	{