From: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Date: Wed, 18 Apr 2018 08:06:29 +0000 (+0200)
Subject: aarch64: support for aarch32 ARM_MODE_SYS
X-Git-Tag: v0.11.0-rc1~858
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=bda2d7371874569cd5232580a3602dd56083a304

aarch64: support for aarch32 ARM_MODE_SYS

Treat ARM_MODE_SYS like all other Aarch32 processor modes,
except for the special case of missing SPSR.

Change-Id: I60b21703659b264f552884cdc0f85fd45f7836de
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4494
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
---

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 8fab3b5d7c..63174c2ebc 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -100,6 +100,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
 		case ARM_MODE_ABT:
 		case ARM_MODE_FIQ:
 		case ARM_MODE_IRQ:
+		case ARM_MODE_SYS:
 			instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 			break;
 
@@ -172,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_SYS:
 		instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 		break;
 
@@ -1032,6 +1034,7 @@ static int aarch64_post_debug_entry(struct target *target)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_SYS:
 		instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
 		break;
 
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 1981e7c3d5..cee837f584 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -73,6 +73,10 @@ static const struct {
 		.name = "ABT",
 		.psr = ARM_MODE_ABT,
 	},
+	{
+		.name = "SYS",
+		.psr = ARM_MODE_SYS,
+	},
 	{
 		.name = "EL0T",
 		.psr = ARMV8_64_EL0T,
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 3c941fa2db..a5d7d11f8d 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -573,6 +573,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 	case ARM_MODE_ABT:
 	case ARM_MODE_IRQ:
 	case ARM_MODE_FIQ:
+	case ARM_MODE_SYS:
 		target_el = 1;
 		break;
 	/*
@@ -790,6 +791,10 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 				dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
 			continue;
 
+		/* Special case: ARM_MODE_SYS has no SPSR at EL1 */
+		if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS)
+			continue;
+
 		retval = dpmv8_read_reg(dpm, r, i);
 		if (retval != ERROR_OK)
 			goto fail;