From: Zachary T Welch Date: Fri, 13 Nov 2009 17:43:03 +0000 (-0800) Subject: armv4_5_common_t -> struct arm X-Git-Tag: v0.4.0-rc1~628 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=af949b2531d2a8863d077025db40cbb170d13a63 armv4_5_common_t -> struct arm Remove misleading typedef and just use struct arm. --- diff --git a/src/flash/arm_nandio.c b/src/flash/arm_nandio.c index 63dcaebbb3..4f04831f52 100644 --- a/src/flash/arm_nandio.c +++ b/src/flash/arm_nandio.c @@ -43,7 +43,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size) { target_t *target = nand->target; struct armv4_5_algorithm algo; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct reg_param reg_params[3]; uint32_t target_buf; uint32_t exit = 0; diff --git a/src/flash/ocl.c b/src/flash/ocl.c index 14b3e7c2b6..0a2496dac6 100644 --- a/src/flash/ocl.c +++ b/src/flash/ocl.c @@ -47,7 +47,7 @@ static int ocl_protect_check(struct flash_bank_s *bank) FLASH_BANK_COMMAND_HANDLER(ocl_flash_bank_command) { int retval; - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; struct ocl_priv *ocl; diff --git a/src/flash/str9xpec.c b/src/flash/str9xpec.c index c553cdce52..ec5d031646 100644 --- a/src/flash/str9xpec.c +++ b/src/flash/str9xpec.c @@ -238,7 +238,7 @@ static int str9xpec_build_block_list(struct flash_bank_s *bank) FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command) { struct str9xpec_flash_controller *str9xpec_info; - armv4_5_common_t *armv4_5 = NULL; + struct arm *armv4_5 = NULL; struct arm7_9_common *arm7_9 = NULL; struct arm_jtag *jtag_info = NULL; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 26b09c7dd4..9bb7567351 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -178,7 +178,7 @@ int arm7_9_setup(target_t *target) * targets * @return ERROR_OK if successful */ -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p) +int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p) { struct arm7_9_common *arm7_9 = target_to_arm7_9(target); struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common; @@ -2877,7 +2877,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_command) int spsr; int retval; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -2922,7 +2922,7 @@ COMMAND_HANDLER(handle_arm7_9_write_xpsr_im8_command) int spsr; int retval; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -2963,7 +2963,7 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) uint32_t mode; int num; target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -2994,7 +2994,7 @@ COMMAND_HANDLER(handle_arm7_9_write_core_reg_command) COMMAND_HANDLER(handle_arm7_9_dbgrq_command) { target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -3027,7 +3027,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command) COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) { target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -3060,7 +3060,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command) COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) { target_t *target = get_current_target(cmd_ctx); - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK) @@ -3093,7 +3093,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command) int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9) { int retval = ERROR_OK; - armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common; + struct arm *armv4_5 = &arm7_9->armv4_5_common; arm7_9->common_magic = ARM7_9_COMMON_MAGIC; diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h index eb4eb1a976..41858c6840 100644 --- a/src/target/arm7_9_common.h +++ b/src/target/arm7_9_common.h @@ -154,6 +154,6 @@ void arm7_9_disable_eice_step(target_t *target); int arm7_9_execute_sys_speed(struct target_s *target); int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9); -int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p); +int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p); #endif /* ARM7_9_COMMON_H */ diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index fdd395a52d..c670c454e0 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -788,7 +788,7 @@ int arm9tdmi_init_target(struct command_context_s *cmd_ctx, int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; arm7_9 = &arm9tdmi->arm7_9_common; diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 941e41ce35..5252666785 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -788,21 +788,21 @@ int arm_simulate_step_core(target_t *target, static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32); } static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value); } static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32); @@ -810,7 +810,7 @@ static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg) static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32, value); @@ -818,21 +818,21 @@ static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_ static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits); } static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; return armv4_5->core_state; } static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; armv4_5->core_state = mode; } @@ -840,7 +840,7 @@ static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim) { - armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data; + struct arm *armv4_5 = (struct arm *)sim->user_data; return armv4_5->core_mode; } diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index fb6c93b8fe..4040623e3a 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -249,7 +249,7 @@ int armv4_5_invalidate_core_regs(target_t *target) return ERROR_OK; } -struct reg_cache* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common) +struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_common) { int num_regs = 37; struct reg_cache *cache = malloc(sizeof(struct reg_cache)); @@ -713,7 +713,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, struct me return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion); } -int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5) +int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5) { target->arch_info = armv4_5; diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h index 3c65069e02..9823f4e66b 100644 --- a/src/target/armv4_5.h +++ b/src/target/armv4_5.h @@ -84,7 +84,7 @@ enum * Cortex-M series cores do not support as many core states or shadowed * registers as traditional ARM cores, and only support Thumb2 instructions. */ -typedef struct arm +struct arm { int common_magic; struct reg_cache *core_cache; @@ -104,7 +104,7 @@ typedef struct arm int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value); void *arch_info; -} armv4_5_common_t; +}; #define target_to_armv4_5 target_to_arm @@ -132,11 +132,11 @@ struct armv4_5_core_reg int num; enum armv4_5_mode mode; target_t *target; - armv4_5_common_t *armv4_5_common; + struct arm *armv4_5_common; }; struct reg_cache* armv4_5_build_reg_cache(target_t *target, - armv4_5_common_t *armv4_5_common); + struct arm *armv4_5_common); /* map psr mode bits to linear number */ static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode) @@ -180,7 +180,7 @@ int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size); int armv4_5_register_commands(struct command_context_s *cmd_ctx); -int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5); +int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5); int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, struct mem_param *mem_params, diff --git a/src/target/armv7a.h b/src/target/armv7a.h index 910a884c53..c775d0c24d 100644 --- a/src/target/armv7a.h +++ b/src/target/armv7a.h @@ -106,7 +106,7 @@ struct armv7a_common /* Cache and Memory Management Unit */ struct armv4_5_mmu_common armv4_5_mmu; - armv4_5_common_t armv4_5_common; + struct arm armv4_5_common; // int (*full_context)(struct target_s *target); // int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode); diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index 82d0b28190..e1bd2e3241 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -1453,7 +1453,7 @@ static int cortex_a8_init_target(struct command_context_s *cmd_ctx, int cortex_a8_init_arch_info(target_t *target, struct cortex_a8_common *cortex_a8, struct jtag_tap *tap) { - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct armv7a_common *armv7a; armv7a = &cortex_a8->armv7a_common; diff --git a/src/target/feroceon.c b/src/target/feroceon.c index 0439f813d2..cf034c4289 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -58,7 +58,7 @@ int feroceon_assert_reset(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; int ud = arm7_9->use_dbgrq; @@ -110,7 +110,7 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr) void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -157,7 +157,7 @@ void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc) void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -176,7 +176,7 @@ void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_reg void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0; @@ -212,7 +212,7 @@ void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -235,7 +235,7 @@ void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr) void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -276,7 +276,7 @@ void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr) void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -294,7 +294,7 @@ void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int sps void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16]) { int i; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -313,7 +313,7 @@ void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_reg void feroceon_branch_resume(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -330,7 +330,7 @@ void feroceon_branch_resume_thumb(target_t *target) { LOG_DEBUG("-"); - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32); @@ -363,7 +363,7 @@ void feroceon_branch_resume_thumb(target_t *target) int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; int err; @@ -385,7 +385,7 @@ int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CR int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; struct arm_jtag *jtag_info = &arm7_9->jtag_info; @@ -404,7 +404,7 @@ int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t C void feroceon_set_dbgrq(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL]; @@ -414,7 +414,7 @@ void feroceon_set_dbgrq(target_t *target) void feroceon_enable_single_step(target_t *target, uint32_t next_pc) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; /* set a breakpoint there */ @@ -427,7 +427,7 @@ void feroceon_enable_single_step(target_t *target, uint32_t next_pc) void feroceon_disable_single_step(target_t *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]); @@ -451,7 +451,7 @@ int feroceon_examine_debug_reason(target_t *target) int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer) { int retval; - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; enum armv4_5_state core_state = armv4_5->core_state; uint32_t x, flip, shift, save[7]; @@ -585,7 +585,7 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar void feroceon_common_setup(struct target_s *target) { - armv4_5_common_t *armv4_5 = target->arch_info; + struct arm *armv4_5 = target->arch_info; struct arm7_9_common *arm7_9 = armv4_5->arch_info; /* override some insn sequence functions */ @@ -642,7 +642,7 @@ int dragonite_target_create(struct target_s *target, Jim_Interp *interp) int feroceon_examine(struct target_s *target) { - armv4_5_common_t *armv4_5; + struct arm *armv4_5; struct arm7_9_common *arm7_9; int retval; diff --git a/src/target/xscale.c b/src/target/xscale.c index 04a5f64c1e..1e0ea77530 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -2870,7 +2870,7 @@ static int xscale_init_target(struct command_context_s *cmd_ctx, static int xscale_init_arch_info(target_t *target, struct xscale_common *xscale, struct jtag_tap *tap, const char *variant) { - armv4_5_common_t *armv4_5; + struct arm *armv4_5; uint32_t high_reset_branch, low_reset_branch; int i; diff --git a/src/target/xscale.h b/src/target/xscale.h index 936782cf37..53bf4721c8 100644 --- a/src/target/xscale.h +++ b/src/target/xscale.h @@ -81,7 +81,7 @@ struct xscale_trace struct xscale_common { /* armv4/5 common stuff */ - armv4_5_common_t armv4_5_common; + struct arm armv4_5_common; int common_magic;