From: Tarek BOCHKATI Date: Mon, 2 Mar 2020 12:58:07 +0000 (+0100) Subject: doc: fix OpenRISC target documentation X-Git-Tag: v0.11.0-rc1~374 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=af69f5ad0bb0cd38ad3163a8a3f3602d751c5d6d doc: fix OpenRISC target documentation OpenRISC correct target name is 'or1k' not 'openrisc' http://openocd.zylin.com/3096 introduced a conflict between 'openrisc' and 'ls1_sap' documentations Change-Id: Iedebbf9809300e1272334c5b63d0b31a41062282 Signed-off-by: Tarek BOCHKATI Reviewed-on: http://openocd.zylin.com/5485 Tested-by: jenkins Reviewed-by: Esben Haabendal Reviewed-by: Oleksij Rempel --- diff --git a/doc/openocd.texi b/doc/openocd.texi index e60d26939e..b5692e6534 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4434,10 +4434,10 @@ The current implementation supports eSi-32xx cores. @item @code{mips_m4k} -- a MIPS core @item @code{xscale} -- this is actually an architecture, not a CPU type. It is based on the ARMv5 architecture. -@item @code{openrisc} -- this is an OpenRISC 1000 core. -The current implementation supports three JTAG TAP cores: @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, allowing access to physical memory addresses independently of CPU cores. +@item @code{or1k} -- this is an OpenRISC 1000 core. +The current implementation supports three JTAG TAP cores: @itemize @minus @item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})