From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 9 Oct 2009 06:51:50 +0000 (-0700)
Subject: make PXA255 targets enumerate sort-of-OK
X-Git-Tag: v0.3.0-rc0~116^2
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=60e24aa597cde2703e933759aebff5d3c2dde314

make PXA255 targets enumerate sort-of-OK

Startup now mostly works, except that the initial target state
is "unknown" ... previously, it refused to even start.

Getting that far required fixing the ircapture value (which
can never have been correct!) and the default JTAG clock rate,
then providing custom reset script.

The "reset" command is still iffy.  DCSR updates, and loading
the debug handler, report numerous DR/IR capture failures.
But once that's done, "poll" reports that the CPU is halted
(which it shouldn't be, this was "reset run"!), due to the
rather curious reason "target-not-halted".

Summary:  you still can't debug these parts, but it's closer.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---

diff --git a/NEWS b/NEWS
index 7fe542dbe3..81fce82181 100644
--- a/NEWS
+++ b/NEWS
@@ -39,6 +39,7 @@ Board, Target, and Interface Configuration Scripts:
     Samsung s3c2450
 	Mini2440 board
     Numeric TAP and Target identifiers now trigger warnings
+    PXA255 partially enumerates
 
 Documentation:
     Capture more debugging and setup advice
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 1608d66c88..7137621a43 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -19,8 +19,37 @@ if { [info exists CPUTAPID ] } {
    set _CPUTAPID 0x69264013
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-debug_level 3
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+	-chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+jtag_khz 300
+$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+	# assert both resets; equivalent to power-on reset
+	jtag_reset 1 1
+
+	# drop TRST after at least 32 cycles
+	sleep 1
+	jtag_reset 0 1
+
+	# minimum 32 TCK cycles to wake up the controller
+	runtest 50
+
+	# now the TAP will be responsive; validate scanchain
+	jtag arp_init
+
+	# ... and take it out of reset
+	jtag_reset 0 0
+}
+
+proc jtag_init {} {
+	init_reset startup
+}