From: Karl Kurbjun <kkurbjun@gmail.com>
Date: Sun, 2 Oct 2011 17:41:33 +0000 (-0600)
Subject: AM/DM37x: Use ICEPick warm reset and include halt when gdb connects.
X-Git-Tag: v0.6.0-rc1~532
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=59beb93752c096fdfa0257ec126ee3e650140eec

AM/DM37x: Use ICEPick warm reset and include halt when gdb connects.

Using the ICEPick reset seems to allow the processor to be halted sooner
and the halt on gdb connection makes the connect process more robust.

Change-Id: I0586f6e6becc60a729030509ef58907a19d545ec
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/23
Tested-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
---

diff --git a/tcl/target/amdm37x.cfg b/tcl/target/amdm37x.cfg
index a6daeab91d..b1bd25ce8d 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/amdm37x.cfg
@@ -1,6 +1,6 @@
 #
-# Copyright (C)   2010        by Karl Kurbjun
-# Copyright (C)   2009-2011  by Øyvind Harboe
+# Copyright (C)   2010-2011   by Karl Kurbjun
+# Copyright (C)   2009-2011   by Øyvind Harboe
 # Copyright (C)   2009        by David Brownell
 # Copyright (C)   2009        by Magnus Lundin
 #
@@ -114,7 +114,7 @@ jtag configure $_CHIPNAME.d2d -event tap-enable \
 
 # Primary TAP: ICEpick - it is closest to TDI so last in the chain
 eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
-	
+
 ######
 # End of Chain Description
 ######
@@ -153,30 +153,39 @@ $_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000
 ######
 
 # Set the JTAG clock down to 10 kHz to be sure that it will work with the
-#  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up 
+#  slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
 #  *after* PLL and clock tree setup.
 
 $_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
 
-# Reset needs to be performed in in software.
-# The AM/DM37x TRM (sprugn4b) describes the software reset in detail.
-# PRM_RSTCTRL is described in table 3-425 on page 618.  We assert RST_GS
-# (bit 1 (in 31:0) ) to do a warm reset.
-
-# Create a vaiable for the register address
-set PRM_RSTCTRL 0x48307250
+# Describe the reset assert process for openocd - this is asserted with the
+# ICEPick
+$_TARGETNAME configure -event "reset-assert" {
 
-# Describe the reset assert process: A value of 2 must be written 
-# (assert bit 1) to the physical address of PRM_RSTCTRL.
+   global _CHIPNAME
 
-$_TARGETNAME configure -event \
-   reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
+   # assert warm system reset through ICEPick
+   icepick_c_wreset $_CHIPNAME.jrc
+}
 
 # After the reset is asserted we need to re-initialize debugging and speed up
 # the JTAG clock.
 
-$_TARGETNAME configure -event \
-   reset-assert-post "amdm37x_dbginit $_TARGETNAME; adapter_khz 1000"
+$_TARGETNAME configure -event reset-assert-post {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+   adapter_khz 1000
+}
+
+$_TARGETNAME configure -event gdb-attach {
+
+   global _TARGETNAME
+   amdm37x_dbginit $_TARGETNAME
+
+   echo "Halting target"
+   halt
+}
 
 ######
 # End Target Reset Event Setup:
@@ -192,8 +201,8 @@ $_TARGETNAME configure -event \
 proc amdm37x_dbginit {target} {
    # General Cortex A8 debug initialisation
    cortex_a8 dbginit
-   
-   # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but 
+
+   # Enable DBGEN signal.  This signal is described in the ARM v7 TRM, but
    # access to the signal appears to be implementation specific.  TI does not
    # describe this register much except a quick line that states DBGEM (sic) is
    # at this address and this bit.