From: mifi Date: Fri, 22 Feb 2008 16:13:07 +0000 (+0000) Subject: - added patch to solve problem with AT91SAM7SE MCU have 3, rather than just 2 GPNVM... X-Git-Tag: v0.1.0~972 X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=34bc9457e9190f2a3ec9c3ec4c6888ef1aa7ac63 - added patch to solve problem with AT91SAM7SE MCU have 3, rather than just 2 GPNVM bits. (Thanks to Pavel for the patch) git-svn-id: svn://svn.berlios.de/openocd/trunk@317 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c index 0347742360..f552900d70 100644 --- a/src/flash/at91sam7.c +++ b/src/flash/at91sam7.c @@ -467,8 +467,8 @@ int at91sam7_read_part_info(struct flash_bank_s *bank) if (at91sam7_info->cidr_arch == 0x72 ) { - at91sam7_info->num_nvmbits = 2; - at91sam7_info->nvmbits = (status>>8)&0x03; + at91sam7_info->num_nvmbits = 3; + at91sam7_info->nvmbits = (status>>8)&0x07; bank->base = 0x100000; bank->bus_width = 4; if (bank->size==0x80000) /* AT91SAM7SE512 */ @@ -892,7 +892,7 @@ int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size) } /* -* On AT91SAM7S: When the gpnmv bits are set with +* On AT91SAM7S: When the gpnvm bits are set with * > at91sam7 gpnvm 0 bitnr set * the changes are not visible in the flash controller status register MC_FSR * until the processor has been reset.