From: is2t <devel@is2t.com>
Date: Fri, 7 Dec 2012 07:15:03 +0000 (+0100)
Subject: LPC1788 target configuration file.
X-Git-Tag: v0.7.0-rc1~138
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=1e07f7bb6a3bb667b5401ffd94ac7985d91fb6cc

LPC1788 target configuration file.

Change-Id: I68bd6b7c19d9d1bee13d0921c32b4490e68ab8f2
Signed-off-by: is2t <devel@is2t.com>
Reviewed-on: http://openocd.zylin.com/1002
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
---

diff --git a/tcl/target/lpc1788.cfg b/tcl/target/lpc1788.cfg
new file mode 100644
index 0000000000..16b62c8a1b
--- /dev/null
+++ b/tcl/target/lpc1788.cfg
@@ -0,0 +1,20 @@
+# NXP LPC1788 Cortex-M3 with 512kB Flash and 64kB Local On-Chip SRAM,
+set CHIPNAME lpc1788
+set CPUTAPID 0x4ba00477
+set CPURAMSIZE 0x10000
+set CPUROMSIZE 0x80000
+
+# After reset the chip is clocked by the ~12MHz internal RC oscillator.
+# When board-specific code (reset-init handler or device firmware)
+# configures another oscillator and/or PLL0, set CCLK to match; if
+# you don't, then flash erase and write operations may misbehave.
+# (The ROM code doing those updates cares about core clock speed...)
+#
+# CCLK is the core clock frequency in KHz
+set CCLK 12000
+
+#Include the main configuration file.
+source [find target/lpc17xx.cfg];
+
+# if srst is not fitted, use SYSRESETREQ to perform a soft reset
+cortex_m3 reset_config sysresetreq