From: David Brownell <dbrownell@users.sourceforge.net>
Date: Mon, 7 Dec 2009 22:55:08 +0000 (-0800)
Subject: ARM: don't clone arm_arch_state() code
X-Git-Tag: v0.4.0-rc1~80
X-Git-Url: https://review.openocd.org/gitweb?p=openocd.git;a=commitdiff_plain;h=19ad7f828ba36f398f52749c2f33e25a3ea78ac2

ARM: don't clone arm_arch_state() code

Have various ARM cores delegate to arm_arch_state() to display
basic information, instead of duplicating that logic.

This shrinks the code, makes them all report when semihosting
is active, and highlights which data are specific to this core.
(Like ARM720 not having separate instruction and data caches.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 48f035868e..84c66b8d8a 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -235,14 +235,8 @@ static int arm720t_arch_state(struct target *target)
 
 	armv4_5 = &arm720t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, Cache: %s",
 			 state[arm720t->armv4_5_mmu.mmu_enabled],
 			 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
 
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 217c63c6a7..c5b7c88dcd 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -449,14 +449,8 @@ int arm920t_arch_state(struct target *target)
 
 	armv4_5 = &arm920t->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm920t->armv4_5_mmu.mmu_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c7ef708edf..4ac92a249c 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -505,14 +505,8 @@ int arm926ejs_arch_state(struct target *target)
 
 	armv4_5 = &arm926ejs->arm7_9_common.armv4_5_common;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
 			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 61994dcb7b..ac697da9e7 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -865,15 +865,8 @@ static int xscale_arch_state(struct target *target)
 		return ERROR_INVALID_ARGUMENTS;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
-			"MMU: %s, D-Cache: %s, I-Cache: %s"
-			"%s",
-			 arm_state_strings[armv4_5->core_state],
-			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
-			 arm_mode_name(armv4_5->core_mode),
-			 buf_get_u32(armv4_5->cpsr->value, 0, 32),
-			 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+	arm_arch_state(target);
+	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
 			 state[xscale->armv4_5_mmu.mmu_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
 			 state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],