cfg: add basic support of Freescale i.MX6 series targets 35/1135/2
authorVladimir Zapolskiy <vz@mleia.com>
Fri, 8 Feb 2013 00:12:49 +0000 (02:12 +0200)
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>
Wed, 6 Mar 2013 19:06:06 +0000 (19:06 +0000)
This change adds a simple target configuration for Freescale
single/dual/quad core i.MX6 SoCs, only one core is configured by default.

Change-Id: I853dd27f4c6765b7f731be2ddea82e85d496c6a4
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-on: http://openocd.zylin.com/1135
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
tcl/target/imx6.cfg [new file with mode: 0644]

diff --git a/tcl/target/imx6.cfg b/tcl/target/imx6.cfg
new file mode 100644 (file)
index 0000000..707bab8
--- /dev/null
@@ -0,0 +1,56 @@
+# Freescale i.MX6 series single/dual/quad core processor
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME imx6
+}
+
+# CoreSight Debug Access Port
+if { [info exists DAP_TAPID] } {
+        set _DAP_TAPID $DAP_TAPID
+} else {
+        set _DAP_TAPID 0x4ba00477
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
+        -expected-id $_DAP_TAPID
+
+# SDMA / no IDCODE
+jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f
+
+# System JTAG Controller
+if { [info exists SJC_TAPID] } {
+        set _SJC_TAPID SJC_TAPID
+} else {
+        set _SJC_TAPID 0x0191c01d
+}
+set _SJC_TAPID2 0x2191c01d
+
+jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
+        -expected-id $_SJC_TAPID -expected-id $_SJC_TAPID2
+
+# GDB target: Cortex-A9, using DAP, configuring only one core
+# Base addresses of cores:
+# core 0  -  0x82150000
+# core 1  -  0x82152000
+# core 2  -  0x82154000
+# core 3  -  0x82156000
+set _TARGETNAME $_CHIPNAME.cpu.0
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \
+        -coreid 0 -dbgbase 0x82150000
+
+# some TCK cycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
+
+proc imx6_dbginit {target} {
+        # General Cortex A8/A9 debug initialisation
+        cortex_a8 dbginit
+}
+
+# Slow speed to be sure it will work
+jtag_rclk 1000
+$_TARGETNAME configure -event reset-start { jtag_rclk 1000 }
+
+$_TARGETNAME configure -event reset-assert-post "imx6_dbginit $_TARGETNAME"
+$_TARGETNAME configure -event gdb-attach { halt }

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)