* support has not yet been integrated, affecting Cortex-M parts.
*/
+/**
+ * Indicates what registers are in the ARM state core register set.
+ *
+ * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
+ * on for example ARM7TDMI cores.
+ * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
+ * three more registers are shadowed for "Secure Monitor" mode.
+ * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
+ * which only shadows SP.
+ */
+enum arm_core_type {
+ ARM_CORE_TYPE_STD = -1,
+ ARM_CORE_TYPE_SEC_EXT = 1,
+ ARM_CORE_TYPE_M_PROFILE,
+};
+
/**
* Represent state of an ARM core.
*
/** Support for arm_reg_current() */
const int *map;
- /**
- * Indicates what registers are in the ARM state core register set.
- * ARM_MODE_ANY indicates the standard set of 37 registers,
- * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
- * more registers are shadowed, for "Secure Monitor" mode.
- * ARM_MODE_THREAD indicates a microcontroller profile core,
- * which only shadows SP.
- */
- enum arm_mode core_type;
+ /** Indicates what registers are in the ARM state core register set. */
+ enum arm_core_type core_type;
/** Record the current core mode: SVC, USR, or some other mode. */
enum arm_mode core_mode;
if (!arm11)
return ERROR_FAIL;
- arm11->arm.core_type = ARM_MODE_ANY;
+ arm11->arm.core_type = ARM_CORE_TYPE_STD;
arm_init_arch_info(target, &arm11->arm);
arm11->jtag_info.tap = target->tap;
type = "ARM1156";
break;
case 0x7B76:
- arm11->arm.core_type = ARM_MODE_MON;
+ arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
/* NOTE: could default arm11->hardware_step to true */
type = "ARM1176";
break;
arm7_9->dcc_downloads = false;
arm->arch_info = arm7_9;
- arm->core_type = ARM_MODE_ANY;
+ arm->core_type = ARM_CORE_TYPE_STD;
arm->read_core_reg = arm7_9_read_core_reg;
arm->write_core_reg = arm7_9_write_core_reg;
arm->full_context = arm7_9_full_context;
for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
return ERROR_FAIL;
}
- if (arm->core_type != ARM_MODE_ANY) {
+ if (arm->core_type != ARM_CORE_TYPE_STD) {
command_print(CMD,
"Microcontroller Profile not supported - use standard reg cmd");
return ERROR_OK;
sep = "";
break;
case ARM_MODE_MON:
- if (arm->core_type != ARM_MODE_MON)
+ if (arm->core_type != ARM_CORE_TYPE_SEC_EXT)
continue;
/* FALLTHROUGH */
default:
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m not supported */
command_print(CMD, "Unsupported Command");
return ERROR_OK;
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m is always thumb mode */
thumb = 1;
}
break;
case REG_CLASS_ALL:
- *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ *reg_list_size = (arm->core_type != ARM_CORE_TYPE_SEC_EXT ? 48 : 51);
unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3)
*reg_list_size += 33;
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
if (!(arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON))
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT))
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}
arm->common_magic = ARM_COMMON_MAGIC;
/* core_type may be overridden by subtype logic */
- if (arm->core_type != ARM_MODE_THREAD) {
- arm->core_type = ARM_MODE_ANY;
+ if (arm->core_type != ARM_CORE_TYPE_M_PROFILE) {
+ arm->core_type = ARM_CORE_TYPE_STD;
arm_set_cpsr(arm, ARM_MODE_USR);
}
/* Enable stimulus port #0 by default */
armv7m->trace_config.itm_ter[0] = 1;
- arm->core_type = ARM_MODE_THREAD;
+ arm->core_type = ARM_CORE_TYPE_M_PROFILE;
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
}
}
- armv7a->arm.core_type = ARM_MODE_MON;
+ armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {
/* prepare ARMv4/5 specific information */
arm->arch_info = xscale;
- arm->core_type = ARM_MODE_ANY;
+ arm->core_type = ARM_CORE_TYPE_STD;
arm->read_core_reg = xscale_read_core_reg;
arm->write_core_reg = xscale_write_core_reg;
arm->full_context = xscale_full_context;