# FIXME much of this should be in reset event handlers
proc omap3_dbginit { } {
poll off
- reset
sleep 100
jtag tapenable omap3530.dap
targets
# General Cortex A8 debug initialisation
cortex_a8 dbginit
- # Enable DBGU singal for OMAP353x
+ # Enable DBGU signal for OMAP353x
omap3.cpu mww 0x5401d030 0x00002000
poll on
}
+set PRM_RSTCTRL 0x48307250
+
+omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
+omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+
+
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