Update the arm_checksum_memory and arm_blank_check_memory
algorithms to use a breakpoint instruction on v5 arch.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
/**
* Runs ARM code in the target to calculate a CRC32 checksum.
*
/**
* Runs ARM code in the target to calculate a CRC32 checksum.
*
- * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
*/
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct arm_algorithm armv4_5_info;
*/
int arm_checksum_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *checksum)
{
struct working_area *crc_algorithm;
struct arm_algorithm armv4_5_info;
+ struct arm *armv4_5 = target_to_arm(target);
struct reg_param reg_params[2];
int retval;
uint32_t i;
struct reg_param reg_params[2];
int retval;
uint32_t i;
static const uint32_t arm_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
static const uint32_t arm_crc_code[] = {
0xE1A02000, /* mov r2, r0 */
0xE1540003, /* cmp r4, r3 */
0x1AFFFFF1, /* bne nbyte */
/* end: */
0xE1540003, /* cmp r4, r3 */
0x1AFFFFF1, /* bne nbyte */
/* end: */
- 0xEAFFFFFE, /* b end */
+ 0xe1200070, /* bkpt #0 */
/* CRC32XOR: */
0x04C11DB7 /* .word 0x04C11DB7 */
};
/* CRC32XOR: */
0x04C11DB7 /* .word 0x04C11DB7 */
};
/* 20 second timeout/megabyte */
int timeout = 20000 * (1 + (count / (1024 * 1024)));
/* 20 second timeout/megabyte */
int timeout = 20000 * (1 + (count / (1024 * 1024)));
+ /* armv4 must exit using a hardware breakpoint */
+ if (armv4_5->is_armv4)
+ exit_var = crc_algorithm->address + sizeof(arm_crc_code) - 8;
+
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address,
- crc_algorithm->address + sizeof(arm_crc_code) - 8,
timeout, &armv4_5_info);
if (retval != ERROR_OK) {
LOG_ERROR("error executing ARM crc algorithm");
timeout, &armv4_5_info);
if (retval != ERROR_OK) {
LOG_ERROR("error executing ARM crc algorithm");
* all ones. NOR flash which has been erased, and thus may be written,
* holds all ones.
*
* all ones. NOR flash which has been erased, and thus may be written,
* holds all ones.
*
- * \todo On ARMv5+, rely on BKPT termination for reduced overhead.
*/
int arm_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank)
*/
int arm_blank_check_memory(struct target *target,
uint32_t address, uint32_t count, uint32_t *blank)
struct working_area *check_algorithm;
struct reg_param reg_params[3];
struct arm_algorithm armv4_5_info;
struct working_area *check_algorithm;
struct reg_param reg_params[3];
struct arm_algorithm armv4_5_info;
+ struct arm *armv4_5 = target_to_arm(target);
static const uint32_t check_code[] = {
/* loop: */
static const uint32_t check_code[] = {
/* loop: */
0xe2511001, /* subs r1, r1, #1 */
0x1afffffb, /* bne loop */
/* end: */
0xe2511001, /* subs r1, r1, #1 */
0x1afffffb, /* bne loop */
/* end: */
+ 0xe1200070, /* bkpt #0 */
};
/* make sure we have a working area */
};
/* make sure we have a working area */
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
init_reg_param(®_params[2], "r2", 32, PARAM_IN_OUT);
buf_set_u32(reg_params[2].value, 0, 32, 0xff);
+ /* armv4 must exit using a hardware breakpoint */
+ if (armv4_5->is_armv4)
+ exit_var = check_algorithm->address + sizeof(check_code) - 4;
+
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
check_algorithm->address,
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
check_algorithm->address,
- check_algorithm->address + sizeof(check_code) - 4,
10000, &armv4_5_info);
if (retval != ERROR_OK) {
destroy_reg_param(®_params[0]);
10000, &armv4_5_info);
if (retval != ERROR_OK) {
destroy_reg_param(®_params[0]);
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