ARM11: ETM + ETB support
authorDavid Brownell <dbrownell@users.sourceforge.net>
Sat, 14 Nov 2009 00:58:14 +0000 (16:58 -0800)
committerDavid Brownell <dbrownell@users.sourceforge.net>
Sat, 14 Nov 2009 00:58:14 +0000 (16:58 -0800)
Kick in ETM (and ETB) support for ARM11.  Tested on OMAP 2420,
so update that configuration.  (That's an ARM1136ejs, ETB,
OpenGL ES1.1, C55x DSP, etc.)

Also update the other ARM11 ETM + ETB targets in the tree
to set up these modules.  (Not tested.)

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
src/target/arm11.c
tcl/target/imx31.cfg
tcl/target/imx35.cfg
tcl/target/omap2420.cfg
tcl/target/samsung_s3c6410.cfg

index b30e5181a87db7f820430aa47efb50e54e8ea918..7a30bc7fab44e69c8c533e49e554b76704997340 100644 (file)
@@ -1898,6 +1898,20 @@ static int arm11_examine(struct target *target)
        if (retval != ERROR_OK)
                return retval;
 
+       /* ETM on ARM11 still uses original scanchain 6 access mode */
+       if (arm11->arm.etm && !target_was_examined(target)) {
+               *register_get_last_cache_p(&target->reg_cache) =
+                       etm_build_reg_cache(target, &arm11->jtag_info,
+                                       arm11->arm.etm);
+               retval = etm_setup(target);
+       }
+
+       /* FIXME this sets a flag in the (shared) arm11_target structure,
+        * not in the (per-cpu) "target" structure ... so it's clearly
+        * wrong in the case of e.g. two different ARM11 chips on the
+        * same board.  (Maybe ARM11 MPCore works though.)  Whoever calls
+        * the examine() method should set a target-specific flag...
+        */
        target_set_examined(target);
 
        return ERROR_OK;
@@ -2212,5 +2226,5 @@ int arm11_register_commands(struct command_context *cmd_ctx)
                        arm11_handle_vcr, COMMAND_ANY,
                        "Control (Interrupt) Vector Catch Register");
 
-       return ERROR_OK;
+       return etm_register_commands(cmd_ctx);
 }
index 9a2aed3222cbfec91c4074ed7c51e00489589754..b613ba6fce471f00ddbf6ecda9c507a98cf56259 100644 (file)
@@ -60,3 +60,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 proc power_restore {} { puts "Sensed power restore. No action." }
 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
index b899084fdbfc3f593688c28010b839c1cf0c8878..d47abdc69208ef88bec435ac30183838ebed739e 100644 (file)
@@ -48,3 +48,7 @@ target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
 
 proc power_restore {} { puts "Sensed power restore. No action." }
 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
index a579866ec331efd4e0e7a698b25a09d54e94ec9b..5cf47b21398b082bb988f5e89df843bda1955f95 100644 (file)
@@ -49,7 +49,6 @@ $_TARGETNAME configure -work-area-phys 0x40210000
 $_TARGETNAME configure -work-area-size 0x00081000
 $_TARGETNAME configure -work-area-backup 0
 
-# trace setup
-# REVISIT ... as of 12-June-2009, OpenOCD's ETM code can't talk to ARM11 cores.
-#etm config $_TARGETNAME 16 normal full etb
-#etb config $_TARGETNAME $_CHIPNAME.etb
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
index e451fd64a60e59b015cd8073190e93b2f4e00cf9..91371991d9fa1d0c24da7bbff3a7a5b204e0c4a9 100644 (file)
@@ -47,3 +47,7 @@ jtag_ntrst_delay 500
 
 #reset configuration
 reset_config trst_and_srst
+
+# trace setup ... NOTE, "normal full" mode fudges the real ETMv3.1 mode
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb

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