aarch64: add cache handling functions

For now only D-Cache flush (Clean&Invalidate) and I-Cache
invalidate are implemented. That's enough for software breakpoints.

Change-Id: I8e96d645a230b51e3490403f4564e59ba6a76cf3
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index c20ac0f03a99b1bca8f0c18dfb51c8025cbddf6e..0021f44d543802231d38eb03f56d33e222c02948 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -76,7 +76,8 @@ ARMV7_SRC = \
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
        %D%/aarch64.c \
 ARMV8_SRC = \
        %D%/armv8_dpm.c \
        %D%/aarch64.c \

-       %D%/armv8.c
+       %D%/armv8.c \
+       %D%/armv8_cache.c

 
 ARM_DEBUG_SRC = \
        %D%/arm_dpm.c \
 
 ARM_DEBUG_SRC = \
        %D%/arm_dpm.c \


@@ -158,6 +159,7 @@ INTEL_IA32_SRC = \
        %D%/armv8.h \
        %D%/armv8_dpm.h \
        %D%/armv8_opcodes.h \
        %D%/armv8.h \
        %D%/armv8_dpm.h \
        %D%/armv8_opcodes.h \

+       %D%/armv8_cache.h \

        %D%/avrt.h \
        %D%/dsp563xx.h \
        %D%/dsp563xx_once.h \
        %D%/avrt.h \
        %D%/dsp563xx.h \
        %D%/dsp563xx_once.h \

diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
new file mode 100644 (file)
index 0000000..fb18804
--- /dev/null
+++ b/src/target/armv8_cache.c
@@ -0,0 +1,122 @@
+/***************************************************************************
+ *   Copyright (C) 2016 by Matthias Welwarsky                              *
+ *   matthias.welwarsky@sysgo.com                                          *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "armv8_cache.h"
+#include "armv8_dpm.h"
+#include "armv8_opcodes.h"
+
+static int armv8_d_cache_sanity_check(struct armv8_common *armv8)
+{
+       struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
+
+       if (armv8_cache->d_u_cache_enabled)
+               return ERROR_OK;
+
+       return ERROR_TARGET_INVALID;
+}
+
+static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
+{
+       struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
+
+       if (armv8_cache->i_cache_enabled)
+               return ERROR_OK;
+
+       return ERROR_TARGET_INVALID;
+}
+
+int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
+{
+       struct arm_dpm *dpm = armv8->arm.dpm;
+       struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
+       uint64_t linelen = armv8_cache->d_u_size.linelen;
+       target_addr_t va_line, va_end;
+       int retval;
+
+       retval = armv8_d_cache_sanity_check(armv8);
+       if (retval != ERROR_OK)
+               return retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               goto done;
+
+       va_line = va & (-linelen);
+       va_end = va + size;
+
+       while (va_line < va_end) {
+               /* DC CIVAC */
+               /* Aarch32: DCCIMVAC: ARMV4_5_MCR(15, 0, 0, 7, 14, 1) */
+               retval = dpm->instr_write_data_r0_64(dpm,
+                               ARMV8_SYS(SYSTEM_DCCIVAC, 0), va_line);
+               if (retval != ERROR_OK)
+                       goto done;
+               va_line += linelen;
+       }
+
+       dpm->finish(dpm);
+       return retval;
+
+done:
+       LOG_ERROR("d-cache invalidate failed");
+       dpm->finish(dpm);
+
+       return retval;
+}
+
+int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
+{
+       struct arm_dpm *dpm = armv8->arm.dpm;
+       struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
+       uint64_t linelen = armv8_cache->i_size.linelen;
+       target_addr_t va_line, va_end;
+       int retval;
+
+       retval = armv8_i_cache_sanity_check(armv8);
+       if (retval != ERROR_OK)
+               return retval;
+
+       retval = dpm->prepare(dpm);
+       if (retval != ERROR_OK)
+               goto done;
+
+       va_line = va & (-linelen);
+       va_end = va + size;
+
+       while (va_line < va_end) {
+               /* IC IVAU - Invalidate instruction cache by VA to PoU. */
+               retval = dpm->instr_write_data_r0_64(dpm,
+                               ARMV8_SYS(SYSTEM_ICIVAU, 0), va_line);
+               if (retval != ERROR_OK)
+                       goto done;
+               va_line += linelen;
+       }
+
+       dpm->finish(dpm);
+       return retval;
+
+done:
+       LOG_ERROR("d-cache invalidate failed");
+       dpm->finish(dpm);
+
+       return retval;
+}

diff --git a/src/target/armv8_cache.h b/src/target/armv8_cache.h
new file mode 100644 (file)
index 0000000..fa46e16
--- /dev/null
+++ b/src/target/armv8_cache.h
@@ -0,0 +1,26 @@
+/***************************************************************************
+ *   Copyright (C) 2016 by Matthias Welwarsky                              *
+ *   matthias.welwarsky@sysgo.com                                          *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+#ifndef OPENOCD_TARGET_ARMV8_CACHE_H_
+#define OPENOCD_TARGET_ARMV8_CACHE_H_
+
+#include "armv8.h"
+
+extern int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size);
+extern int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va, size_t size);
+
+#endif /* OPENOCD_TARGET_ARMV8_CACHE_H_ */

diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index a1fb5d4d0018711d5a5716ab2d9f7398989ea394..89d7440a8769734d3d183014ccd468f6fcd72810 100644 (file)
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -82,6 +82,7 @@
 #define SYSTEM_DCCSW                   0b0100001111010010
 #define SYSTEM_ICIVAU                  0b0101101110101001
 #define SYSTEM_DCCVAU                  0b0101101111011001
 #define SYSTEM_DCCSW                   0b0100001111010010
 #define SYSTEM_ICIVAU                  0b0101101110101001
 #define SYSTEM_DCCVAU                  0b0101101111011001

+#define SYSTEM_DCCIVAC                 0b0101101111110001

 
 #define SYSTEM_MPIDR                   0b1100000000000101
 
 
 #define SYSTEM_MPIDR                   0b1100000000000101
 


@@ -125,5 +126,6 @@
 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
 
 #define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
 #define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
 

+#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)

 
 #endif /* __ARM_OPCODES_H */
 
 #endif /* __ARM_OPCODES_H */