flash/stm32l4x: introduce table with register offsets

This change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.

flash_regs table is introduced within stm32l4_flash_bank struct in order
to get correct register offsets, by using the driver internal function
'stm32l4_get_flash_reg_by_index'.

To use efficiently register indexes, stm32l4 _[get|read|write]_flash_reg
functions are surcharged to accept register indexes.

IMPORTANT: stm32l4_write_option is not surcharged, and they always accept
the option register offset.

tested on NUCLEO-G474RE and STM32L4R9I-DISCO

Change-Id: I739d3e97d63b831af6aa569c5629db0000209551
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5509
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 9bdc2dbcad78dbceef063b5d3a906a92375e51f4..ca8a3b81de6f5fcc889feb9e5e4e519dc7c2e0d2 100644 (file)
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -81,8 +81,7 @@
  * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
  */
 
-/*
- * STM32G0xxx series for reference.
+/* STM32G0xxx series for reference.
  *
  * RM0444 (STM32G0x1)
  * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
@@ -91,8 +90,7 @@
  * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
  */
 
-/*
- * STM32G4xxx series for reference.
+/* STM32G4xxx series for reference.
  *
  * RM0440 (STM32G43x/44x/47x/48x/49x/4Ax)
  * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
@@ -112,6 +110,33 @@
 
 #define FLASH_ERASE_TIMEOUT 250
 
+enum stm32l4_flash_reg_index {
+       STM32_FLASH_ACR_INDEX,
+       STM32_FLASH_KEYR_INDEX,
+       STM32_FLASH_OPTKEYR_INDEX,
+       STM32_FLASH_SR_INDEX,
+       STM32_FLASH_CR_INDEX,
+       STM32_FLASH_OPTR_INDEX,
+       STM32_FLASH_WRP1AR_INDEX,
+       STM32_FLASH_WRP1BR_INDEX,
+       STM32_FLASH_WRP2AR_INDEX,
+       STM32_FLASH_WRP2BR_INDEX,
+       STM32_FLASH_REG_INDEX_NUM,
+};
+
+static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
+       [STM32_FLASH_ACR_INDEX]      = 0x000,
+       [STM32_FLASH_KEYR_INDEX]     = 0x008,
+       [STM32_FLASH_OPTKEYR_INDEX]  = 0x00C,
+       [STM32_FLASH_SR_INDEX]       = 0x010,
+       [STM32_FLASH_CR_INDEX]       = 0x014,
+       [STM32_FLASH_OPTR_INDEX]     = 0x020,
+       [STM32_FLASH_WRP1AR_INDEX]   = 0x02C,
+       [STM32_FLASH_WRP1BR_INDEX]   = 0x030,
+       [STM32_FLASH_WRP2AR_INDEX]   = 0x04C,
+       [STM32_FLASH_WRP2BR_INDEX]   = 0x050,
+};
+
 struct stm32l4_rev {
        const uint16_t rev;
        const char *str;
@@ -125,6 +150,7 @@ struct stm32l4_part_info {
        const uint16_t max_flash_size_kb;
        const bool has_dual_bank;
        const uint32_t flash_regs_base;
+       const uint32_t *default_flash_regs;
        const uint32_t fsize_addr;
 };
 
@@ -137,10 +163,11 @@ struct stm32l4_flash_bank {
        uint32_t user_bank_size;
        uint32_t wrpxxr_mask;
        const struct stm32l4_part_info *part_info;
+       const uint32_t *flash_regs;
 };
 
-/* human readable list of families this drivers supports */
-static const char *device_families = "STM32L4/L4+/WB/WL/G4/G0";
+/* human readable list of families this drivers supports (sorted alphabetically) */
+static const char *device_families = "STM32G0/G4/L4/L4+/WB/WL";
 
 static const struct stm32l4_rev stm32_415_revs[] = {
        { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
@@ -211,6 +238,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 1024,
          .has_dual_bank         = true,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -221,6 +249,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 256,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -231,6 +260,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 128,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -241,6 +271,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 1024,
          .has_dual_bank         = true,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -251,6 +282,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 512,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -261,6 +293,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 128,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -271,6 +304,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 64,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -281,6 +315,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 128,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -291,6 +326,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 512,
          .has_dual_bank         = true,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -301,6 +337,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 2048,
          .has_dual_bank         = true,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -311,6 +348,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 1024,
          .has_dual_bank         = true,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -321,6 +359,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 512,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x40022000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -331,6 +370,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 1024,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x58004000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -341,6 +381,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 512,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x58004000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
        {
@@ -351,6 +392,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .max_flash_size_kb     = 256,
          .has_dual_bank         = false,
          .flash_regs_base       = 0x58004000,
+         .default_flash_regs    = stm32l4_flash_regs,
          .fsize_addr            = 0x1FFF75E0,
        },
 };
@@ -384,16 +426,37 @@ static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t r
        return stm32l4_info->part_info->flash_regs_base + reg_offset;
 }
 
+static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
+       enum stm32l4_flash_reg_index reg_index)
+{
+       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+       return stm32l4_get_flash_reg(bank, stm32l4_info->flash_regs[reg_index]);
+}
+
 static inline int stm32l4_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
 {
        return target_read_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 }
 
+static inline int stm32l4_read_flash_reg_by_index(struct flash_bank *bank,
+       enum stm32l4_flash_reg_index reg_index, uint32_t *value)
+{
+       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+       return stm32l4_read_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
+}
+
 static inline int stm32l4_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
 {
        return target_write_u32(bank->target, stm32l4_get_flash_reg(bank, reg_offset), value);
 }
 
+static inline int stm32l4_write_flash_reg_by_index(struct flash_bank *bank,
+       enum stm32l4_flash_reg_index reg_index, uint32_t value)
+{
+       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+       return stm32l4_write_flash_reg(bank, stm32l4_info->flash_regs[reg_index], value);
+}
+
 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 {
        uint32_t status;
@@ -401,7 +464,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 
        /* wait for busy to clear */
        for (;;) {
-               retval = stm32l4_read_flash_reg(bank, STM32_FLASH_SR, &status);
+               retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
                if (retval != ERROR_OK)
                        return retval;
                LOG_DEBUG("status: 0x%" PRIx32 "", status);
@@ -427,7 +490,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
                /* If this operation fails, we ignore it and report the original
                 * retval
                 */
-               stm32l4_write_flash_reg(bank, STM32_FLASH_SR, status & FLASH_ERROR);
+               stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, status & FLASH_ERROR);
        }
 
        return retval;
@@ -440,7 +503,7 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
        /* first check if not already unlocked
         * otherwise writing on STM32_FLASH_KEYR will fail
         */
-       int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+       int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
        if (retval != ERROR_OK)
                return retval;
 
@@ -448,15 +511,15 @@ static int stm32l4_unlock_reg(struct flash_bank *bank)
                return ERROR_OK;
 
        /* unlock flash registers */
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY1);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY1);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_KEYR, KEY2);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_KEYR_INDEX, KEY2);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+       retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
        if (retval != ERROR_OK)
                return retval;
 
@@ -472,7 +535,7 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
 {
        uint32_t ctrl;
 
-       int retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+       int retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
        if (retval != ERROR_OK)
                return retval;
 
@@ -480,15 +543,15 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
                return ERROR_OK;
 
        /* unlock option registers */
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY1);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY1);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_OPTKEYR, OPTKEY2);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_OPTKEYR_INDEX, OPTKEY2);
        if (retval != ERROR_OK)
                return retval;
 
-       retval = stm32l4_read_flash_reg(bank, STM32_FLASH_CR, &ctrl);
+       retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, &ctrl);
        if (retval != ERROR_OK)
                return retval;
 
@@ -524,14 +587,14 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
        if (retval != ERROR_OK)
                goto err_lock;
 
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OPTSTRT);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OPTSTRT);
        if (retval != ERROR_OK)
                goto err_lock;
 
        retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 
 err_lock:
-       retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK | FLASH_OPTLOCK);
+       retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
 
        if (retval != ERROR_OK)
                return retval;
@@ -544,11 +607,11 @@ static int stm32l4_protect_check(struct flash_bank *bank)
        struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
 
        uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
-       stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
-       stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
+       stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1AR_INDEX, &wrp1ar);
+       stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP1BR_INDEX, &wrp1br);
        if (stm32l4_info->part_info->has_dual_bank) {
-               stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
-               stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
+               stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2AR_INDEX, &wrp2ar);
+               stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_WRP2BR_INDEX, &wrp2br);
        } else {
                /* prevent uninitialized errors */
                wrp2ar = 0;
@@ -627,7 +690,7 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
                        erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
                } else
                        erase_flags |= i << FLASH_PAGE_SHIFT;
-               retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, erase_flags);
+               retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, erase_flags);
                if (retval != ERROR_OK)
                        break;
 
@@ -639,7 +702,7 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
        }
 
 err_lock:
-       retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+       retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
 
        if (retval != ERROR_OK)
                return retval;
@@ -667,7 +730,7 @@ static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first,
                        reg_value = ((last & 0xFF) << 16) | begin;
                }
 
-               ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
+               ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP2AR_INDEX], reg_value, 0xffffffff);
        }
        /* Bank 1 */
        reg_value = 0xFF; /* Default to bank un-protected */
@@ -677,7 +740,7 @@ static int stm32l4_protect(struct flash_bank *bank, int set, unsigned int first,
                        reg_value = (end << 16) | (first & 0xFF);
                }
 
-               ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
+               ret = stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_WRP1AR_INDEX], reg_value, 0xffffffff);
        }
 
        return ret;
@@ -743,8 +806,8 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
        buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
        buf_set_u32(reg_params[2].value, 0, 32, address);
        buf_set_u32(reg_params[3].value, 0, 32, count);
-       buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_SR));
-       buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg(bank, STM32_FLASH_CR));
+       buf_set_u32(reg_params[4].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX));
+       buf_set_u32(reg_params[5].value, 0, 32, stm32l4_get_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX));
 
        retval = target_run_flash_async_algorithm(target, buffer, count, 8,
                        0, NULL,
@@ -764,7 +827,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
                if (error != 0) {
                        LOG_ERROR("flash write failed = %08" PRIx32, error);
                        /* Clear but report errors */
-                       stm32l4_write_flash_reg(bank, STM32_FLASH_SR, error);
+                       stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, error);
                        retval = ERROR_FAIL;
                }
        }
@@ -841,7 +904,7 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
        retval = stm32l4_write_block(bank, buffer, offset, count / 8);
 
 err_lock:
-       retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+       retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
 
        if (retval != ERROR_OK) {
                LOG_ERROR("block write failed");
@@ -896,6 +959,7 @@ static int stm32l4_probe(struct flash_bank *bank)
        }
 
        part_info = stm32l4_info->part_info;
+       stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
 
        char device_info[1024];
        retval = bank->driver->info(bank, device_info, sizeof(device_info));
@@ -929,7 +993,7 @@ static int stm32l4_probe(struct flash_bank *bank)
        assert((flash_size_kb != 0xffff) && flash_size_kb);
 
        /* read flash option register */
-       retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
+       retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_OPTR_INDEX, &options);
        if (retval != ERROR_OK)
                return retval;
 
@@ -1150,18 +1214,18 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
        if (retval != ERROR_OK)
                goto err_lock;
 
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action);
        if (retval != ERROR_OK)
                goto err_lock;
 
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, action | FLASH_STRT);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, action | FLASH_STRT);
        if (retval != ERROR_OK)
                goto err_lock;
 
        retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
 
 err_lock:
-       retval2 = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_LOCK);
+       retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
 
        if (retval != ERROR_OK)
                return retval;
@@ -1274,7 +1338,7 @@ COMMAND_HANDLER(stm32l4_handle_option_load_command)
         * "Note: If the read protection is set while the debugger is still
         * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
         */
-       retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBL_LAUNCH);
+       retval = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_OBL_LAUNCH);
 
        command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
 
@@ -1305,7 +1369,8 @@ COMMAND_HANDLER(stm32l4_handle_lock_command)
        }
 
        /* set readout protection level 1 by erasing the RDP option byte */
-       if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
+       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+       if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX], 0, 0x000000FF) != ERROR_OK) {
                command_print(CMD, "%s failed to lock device", bank->driver->name);
                return ERROR_OK;
        }
@@ -1332,7 +1397,9 @@ COMMAND_HANDLER(stm32l4_handle_unlock_command)
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
+       struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+       if (stm32l4_write_option(bank, stm32l4_info->flash_regs[STM32_FLASH_OPTR_INDEX],
+                       RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
                command_print(CMD, "%s failed to unlock device", bank->driver->name);
                return ERROR_OK;
        }

diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index abd8010fc7fe6aa6f5f62a62e69b22568fdab4a4..3e810a03ce7ef034b6e4fa6e41093d6edc7e0fcc 100644 (file)
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -19,18 +19,6 @@
 #ifndef OPENOCD_FLASH_NOR_STM32L4X
 #define OPENOCD_FLASH_NOR_STM32L4X
 
-/* Flash registers offsets */
-#define STM32_FLASH_ACR                        0x00
-#define STM32_FLASH_KEYR               0x08
-#define STM32_FLASH_OPTKEYR            0x0c
-#define STM32_FLASH_SR                 0x10
-#define STM32_FLASH_CR                 0x14
-#define STM32_FLASH_OPTR               0x20
-#define STM32_FLASH_WRP1AR             0x2c
-#define STM32_FLASH_WRP1BR             0x30
-#define STM32_FLASH_WRP2AR             0x4c
-#define STM32_FLASH_WRP2BR             0x50
-
 /* FLASH_CR register bits */
 #define FLASH_PG                               (1 << 0)
 #define FLASH_PER                              (1 << 1)