Correct ZynqMP configuration to be appropriately named

The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

diff --git a/tcl/board/avnet_ultrazed-eg.cfg b/tcl/board/avnet_ultrazed-eg.cfg
index a0ac5c6a743b21bbea77c96263b00d69dcb22eb2..9879bfcb15e3ec7468cdaa6038ba613d2a702bf6 100644 (file)
--- a/tcl/board/avnet_ultrazed-eg.cfg
+++ b/tcl/board/avnet_ultrazed-eg.cfg
@@ -1,6 +1,6 @@
 #
 # AVNET UltraZED EG StarterKit
-# UlraScale-EG plus IO Carrier with on-board digilent smt2
+# ZynqMP UlraScale-EG plus IO Carrier with on-board digilent smt2
 #
 source [find interface/ftdi/digilent_jtag_smt2_nc.cfg]
 # jtag transport only
@@ -13,4 +13,4 @@ adapter_khz 1000
 
 set CHIPNAME uscale
 
-source [find target/xilinx_ultrascale.cfg]
+source [find target/xilinx_zynqmp.cfg]

diff --git a/tcl/target/xilinx_ultrascale.cfg b/tcl/target/xilinx_zynqmp.cfg
similarity index 75%
rename from tcl/target/xilinx_ultrascale.cfg
rename to tcl/target/xilinx_zynqmp.cfg
index 9056c976ef3891057cdce88b6ebdee069c3b47cb..9be781cd8f72e9dd0caad666a55df3d46c93fed0 100644 (file)
--- a/tcl/target/xilinx_ultrascale.cfg
+++ b/tcl/target/xilinx_zynqmp.cfg
@@ -1,6 +1,6 @@
 #
 # target configuration for
-# Xilinx UltraScale+
+# Xilinx ZynqMP (UltraScale+ / A53)
 #
 if { [info exists CHIPNAME] } {
     set _CHIPNAME $CHIPNAME
@@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } {
 }
 
 #
-# DAP tap
+# DAP tap (Quard core A53)
 #
 if { [info exists DAP_TAPID] } {
     set _DAP_TAPID $DAP_TAPID
@@ -21,18 +21,29 @@ jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DA
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
 
 #
-# PS tap
+# PS tap (UltraScale+)
 #
 if { [info exists PS_TAPID] } {
     set _PS_TAPID $PS_TAPID
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
 } else {
-    set _PS_TAPID 0x04710093
+    # FPGA Programmable logic. Values take from Table 39-1 in UG1085:
+    jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -ignore-version \
+        -expected-id 0x04711093 \
+        -expected-id 0x04710093 \
+        -expected-id 0x04721093 \
+        -expected-id 0x04720093 \
+        -expected-id 0x04739093 \
+        -expected-id 0x04730093 \
+        -expected-id 0x04738093 \
+        -expected-id 0x04740093 \
+        -expected-id 0x04750093 \
+        -expected-id 0x04759093 \
+        -expected-id 0x04758093
 }
 
 set jtag_configured 0
 
-jtag newtap $_CHIPNAME ps -irlen 12 -ircapture 0x1 -irmask 0x03 -expected-id $_PS_TAPID
-
 jtag configure $_CHIPNAME.ps -event setup {
     global _CHIPNAME
     global jtag_configured