rclk = 4MHz oon lpc1768, the correct JTAG clk is 666MHz(4MHz/6).
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
# JTAG clock should be CCLK/6 (unless using adaptive clocking)
# CCLK is 4 MHz after reset, and until board-specific code (like
# a reset-init handler) speeds it up.
-jtag_rclk [ expr 4000 / 6 ]
-$_TARGETNAME configure -event reset-start { jtag_rclk [ expr 4000 / 6] }
+#
+# Although rclk "appears to work", it turns out that this yields
+# 4MHz whereas the "correct" rate is CCLK/6, which is not what
+# you get with rclk.
+jtag_khz [ expr 4000 / 6 ]
+
$_TARGETNAME configure -event reset-init {
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