Remove misleading typedef and redundant suffix from struct reg.
28 files changed:
* The format of reg->value is little endian
*
*/
* The format of reg->value is little endian
*
*/
-void gdb_str_to_target(target_t *target, char *tstr, reg_t *reg)
+void gdb_str_to_target(target_t *target, char *tstr, struct reg *reg)
int gdb_get_registers_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
{
int gdb_get_registers_packet(struct connection *connection, target_t *target, char* packet, int packet_size)
{
int reg_list_size;
int retval;
int reg_packet_size = 0;
int reg_list_size;
int retval;
int reg_packet_size = 0;
int gdb_set_registers_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
{
int i;
int gdb_set_registers_packet(struct connection *connection, target_t *target, char *packet, int packet_size)
{
int i;
int reg_list_size;
int retval;
char *packet_p;
int reg_list_size;
int retval;
char *packet_p;
- /* free reg_t *reg_list[] array allocated by get_gdb_reg_list */
+ /* free struct reg *reg_list[] array allocated by get_gdb_reg_list */
free(reg_list);
gdb_put_packet(connection, "OK", 2);
free(reg_list);
gdb_put_packet(connection, "OK", 2);
{
char *reg_packet;
int reg_num = strtoul(packet + 1, NULL, 16);
{
char *reg_packet;
int reg_num = strtoul(packet + 1, NULL, 16);
int reg_list_size;
int retval;
int reg_list_size;
int retval;
char *separator;
uint8_t *bin_buf;
int reg_num = strtoul(packet + 1, &separator, 16);
char *separator;
uint8_t *bin_buf;
int reg_num = strtoul(packet + 1, &separator, 16);
int reg_list_size;
int retval;
struct reg_arch_type *arch_type;
int reg_list_size;
int retval;
struct reg_arch_type *arch_type;
static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
static uint8_t arm11_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-static reg_t arm11_gdb_dummy_fp_reg =
+static struct reg arm11_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
{
"GDB dummy floating-point register", arm11_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t arm11_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-static reg_t arm11_gdb_dummy_fps_reg =
+static struct reg arm11_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
{
"GDB dummy floating-point status register", arm11_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
uint32_t address, int handle_breakpoints);
/* helpers */
static int arm11_build_reg_cache(target_t *target);
uint32_t address, int handle_breakpoints);
/* helpers */
static int arm11_build_reg_cache(target_t *target);
-static int arm11_set_reg(reg_t *reg, uint8_t *buf);
-static int arm11_get_reg(reg_t *reg);
+static int arm11_set_reg(struct reg *reg, uint8_t *buf);
+static int arm11_get_reg(struct reg *reg);
static void arm11_record_register_history(struct arm11_common * arm11);
static void arm11_dump_reg_changes(struct arm11_common * arm11);
static void arm11_record_register_history(struct arm11_common * arm11);
static void arm11_dump_reg_changes(struct arm11_common * arm11);
/* target register access for gdb */
static int arm11_get_gdb_reg_list(struct target_s *target,
/* target register access for gdb */
static int arm11_get_gdb_reg_list(struct target_s *target,
- struct reg_s **reg_list[], int *reg_list_size)
+ struct reg **reg_list[], int *reg_list_size)
{
FNC_INFO;
struct arm11_common * arm11 = target->arch_info;
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
{
FNC_INFO;
struct arm11_common * arm11 = target->arch_info;
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
- *reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
+ *reg_list = malloc(sizeof(struct reg*) * ARM11_GDB_REGISTER_COUNT);
for (size_t i = 16; i < 24; i++)
{
for (size_t i = 16; i < 24; i++)
{
// Set register parameters
for (int i = 0; i < num_reg_params; i++)
{
// Set register parameters
for (int i = 0; i < num_reg_params; i++)
{
- reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
{
if (reg_params[i].direction != PARAM_OUT)
{
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
/** Load a register that is marked !valid in the register cache */
/** Load a register that is marked !valid in the register cache */
-static int arm11_get_reg(reg_t *reg)
+static int arm11_get_reg(struct reg *reg)
}
/** Change a value in the register cache */
}
/** Change a value in the register cache */
-static int arm11_set_reg(reg_t *reg, uint8_t *buf)
+static int arm11_set_reg(struct reg *reg, uint8_t *buf)
struct arm11_common *arm11 = target->arch_info;
NEW(struct reg_cache, cache, 1);
struct arm11_common *arm11 = target->arch_info;
NEW(struct reg_cache, cache, 1);
- NEW(reg_t, reg_list, ARM11_REGCACHE_COUNT);
+ NEW(struct reg, reg_list, ARM11_REGCACHE_COUNT);
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
if (arm11_regs_arch_type == -1)
NEW(struct arm11_reg_state, arm11_reg_states, ARM11_REGCACHE_COUNT);
if (arm11_regs_arch_type == -1)
for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
- reg_t * r = reg_list + i;
+ struct reg * r = reg_list + i;
const struct arm11_reg_defs * rd = arm11_reg_defs + i;
struct arm11_reg_state * rs = arm11_reg_states + i;
const struct arm11_reg_defs * rd = arm11_reg_defs + i;
struct arm11_reg_state * rs = arm11_reg_states + i;
/** \name Shadow registers to save processor state */
/*@{*/
/** \name Shadow registers to save processor state */
/*@{*/
- reg_t * reg_list; /**< target register list */
+ struct reg * reg_list; /**< target register list */
uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
uint32_t reg_values[ARM11_REGCACHE_COUNT]; /**< data for registers */
/*@}*/
{
int retval = ERROR_OK;
struct arm720t_common *arm720t = target_to_arm720(target);
{
int retval = ERROR_OK;
struct arm720t_common *arm720t = target_to_arm720(target);
- reg_t *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
+ struct reg *dbg_stat = &arm720t->arm7tdmi_common.arm7_9_common
.eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
.arm7_9_common.armv4_5_common;
.eice_cache->reg_list[EICE_DBG_STAT];
struct armv4_5_common_s *armv4_5 = &arm720t->arm7tdmi_common
.arm7_9_common.armv4_5_common;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
/* set RESTART instruction */
jtag_set_end_state(TAP_IDLE);
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
return ERROR_OK;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- reg_t *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
+ struct reg *dcc_control = &arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL];
if (!target->dbg_msg_enabled)
return ERROR_OK;
if (!target->dbg_msg_enabled)
return ERROR_OK;
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* read debug status register */
embeddedice_read_reg(dbg_stat);
/* read debug status register */
embeddedice_read_reg(dbg_stat);
- reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
+ struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
uint32_t t=*((uint32_t *)reg->value);
if (t != 0)
{
uint32_t t=*((uint32_t *)reg->value);
if (t != 0)
{
int arm7_9_clear_halt(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
int arm7_9_clear_halt(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
/* we used DBGRQ only if we didn't come out of reset */
if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
/* we used DBGRQ only if we didn't come out of reset */
if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
}
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
}
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
target_state_name(target));
LOG_DEBUG("target->state: %s",
target_state_name(target));
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
int retval;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
#ifdef _DEBUG_ARM7_9_
LOG_DEBUG("-");
#ifdef _DEBUG_ARM7_9_
LOG_DEBUG("-");
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct armv4_5_core_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
int i, j;
struct armv4_5_core_reg *reg_arch_info;
enum armv4_5_mode current_mode = armv4_5->core_mode;
int i, j;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct breakpoint *breakpoint = target->breakpoints;
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err, retval = ERROR_OK;
LOG_DEBUG("-");
int err, retval = ERROR_OK;
LOG_DEBUG("-");
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
uint32_t reg[16];
uint32_t num_accesses = 0;
uint32_t reg[16];
uint32_t num_accesses = 0;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm920t_common *arm920t = target_to_arm920(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
{
if ((retval = target_halt(target)) != ERROR_OK)
{
static int arm926ejs_examine_debug_reason(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
static int arm926ejs_examine_debug_reason(target_t *target)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
int debug_reason;
int retval;
int debug_reason;
int retval;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm926ejs_common *arm926ejs = target_to_arm926(target);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
if ((retval = target_halt(target)) != ERROR_OK)
{
if ((retval = target_halt(target)) != ERROR_OK)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- reg_t *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
+ struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
/* LDMIA r0-15, [r0] at debug speed
* register values will start to appear on 4th DCLK
{
target_t *target = get_current_target(cmd_ctx);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
{
target_t *target = get_current_target(cmd_ctx);
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+ struct reg *vector_catch;
uint32_t vector_catch_value;
/* it's uncommon, but some ARM7 chips can support this */
uint32_t vector_catch_value;
/* it's uncommon, but some ARM7 chips can support this */
uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
uint8_t armv4_5_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-reg_t armv4_5_gdb_dummy_fp_reg =
+struct reg armv4_5_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
{
"GDB dummy floating-point register", armv4_5_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
uint8_t armv4_5_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-reg_t armv4_5_gdb_dummy_fps_reg =
+struct reg armv4_5_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
{
"GDB dummy floating-point status register", armv4_5_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
-int armv4_5_get_core_reg(reg_t *reg)
+int armv4_5_get_core_reg(struct reg *reg)
{
int retval;
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
{
int retval;
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
-int armv4_5_set_core_reg(reg_t *reg, uint8_t *buf)
+int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
target_t *target = armv4_5->target;
{
struct armv4_5_core_reg *armv4_5 = reg->arch_info;
target_t *target = armv4_5->target;
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
+ struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
int i;
struct armv4_5_core_reg *arch_info = malloc(sizeof(struct armv4_5_core_reg) * num_regs);
int i;
-int armv4_5_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int armv4_5_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
{
struct armv4_5_common_s *armv4_5 = target_to_armv4_5(target);
int i;
return ERROR_FAIL;
*reg_list_size = 26;
return ERROR_FAIL;
*reg_list_size = 26;
- *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+ *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < 16; i++)
{
for (i = 0; i < 16; i++)
{
for (i = 0; i < num_reg_params; i++)
{
for (i = 0; i < num_reg_params; i++)
{
- reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
if (reg_params[i].direction != PARAM_OUT)
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
if (!reg)
{
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
int armv4_5_arch_state(struct target_s *target);
int armv4_5_get_gdb_reg_list(target_t *target,
int armv4_5_arch_state(struct target_s *target);
int armv4_5_get_gdb_reg_list(target_t *target,
- reg_t **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
-reg_t armv7a_gdb_dummy_fp_reg =
+struct reg armv7a_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7a_gdb_dummy_fp_value,
0, 1, 96, NULL, 0, NULL, 0
{
"GDB dummy floating-point register", armv7a_gdb_dummy_fp_value,
0, 1, 96, NULL, 0, NULL, 0
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
};
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
};
-static reg_t armv7m_gdb_dummy_fp_reg =
+static struct reg armv7m_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
{
"GDB dummy floating-point register", armv7m_gdb_dummy_fp_value, 0, 1, 96, NULL, 0, NULL, 0
};
static uint8_t armv7m_gdb_dummy_fps_value[] = {0, 0, 0, 0};
-static reg_t armv7m_gdb_dummy_fps_reg =
+static struct reg armv7m_gdb_dummy_fps_reg =
{
"GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
{
"GDB dummy floating-point status register", armv7m_gdb_dummy_fps_value, 0, 1, 32, NULL, 0, NULL, 0
};
#ifdef ARMV7_GDB_HACKS
uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
#ifdef ARMV7_GDB_HACKS
uint8_t armv7m_gdb_dummy_cpsr_value[] = {0, 0, 0, 0};
-reg_t armv7m_gdb_dummy_cpsr_reg =
+struct reg armv7m_gdb_dummy_cpsr_reg =
{
"GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
};
{
"GDB dummy cpsr register", armv7m_gdb_dummy_cpsr_value, 0, 1, 32, NULL, 0, NULL, 0
};
-static int armv7m_get_core_reg(reg_t *reg)
+static int armv7m_get_core_reg(struct reg *reg)
{
int retval;
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
{
int retval;
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
-static int armv7m_set_core_reg(reg_t *reg, uint8_t *buf)
+static int armv7m_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
{
struct armv7m_core_reg *armv7m_reg = reg->arch_info;
target_t *target = armv7m_reg->target;
* hardware, so this also fakes a set of long-obsolete FPA registers that
* are not used in EABI based software stacks.
*/
* hardware, so this also fakes a set of long-obsolete FPA registers that
* are not used in EABI based software stacks.
*/
-int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int armv7m_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
*reg_list_size = 26;
{
struct armv7m_common *armv7m = target_to_armv7m(target);
int i;
*reg_list_size = 26;
- *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+ *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
/*
* GDB register packet format for ARM:
/*
* GDB register packet format for ARM:
for (i = 0; i < num_reg_params; i++)
{
for (i = 0; i < num_reg_params; i++)
{
- reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
// uint32_t regvalue;
if (!reg)
// uint32_t regvalue;
if (!reg)
{
if (reg_params[i].direction != PARAM_OUT)
{
{
if (reg_params[i].direction != PARAM_OUT)
{
- reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
+ struct reg *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
int num_regs = ARMV7M_NUM_REGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
int num_regs = ARMV7M_NUM_REGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = calloc(num_regs, sizeof(reg_t));
+ struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
struct armv7m_core_reg *arch_info = calloc(num_regs, sizeof(struct armv7m_core_reg));
int i;
int armv7m_arch_state(struct target_s *target);
int armv7m_get_gdb_reg_list(target_t *target,
int armv7m_arch_state(struct target_s *target);
int armv7m_get_gdb_reg_list(target_t *target,
- reg_t **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size);
int armv7m_register_commands(struct command_context_s *cmd_ctx);
int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m);
int armv7m_register_commands(struct command_context_s *cmd_ctx);
int armv7m_init_arch_info(target_t *target, struct armv7m_common *armv7m);
#ifdef ARMV7_GDB_HACKS
extern uint8_t armv7m_gdb_dummy_cpsr_value[];
#ifdef ARMV7_GDB_HACKS
extern uint8_t armv7m_gdb_dummy_cpsr_value[];
-extern reg_t armv7m_gdb_dummy_cpsr_reg;
+extern struct reg armv7m_gdb_dummy_cpsr_reg;
#endif
static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
#endif
static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
uint32_t value; /* scratch/cache */
};
uint32_t value; /* scratch/cache */
};
-static int cortex_m3_dwt_get_reg(struct reg_s *reg)
+static int cortex_m3_dwt_get_reg(struct reg *reg)
{
struct dwt_reg_state *state = reg->arch_info;
return target_read_u32(state->target, state->addr, &state->value);
}
{
struct dwt_reg_state *state = reg->arch_info;
return target_read_u32(state->target, state->addr, &state->value);
}
-static int cortex_m3_dwt_set_reg(struct reg_s *reg, uint8_t *buf)
+static int cortex_m3_dwt_set_reg(struct reg *reg, uint8_t *buf)
{
struct dwt_reg_state *state = reg->arch_info;
{
struct dwt_reg_state *state = reg->arch_info;
static int dwt_reg_type = -1;
static void
static int dwt_reg_type = -1;
static void
-cortex_m3_dwt_addreg(struct target_s *t, struct reg_s *r, struct dwt_reg *d)
+cortex_m3_dwt_addreg(struct target_s *t, struct reg *r, struct dwt_reg *d)
{
struct dwt_reg_state *state;
{
struct dwt_reg_state *state;
static int embeddedice_reg_arch_type = -1;
static int embeddedice_reg_arch_type = -1;
-static int embeddedice_get_reg(reg_t *reg)
+static int embeddedice_get_reg(struct reg *reg)
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
{
int retval;
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = NULL;
+ struct reg *reg_list = NULL;
struct embeddedice_reg *arch_info = NULL;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
struct embeddedice_reg *arch_info = NULL;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int num_regs = ARRAY_SIZE(eice_regs);
num_regs--;
/* the actual registers are kept in two arrays */
num_regs--;
/* the actual registers are kept in two arrays */
- reg_list = calloc(num_regs, sizeof(reg_t));
+ reg_list = calloc(num_regs, sizeof(struct reg));
arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
/* fill in values for the reg cache */
arch_info = calloc(num_regs, sizeof(struct embeddedice_reg));
/* fill in values for the reg cache */
*/
if (arm7_9->has_monitor_mode)
{
*/
if (arm7_9->has_monitor_mode)
{
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
embeddedice_read_reg(dbg_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
embeddedice_read_reg(dbg_ctrl);
if ((retval = jtag_execute_queue()) != ERROR_OK)
* optionally checking the value read.
* Note that at this level, all registers are 32 bits wide.
*/
* optionally checking the value read.
* Note that at this level, all registers are 32 bits wide.
*/
-int embeddedice_read_reg_w_check(reg_t *reg,
+int embeddedice_read_reg_w_check(struct reg *reg,
uint8_t *check_value, uint8_t *check_mask)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
uint8_t *check_value, uint8_t *check_mask)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
* Queue a read for an EmbeddedICE register into the register cache,
* not checking the value read.
*/
* Queue a read for an EmbeddedICE register into the register cache,
* not checking the value read.
*/
-int embeddedice_read_reg(reg_t *reg)
+int embeddedice_read_reg(struct reg *reg)
{
return embeddedice_read_reg_w_check(reg, NULL, NULL);
}
{
return embeddedice_read_reg_w_check(reg, NULL, NULL);
}
* Queue a write for an EmbeddedICE register, updating the register cache.
* Uses embeddedice_write_reg().
*/
* Queue a write for an EmbeddedICE register, updating the register cache.
* Uses embeddedice_write_reg().
*/
-void embeddedice_set_reg(reg_t *reg, uint32_t value)
+void embeddedice_set_reg(struct reg *reg, uint32_t value)
{
embeddedice_write_reg(reg, value);
{
embeddedice_write_reg(reg, value);
* Write an EmbeddedICE register, updating the register cache.
* Uses embeddedice_set_reg(); not queued.
*/
* Write an EmbeddedICE register, updating the register cache.
* Uses embeddedice_set_reg(); not queued.
*/
-int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf)
/**
* Queue a write for an EmbeddedICE register, bypassing the register cache.
*/
/**
* Queue a write for an EmbeddedICE register, bypassing the register cache.
*/
-void embeddedice_write_reg(reg_t *reg, uint32_t value)
+void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
{
struct embeddedice_reg *ice_reg = reg->arch_info;
* Queue a write for an EmbeddedICE register, using cached value.
* Uses embeddedice_write_reg().
*/
* Queue a write for an EmbeddedICE register, using cached value.
* Uses embeddedice_write_reg().
*/
-void embeddedice_store_reg(reg_t *reg)
+void embeddedice_store_reg(struct reg *reg)
{
embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
{
embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
int embeddedice_setup(target_t *target);
int embeddedice_setup(target_t *target);
-int embeddedice_read_reg(reg_t *reg);
-int embeddedice_read_reg_w_check(reg_t *reg,
+int embeddedice_read_reg(struct reg *reg);
+int embeddedice_read_reg_w_check(struct reg *reg,
uint8_t* check_value, uint8_t* check_mask);
uint8_t* check_value, uint8_t* check_mask);
-void embeddedice_write_reg(reg_t *reg, uint32_t value);
-void embeddedice_store_reg(reg_t *reg);
+void embeddedice_write_reg(struct reg *reg, uint32_t value);
+void embeddedice_store_reg(struct reg *reg);
-void embeddedice_set_reg(reg_t *reg, uint32_t value);
-int embeddedice_set_reg_w_exec(reg_t *reg, uint8_t *buf);
+void embeddedice_set_reg(struct reg *reg, uint32_t value);
+int embeddedice_set_reg_w_exec(struct reg *reg, uint8_t *buf);
int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size);
static int etb_reg_arch_type = -1;
static int etb_reg_arch_type = -1;
-static int etb_get_reg(reg_t *reg);
+static int etb_get_reg(struct reg *reg);
static int etb_set_instr(struct etb *etb, uint32_t new_instr)
{
static int etb_set_instr(struct etb *etb, uint32_t new_instr)
{
-static int etb_read_reg_w_check(reg_t *, uint8_t *, uint8_t *);
-static int etb_set_reg_w_exec(reg_t *, uint8_t *);
+static int etb_read_reg_w_check(struct reg *, uint8_t *, uint8_t *);
+static int etb_set_reg_w_exec(struct reg *, uint8_t *);
-static int etb_read_reg(reg_t *reg)
+static int etb_read_reg(struct reg *reg)
{
return etb_read_reg_w_check(reg, NULL, NULL);
}
{
return etb_read_reg_w_check(reg, NULL, NULL);
}
-static int etb_get_reg(reg_t *reg)
+static int etb_get_reg(struct reg *reg)
struct reg_cache* etb_build_reg_cache(struct etb *etb)
{
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
struct reg_cache* etb_build_reg_cache(struct etb *etb)
{
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = NULL;
+ struct reg *reg_list = NULL;
struct etb_reg *arch_info = NULL;
int num_regs = 9;
int i;
struct etb_reg *arch_info = NULL;
int num_regs = 9;
int i;
etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
/* the actual registers are kept in two arrays */
etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
/* the actual registers are kept in two arrays */
- reg_list = calloc(num_regs, sizeof(reg_t));
+ reg_list = calloc(num_regs, sizeof(struct reg));
arch_info = calloc(num_regs, sizeof(struct etb_reg));
/* fill in values for the reg cache */
arch_info = calloc(num_regs, sizeof(struct etb_reg));
/* fill in values for the reg cache */
-static int etb_read_reg_w_check(reg_t *reg,
+static int etb_read_reg_w_check(struct reg *reg,
uint8_t* check_value, uint8_t* check_mask)
{
struct etb_reg *etb_reg = reg->arch_info;
uint8_t* check_value, uint8_t* check_mask)
{
struct etb_reg *etb_reg = reg->arch_info;
-static int etb_write_reg(reg_t *, uint32_t);
+static int etb_write_reg(struct reg *, uint32_t);
-static int etb_set_reg(reg_t *reg, uint32_t value)
+static int etb_set_reg(struct reg *reg, uint32_t value)
-static int etb_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+static int etb_set_reg_w_exec(struct reg *reg, uint8_t *buf)
-static int etb_write_reg(reg_t *reg, uint32_t value)
+static int etb_write_reg(struct reg *reg, uint32_t value)
{
struct etb_reg *etb_reg = reg->arch_info;
uint8_t reg_addr = etb_reg->addr & 0x7f;
{
struct etb_reg *etb_reg = reg->arch_info;
uint8_t reg_addr = etb_reg->addr & 0x7f;
static trace_status_t etb_status(struct etm_context *etm_ctx)
{
struct etb *etb = etm_ctx->capture_driver_priv;
static trace_status_t etb_status(struct etm_context *etm_ctx)
{
struct etb *etb = etm_ctx->capture_driver_priv;
- reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL];
- reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS];
+ struct reg *control = &etb->reg_cache->reg_list[ETB_CTRL];
+ struct reg *status = &etb->reg_cache->reg_list[ETB_STATUS];
trace_status_t retval = 0;
int etb_timeout = 100;
trace_status_t retval = 0;
int etb_timeout = 100;
static int etb_stop_capture(struct etm_context *etm_ctx)
{
struct etb *etb = etm_ctx->capture_driver_priv;
static int etb_stop_capture(struct etm_context *etm_ctx)
{
struct etb *etb = etm_ctx->capture_driver_priv;
- reg_t *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
+ struct reg *etb_ctrl_reg = &etb->reg_cache->reg_list[ETB_CTRL];
etb_write_reg(etb_ctrl_reg, 0x0);
jtag_execute_queue();
etb_write_reg(etb_ctrl_reg, 0x0);
jtag_execute_queue();
static int etm_reg_arch_type = -1;
static int etm_reg_arch_type = -1;
-static int etm_get_reg(reg_t *reg);
-static int etm_read_reg_w_check(reg_t *reg,
+static int etm_get_reg(struct reg *reg);
+static int etm_read_reg_w_check(struct reg *reg,
uint8_t* check_value, uint8_t* check_mask);
static int etm_register_user_commands(struct command_context_s *cmd_ctx);
uint8_t* check_value, uint8_t* check_mask);
static int etm_register_user_commands(struct command_context_s *cmd_ctx);
-static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
-static int etm_write_reg(reg_t *reg, uint32_t value);
+static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf);
+static int etm_write_reg(struct reg *reg, uint32_t value);
static command_t *etm_cmd;
static command_t *etm_cmd;
/* Look up register by ID ... most ETM instances only
* support a subset of the possible registers.
*/
/* Look up register by ID ... most ETM instances only
* support a subset of the possible registers.
*/
-static reg_t *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
+static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
{
struct reg_cache *cache = etm_ctx->reg_cache;
int i;
{
struct reg_cache *cache = etm_ctx->reg_cache;
int i;
struct reg_cache *cache, struct etm_reg *ereg,
const struct etm_reg_info *r, unsigned nreg)
{
struct reg_cache *cache, struct etm_reg *ereg,
const struct etm_reg_info *r, unsigned nreg)
{
- reg_t *reg = cache->reg_list;
+ struct reg *reg = cache->reg_list;
reg += cache->num_regs;
ereg += cache->num_regs;
reg += cache->num_regs;
ereg += cache->num_regs;
struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
{
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
struct arm_jtag *jtag_info, struct etm_context *etm_ctx)
{
struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = NULL;
+ struct reg *reg_list = NULL;
struct etm_reg *arch_info = NULL;
unsigned bcd_vers, config;
struct etm_reg *arch_info = NULL;
unsigned bcd_vers, config;
etm_set_reg_w_exec);
/* the actual registers are kept in two arrays */
etm_set_reg_w_exec);
/* the actual registers are kept in two arrays */
- reg_list = calloc(128, sizeof(reg_t));
+ reg_list = calloc(128, sizeof(struct reg));
arch_info = calloc(128, sizeof(struct etm_reg));
/* fill in values for the reg cache */
arch_info = calloc(128, sizeof(struct etm_reg));
/* fill in values for the reg cache */
-static int etm_read_reg(reg_t *reg)
+static int etm_read_reg(struct reg *reg)
{
return etm_read_reg_w_check(reg, NULL, NULL);
}
{
return etm_read_reg_w_check(reg, NULL, NULL);
}
-static int etm_store_reg(reg_t *reg)
+static int etm_store_reg(struct reg *reg)
{
return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
{
return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
uint32_t etm_ctrl_value;
struct arm *arm = target_to_arm(target);
struct etm_context *etm_ctx = arm->etm;
uint32_t etm_ctrl_value;
struct arm *arm = target_to_arm(target);
struct etm_context *etm_ctx = arm->etm;
+ struct reg *etm_ctrl_reg;
etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
if (!etm_ctrl_reg)
etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
if (!etm_ctrl_reg)
-static int etm_get_reg(reg_t *reg)
+static int etm_get_reg(struct reg *reg)
-static int etm_read_reg_w_check(reg_t *reg,
+static int etm_read_reg_w_check(struct reg *reg,
uint8_t* check_value, uint8_t* check_mask)
{
struct etm_reg *etm_reg = reg->arch_info;
uint8_t* check_value, uint8_t* check_mask)
{
struct etm_reg *etm_reg = reg->arch_info;
-static int etm_set_reg(reg_t *reg, uint32_t value)
+static int etm_set_reg(struct reg *reg, uint32_t value)
-static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+static int etm_set_reg_w_exec(struct reg *reg, uint8_t *buf)
-static int etm_write_reg(reg_t *reg, uint32_t value)
+static int etm_write_reg(struct reg *reg, uint32_t value)
{
struct etm_reg *etm_reg = reg->arch_info;
const struct etm_reg_info *r = etm_reg->reg_info;
{
struct etm_reg *etm_reg = reg->arch_info;
const struct etm_reg_info *r = etm_reg->reg_info;
/* only update ETM_CTRL register if tracemode changed */
if (etm->tracemode != tracemode)
{
/* only update ETM_CTRL register if tracemode changed */
if (etm->tracemode != tracemode)
{
+ struct reg *etm_ctrl_reg;
etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
if (!etm_ctrl_reg)
etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
if (!etm_ctrl_reg)
target_t *target;
struct arm *arm;
struct etm_context *etm;
target_t *target;
struct arm *arm;
struct etm_context *etm;
- reg_t *etm_sys_config_reg;
+ struct reg *etm_sys_config_reg;
int max_port_size;
uint32_t config;
int max_port_size;
uint32_t config;
/* ETM status */
if (etm->bcd_vers >= 0x11) {
/* ETM status */
if (etm->bcd_vers >= 0x11) {
reg = etm_reg_lookup(etm, ETM_STATUS);
if (!reg)
reg = etm_reg_lookup(etm, ETM_STATUS);
if (!reg)
target_t *target;
struct arm *arm;
struct etm_context *etm_ctx;
target_t *target;
struct arm *arm;
struct etm_context *etm_ctx;
+ struct reg *etm_ctrl_reg;
target = get_current_target(cmd_ctx);
arm = target_to_arm(target);
target = get_current_target(cmd_ctx);
arm = target_to_arm(target);
target_t *target;
struct arm *arm;
struct etm_context *etm_ctx;
target_t *target;
struct arm *arm;
struct etm_context *etm_ctx;
+ struct reg *etm_ctrl_reg;
target = get_current_target(cmd_ctx);
arm = target_to_arm(target);
target = get_current_target(cmd_ctx);
arm = target_to_arm(target);
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
{
struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
- reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
+ struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
embeddedice_store_reg(dbg_ctrl);
buf_set_u32(dbg_ctrl->value, 0, 8, 2);
embeddedice_store_reg(dbg_ctrl);
uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
-reg_t mips32_gdb_dummy_fp_reg =
+struct reg mips32_gdb_dummy_fp_reg =
{
"GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0
};
int mips32_core_reg_arch_type = -1;
{
"GDB dummy floating-point register", mips32_gdb_dummy_fp_value, 0, 1, 32, NULL, 0, NULL, 0
};
int mips32_core_reg_arch_type = -1;
-int mips32_get_core_reg(reg_t *reg)
+int mips32_get_core_reg(struct reg *reg)
{
int retval;
struct mips32_core_reg *mips32_reg = reg->arch_info;
{
int retval;
struct mips32_core_reg *mips32_reg = reg->arch_info;
-int mips32_set_core_reg(reg_t *reg, uint8_t *buf)
+int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct mips32_core_reg *mips32_reg = reg->arch_info;
target_t *target = mips32_reg->target;
{
struct mips32_core_reg *mips32_reg = reg->arch_info;
target_t *target = mips32_reg->target;
-int mips32_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size)
+int mips32_get_gdb_reg_list(target_t *target, struct reg **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target->arch_info;
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target->arch_info;
/* include floating point registers */
*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
/* include floating point registers */
*reg_list_size = MIPS32NUMCOREREGS + MIPS32NUMFPREGS;
- *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size));
+ *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
for (i = 0; i < MIPS32NUMCOREREGS; i++)
{
for (i = 0; i < MIPS32NUMCOREREGS; i++)
{
int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
- reg_t *reg_list = malloc(sizeof(reg_t) * num_regs);
+ struct reg *reg_list = malloc(sizeof(struct reg) * num_regs);
struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
int i;
struct mips32_core_reg *arch_info = malloc(sizeof(struct mips32_core_reg) * num_regs);
int i;
int mips32_invalidate_core_regs(target_t *target);
int mips32_get_gdb_reg_list(target_t *target,
int mips32_invalidate_core_regs(target_t *target);
int mips32_get_gdb_reg_list(target_t *target,
- reg_t **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size);
struct reg_arch_type *reg_arch_types = NULL;
struct reg_arch_type *reg_arch_types = NULL;
-reg_t* register_get_by_name(struct reg_cache *first,
+struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all)
{
int i;
const char *name, bool search_all)
{
int i;
-int register_reg_arch_type(int (*get)(reg_t *reg), int (*set)(reg_t *reg, uint8_t *buf))
+int register_reg_arch_type(int (*get)(struct reg *reg), int (*set)(struct reg *reg, uint8_t *buf))
{
struct reg_arch_type** arch_type_p = ®_arch_types;
int id = 0;
{
struct reg_arch_type** arch_type_p = ®_arch_types;
int id = 0;
-static int register_get_dummy_core_reg(reg_t *reg)
+static int register_get_dummy_core_reg(struct reg *reg)
-static int register_set_dummy_core_reg(reg_t *reg, uint8_t *buf)
+static int register_set_dummy_core_reg(struct reg *reg, uint8_t *buf)
{
reg->dirty = 1;
reg->valid = 1;
{
reg->dirty = 1;
reg->valid = 1;
-void register_init_dummy(reg_t *reg)
+void register_init_dummy(struct reg *reg)
{
static int dummy_arch_type = -1;
if (dummy_arch_type == -1)
{
static int dummy_arch_type = -1;
if (dummy_arch_type == -1)
{
char *name;
void *value;
{
char *name;
void *value;
int num_bitfields;
void *arch_info;
int arch_type;
int num_bitfields;
void *arch_info;
int arch_type;
struct reg_cache
{
char *name;
struct reg_cache *next;
struct reg_cache
{
char *name;
struct reg_cache *next;
int num_regs;
};
struct reg_arch_type
{
int id;
int num_regs;
};
struct reg_arch_type
{
int id;
- int (*get)(reg_t *reg);
- int (*set)(reg_t *reg, uint8_t *buf);
+ int (*get)(struct reg *reg);
+ int (*set)(struct reg *reg, uint8_t *buf);
struct reg_arch_type *next;
};
struct reg_arch_type *next;
};
-reg_t* register_get_by_name(struct reg_cache *first,
+struct reg* register_get_by_name(struct reg_cache *first,
const char *name, bool search_all);
struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
const char *name, bool search_all);
struct reg_cache** register_get_last_cache_p(struct reg_cache **first);
-int register_reg_arch_type(int (*get)(reg_t *reg),
- int (*set)(reg_t *reg, uint8_t *buf));
+int register_reg_arch_type(int (*get)(struct reg *reg),
+ int (*set)(struct reg *reg, uint8_t *buf));
struct reg_arch_type* register_get_arch_type(int id);
struct reg_arch_type* register_get_arch_type(int id);
-void register_init_dummy(reg_t *reg);
+void register_init_dummy(struct reg *reg);
}
int target_get_gdb_reg_list(struct target_s *target,
}
int target_get_gdb_reg_list(struct target_s *target,
- struct reg_s **reg_list[], int *reg_list_size)
+ struct reg **reg_list[], int *reg_list_size)
{
return target->type->get_gdb_reg_list(target, reg_list, reg_list_size);
}
{
return target->type->get_gdb_reg_list(target, reg_list, reg_list_size);
}
COMMAND_HANDLER(handle_reg_command)
{
target_t *target;
COMMAND_HANDLER(handle_reg_command)
{
target_t *target;
+ struct reg *reg = NULL;
int count = 0;
char *value;
int count = 0;
char *value;
int numSamples = 0;
/* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */
int numSamples = 0;
/* hopefully it is safe to cache! We want to stop/restart as quickly as possible. */
- reg_t *reg = register_get_by_name(target->reg_cache, "pc", 1);
+ struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
#include "algorithm.h"
#include "command.h"
#include "algorithm.h"
#include "command.h"
struct trace;
struct command_context_s;
struct trace;
struct command_context_s;
* This routine is a wrapper for target->type->get_gdb_reg_list.
*/
int target_get_gdb_reg_list(struct target_s *target,
* This routine is a wrapper for target->type->get_gdb_reg_list.
*/
int target_get_gdb_reg_list(struct target_s *target,
- struct reg_s **reg_list[], int *reg_list_size);
+ struct reg **reg_list[], int *reg_list_size);
* list, however it is after GDB is connected that monitor commands can
* be run to properly initialize the target
*/
* list, however it is after GDB is connected that monitor commands can
* be run to properly initialize the target
*/
- int (*get_gdb_reg_list)(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
+ int (*get_gdb_reg_list)(struct target_s *target, struct reg **reg_list[], int *reg_list_size);
/* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
/* target memory access
* size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
uint32_t address, int handle_breakpoints, int debug_execution);
static int xscale_debug_entry(target_t *);
static int xscale_restore_context(target_t *);
uint32_t address, int handle_breakpoints, int debug_execution);
static int xscale_debug_entry(target_t *);
static int xscale_restore_context(target_t *);
-static int xscale_get_reg(reg_t *reg);
-static int xscale_set_reg(reg_t *reg, uint8_t *buf);
+static int xscale_get_reg(struct reg *reg);
+static int xscale_set_reg(struct reg *reg, uint8_t *buf);
static int xscale_set_breakpoint(struct target_s *, struct breakpoint *);
static int xscale_set_watchpoint(struct target_s *, struct watchpoint *);
static int xscale_unset_breakpoint(struct target_s *, struct breakpoint *);
static int xscale_set_breakpoint(struct target_s *, struct breakpoint *);
static int xscale_set_watchpoint(struct target_s *, struct watchpoint *);
static int xscale_unset_breakpoint(struct target_s *, struct breakpoint *);
static int xscale_reg_arch_type = -1;
/* convenience wrapper to access XScale specific registers */
static int xscale_reg_arch_type = -1;
/* convenience wrapper to access XScale specific registers */
-static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
+static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
{
struct xscale_common *xscale = target_to_xscale(target);
- reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+ struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
if (xscale->ibcr0_used)
int retval;
if (xscale->ibcr0_used)
static int xscale_disable_single_step(struct target_s *target)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_disable_single_step(struct target_s *target)
{
struct xscale_common *xscale = target_to_xscale(target);
- reg_t *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
+ struct reg *ibcr0 = &xscale->reg_cache->reg_list[XSCALE_IBCR0];
int retval;
if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
int retval;
if ((retval = xscale_set_reg_u32(ibcr0, 0x0)) != ERROR_OK)
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t enable = 0;
{
struct xscale_common *xscale = target_to_xscale(target);
uint8_t enable = 0;
- reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+ struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED)
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED)
struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
struct watchpoint *watchpoint)
{
struct xscale_common *xscale = target_to_xscale(target);
- reg_t *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
+ struct reg *dbcon = &xscale->reg_cache->reg_list[XSCALE_DBCON];
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED)
uint32_t dbcon_value = buf_get_u32(dbcon->value, 0, 32);
if (target->state != TARGET_HALTED)
-static int xscale_get_reg(reg_t *reg)
+static int xscale_get_reg(struct reg *reg)
{
struct xscale_reg *arch_info = reg->arch_info;
target_t *target = arch_info->target;
{
struct xscale_reg *arch_info = reg->arch_info;
target_t *target = arch_info->target;
-static int xscale_set_reg(reg_t *reg, uint8_t* buf)
+static int xscale_set_reg(struct reg *reg, uint8_t* buf)
{
struct xscale_reg *arch_info = reg->arch_info;
target_t *target = arch_info->target;
{
struct xscale_reg *arch_info = reg->arch_info;
target_t *target = arch_info->target;
static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
{
struct xscale_common *xscale = target_to_xscale(target);
static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
{
struct xscale_common *xscale = target_to_xscale(target);
- reg_t *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
+ struct reg *dcsr = &xscale->reg_cache->reg_list[XSCALE_DCSR];
struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
/* send CP write request (command 0x41) */
struct xscale_reg *dcsr_arch_info = dcsr->arch_info;
/* send CP write request (command 0x41) */
/* fill in values for the xscale reg cache */
(*cache_p)->name = "XScale registers";
(*cache_p)->next = NULL;
/* fill in values for the xscale reg cache */
(*cache_p)->name = "XScale registers";
(*cache_p)->next = NULL;
- (*cache_p)->reg_list = malloc(num_regs * sizeof(reg_t));
+ (*cache_p)->reg_list = malloc(num_regs * sizeof(struct reg));
(*cache_p)->num_regs = num_regs;
for (i = 0; i < num_regs; i++)
(*cache_p)->num_regs = num_regs;
for (i = 0; i < num_regs; i++)
return ERROR_OK;
}
uint32_t reg_no = 0;
return ERROR_OK;
}
uint32_t reg_no = 0;
+ struct reg *reg = NULL;
if (argc > 0)
{
COMMAND_PARSE_NUMBER(u32, args[0], reg_no);
if (argc > 0)
{
COMMAND_PARSE_NUMBER(u32, args[0], reg_no);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)
Code Review / openocd.git / commitdiff