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target/arm_dpm: uniform names of exported functions 56/4756/2
authorAntonio Borneo <borneo.antonio@gmail.com>
Sat, 3 Nov 2018 13:52:30 +0000 (14:52 +0100)
committerMatthias Welwarsky <matthias@welwarsky.de>
Tue, 6 Nov 2018 12:18:40 +0000 (12:18 +0000)
The name of the function dpm_modeswitch() does not follow the
common style of the other function names in the same file.

Rename it as arm_dpm_modeswitch().

Change-Id: Idebf3c7bbddcd9b3c7b44f8d0dea1e5f7549b0eb
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4756
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
src/target/arm_dpm.c patch | blob | history
src/target/arm_dpm.h patch | blob | history
src/target/cortex_a.c patch | blob | history

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index f9b30c18722c8732d7d6db5934ac59ccec0f8041..9bab96f7e17bbc47f41eb6925c0207dd5e91d75e 100644 (file)
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -108,7 +108,7 @@ static int dpm_mcr(struct target *target, int cpnum,
 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  * Routines *must* restore the original mode before returning!!
  */
 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  * Routines *must* restore the original mode before returning!!
  */
-int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
+int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 {
        int retval;
        uint32_t cpsr;
 {
        int retval;
        uint32_t cpsr;
@@ -543,7 +543,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 
                                /* REVISIT error checks */
                                if (tmode != ARM_MODE_ANY) {
 
                                /* REVISIT error checks */
                                if (tmode != ARM_MODE_ANY) {
-                                       retval = dpm_modeswitch(dpm, tmode);
+                                       retval = arm_dpm_modeswitch(dpm, tmode);
                                        if (retval != ERROR_OK)
                                                goto done;
                                }
                                        if (retval != ERROR_OK)
                                                goto done;
                                }
@@ -564,7 +564,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
         * or it's dirty.  Must write PC to ensure the return address is
         * defined, and must not write it before CPSR.
         */
         * or it's dirty.  Must write PC to ensure the return address is
         * defined, and must not write it before CPSR.
         */
-       retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
+       retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
        if (retval != ERROR_OK)
                goto done;
        arm->cpsr->dirty = false;
        if (retval != ERROR_OK)
                goto done;
        arm->cpsr->dirty = false;
@@ -671,7 +671,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
                return retval;
 
        if (mode != ARM_MODE_ANY) {
                return retval;
 
        if (mode != ARM_MODE_ANY) {
-               retval = dpm_modeswitch(dpm, mode);
+               retval = arm_dpm_modeswitch(dpm, mode);
                if (retval != ERROR_OK)
                        goto fail;
        }
                if (retval != ERROR_OK)
                        goto fail;
        }
@@ -682,7 +682,7 @@ static int arm_dpm_read_core_reg(struct target *target, struct reg *r,
        /* always clean up, regardless of error */
 
        if (mode != ARM_MODE_ANY)
        /* always clean up, regardless of error */
 
        if (mode != ARM_MODE_ANY)
-               /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
+               /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
 
 fail:
        /* (void) */ dpm->finish(dpm);
 
 fail:
        /* (void) */ dpm->finish(dpm);
@@ -715,7 +715,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
                return retval;
 
        if (mode != ARM_MODE_ANY) {
                return retval;
 
        if (mode != ARM_MODE_ANY) {
-               retval = dpm_modeswitch(dpm, mode);
+               retval = arm_dpm_modeswitch(dpm, mode);
                if (retval != ERROR_OK)
                        goto fail;
        }
                if (retval != ERROR_OK)
                        goto fail;
        }
@@ -724,7 +724,7 @@ static int arm_dpm_write_core_reg(struct target *target, struct reg *r,
        /* always clean up, regardless of error */
 
        if (mode != ARM_MODE_ANY)
        /* always clean up, regardless of error */
 
        if (mode != ARM_MODE_ANY)
-               /* (void) */ dpm_modeswitch(dpm, ARM_MODE_ANY);
+               /* (void) */ arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
 
 fail:
        /* (void) */ dpm->finish(dpm);
 
 fail:
        /* (void) */ dpm->finish(dpm);
@@ -773,9 +773,9 @@ static int arm_dpm_full_context(struct target *target)
                                 * in FIQ mode we need to patch mode.
                                 */
                                if (mode != ARM_MODE_ANY)
                                 * in FIQ mode we need to patch mode.
                                 */
                                if (mode != ARM_MODE_ANY)
-                                       retval = dpm_modeswitch(dpm, mode);
+                                       retval = arm_dpm_modeswitch(dpm, mode);
                                else
                                else
-                                       retval = dpm_modeswitch(dpm, ARM_MODE_USR);
+                                       retval = arm_dpm_modeswitch(dpm, ARM_MODE_USR);
 
                                if (retval != ERROR_OK)
                                        goto done;
 
                                if (retval != ERROR_OK)
                                        goto done;
@@ -793,7 +793,7 @@ static int arm_dpm_full_context(struct target *target)
 
        } while (did_read);
 
 
        } while (did_read);
 
-       retval = dpm_modeswitch(dpm, ARM_MODE_ANY);
+       retval = arm_dpm_modeswitch(dpm, ARM_MODE_ANY);
        /* (void) */ dpm->finish(dpm);
 done:
        return retval;
        /* (void) */ dpm->finish(dpm);
 done:
        return retval;
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index f8d124813658a0ffe4a4c9293f99dc67963663e9..ea6b25a6095755f29e7762c8caccf827021f4947 100644 (file)
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -153,7 +153,7 @@ int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
 int arm_dpm_read_current_registers(struct arm_dpm *);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
 int arm_dpm_read_current_registers(struct arm_dpm *);
-int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
 
 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 2768e18cf91055f8d19b2572d7b07dd71b6f6973..77859d3e861b70b574adb3598668bd0511e83b5f 100644 (file)
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -113,7 +113,7 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
        int mmu_enabled = 0;
 
        if (phys_access == 0) {
        int mmu_enabled = 0;
 
        if (phys_access == 0) {
-               dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+               arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
                cortex_a_mmu(target, &mmu_enabled);
                if (mmu_enabled)
                        cortex_a_mmu_modify(target, 1);
                cortex_a_mmu(target, &mmu_enabled);
                if (mmu_enabled)
                        cortex_a_mmu_modify(target, 1);
@@ -148,7 +148,7 @@ static int cortex_a_post_memaccess(struct target *target, int phys_access)
                                        0, 0, 3, 0,
                                        cortex_a->cp15_dacr_reg);
                }
                                        0, 0, 3, 0,
                                        cortex_a->cp15_dacr_reg);
                }
-               dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+               arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        } else {
                int mmu_enabled = 0;
                cortex_a_mmu(target, &mmu_enabled);
        } else {
                int mmu_enabled = 0;
                cortex_a_mmu(target, &mmu_enabled);
@@ -1011,7 +1011,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
        arm->pc->valid = 1;
 
        /* restore dpm_mode at system halt */
        arm->pc->valid = 1;
 
        /* restore dpm_mode at system halt */
-       dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+       arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        /* called it now before restoring context because it uses cpu
         * register r0 for restoring cp15 control register */
        retval = cortex_a_restore_cp15_control_reg(target);
        /* called it now before restoring context because it uses cpu
         * register r0 for restoring cp15 control register */
        retval = cortex_a_restore_cp15_control_reg(target);
@@ -1277,7 +1277,7 @@ static int cortex_a_post_debug_entry(struct target *target)
        cortex_a->curr_mode = armv7a->arm.core_mode;
 
        /* switch to SVC mode to read DACR */
        cortex_a->curr_mode = armv7a->arm.core_mode;
 
        /* switch to SVC mode to read DACR */
-       dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
+       arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
        armv7a->arm.mrc(target, 15,
                        0, 0, 3, 0,
                        &cortex_a->cp15_dacr_reg);
        armv7a->arm.mrc(target, 15,
                        0, 0, 3, 0,
                        &cortex_a->cp15_dacr_reg);
@@ -1285,7 +1285,7 @@ static int cortex_a_post_debug_entry(struct target *target)
        LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
                        cortex_a->cp15_dacr_reg);
 
        LOG_DEBUG("cp15_dacr_reg: %8.8" PRIx32,
                        cortex_a->cp15_dacr_reg);
 
-       dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
+       arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
        return ERROR_OK;
 }
 
        return ERROR_OK;
 }
 
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