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minor corrections for target scripts.
authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Fri, 7 Mar 2008 11:42:03 +0000 (11:42 +0000)
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Fri, 7 Mar 2008 11:42:03 +0000 (11:42 +0000)
git-svn-id: svn://svn.berlios.de/openocd/trunk@468 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/Makefile.am patch | blob | history
src/target/event/pxa255_reset.script [new file with mode: 0644] patch | blob
src/target/target/pxa255.cfg patch | blob | history
src/target/target/pxa255_sst.cfg patch | blob | history

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 64e12753c46374e0c01bd88d8a7b7527c43aed0c..7dfcc89e43901d1ade81bc874301be629ab6d0da 100644 (file)
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -23,7 +23,8 @@ nobase_dist_pkglib_DATA = xscale/debug_handler.bin event/at91eb40a_reset.script
        event/at91r40008_reset.script event/sam7s256_reset.script event/sam7x256_reset.script \
        target/at91r40008.cfg target/lpc2148.cfg target/lpc2294.cfg target/sam7s256.cfg \
        target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
-       target/pxa255.cfg  target/zy1000.cfg event/zy1000_reset.script event/at91sam9260_reset.script target/at91sam9260.cfg 
+       target/pxa255.cfg  target/zy1000.cfg event/zy1000_reset.script event/at91sam9260_reset.script target/at91sam9260.cfg \
+       target/wi-9c.cfg event/wi-9c_reset.script event/pxa255_reset.script
        
 
 
diff --git a/src/target/event/pxa255_reset.script b/src/target/event/pxa255_reset.script
new file mode 100644 (file)
index 0000000..a4a9716
--- /dev/null
+++ b/src/target/event/pxa255_reset.script
@@ -0,0 +1,74 @@
+#configuration file for PXA250 Evaluation Board\r
+# -----------------------------------------------------\r
+#\r
+xscale cp15   15      0x00002001  #Enable CP0 and CP13 access\r
+#\r
+# setup GPIO\r
+#\r
+mww    0x40E00018  0x00008000  #CPSR0\r
+sleep   20\r
+mww    0x40E0001C  0x00000002  #GPSR1\r
+sleep   20\r
+mww    0x40E00020  0x00000008  #GPSR2\r
+sleep   20\r
+mww    0x40E0000C  0x00008000  #GPDR0\r
+sleep   20\r
+mww    0x40E00054  0x80000000  #GAFR0_L\r
+sleep   20\r
+mww    0x40E00058  0x00188010  #GAFR0_H\r
+sleep   20\r
+mww    0x40E0005C  0x60908018  #GAFR1_L\r
+sleep   20\r
+mww    0x40E0000C  0x0280E000  #GPDR0\r
+sleep   20\r
+mww    0x40E00010  0x821C88B2  #GPDR1\r
+sleep   20\r
+mww    0x40E00014  0x000F03DB  #GPDR2\r
+sleep   20\r
+mww    0x40E00000  0x000F03DB  #GPLR0\r
+sleep   20\r
+\r
+\r
+mww    0x40F00004  0x00000020  #PSSR\r
+sleep   20\r
+\r
+#\r
+# setup memory controller\r
+#\r
+mww    0x48000008  0x01111998  #MSC0\r
+sleep   20\r
+mww    0x48000010  0x00047ff0  #MSC2\r
+sleep   20\r
+mww    0x48000014  0x00000000  #MECR\r
+sleep   20\r
+mww    0x48000028  0x00010504  #MCMEM0\r
+sleep   20\r
+mww    0x4800002C  0x00010504  #MCMEM1\r
+sleep   20\r
+mww    0x48000030  0x00010504  #MCATT0\r
+sleep   20\r
+mww    0x48000034  0x00010504  #MCATT1\r
+sleep   20\r
+mww    0x48000038  0x00004715  #MCIO0\r
+sleep   20\r
+mww    0x4800003C  0x00004715  #MCIO1\r
+sleep   20\r
+#\r
+mww    0x48000004  0x03CA4018  #MDREF\r
+sleep   20\r
+mww    0x48000004  0x004B4018  #MDREF\r
+sleep   20\r
+mww    0x48000004  0x000B4018  #MDREF\r
+sleep   20\r
+mww    0x48000004  0x000BC018  #MDREF\r
+sleep   20\r
+mww    0x48000000  0x00001AC8  #MDCNFG\r
+sleep   20\r
+\r
+sleep   20\r
+\r
+mww    0x48000000  0x00001AC9  #MDCNFG\r
+sleep   20\r
+mww    0x48000040  0x00000000  #MDMRS\r
+sleep   20\r
+\r
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg
index 2a4521356cf2a0d3644ea0cc23d765dbd341db2d..0c4e6b9c4e07ac033822ebfc0a675ca4e12448c5 100644 (file)
--- a/src/target/target/pxa255.cfg
+++ b/src/target/target/pxa255.cfg
@@ -5,82 +5,7 @@ target xscale little reset_init 0 pxa255
 reset_config trst_and_srst
 run_and_halt_time 0 30
 
-target_script 0 reset /ram/pxa255.init
+target_script 0 reset event/pxa255_reset.script
 
 #xscale debug_handler 0  0xFFFF0800      # debug handler base address
 
-trunc /ram/pxa255.init
-append /ram/pxa255.init #configuration file for PXA250 Evaluation Board
-append /ram/pxa255.init # -----------------------------------------------------
-append /ram/pxa255.init #
-append /ram/pxa255.init xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
-append /ram/pxa255.init #
-append /ram/pxa255.init # setup GPIO
-append /ram/pxa255.init #
-append /ram/pxa255.init mww    0x40E00018  0x00008000  #CPSR0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E0001C  0x00000002  #GPSR1
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00020  0x00000008  #GPSR2
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E0000C  0x00008000  #GPDR0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00054  0x80000000  #GAFR0_L
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00058  0x00188010  #GAFR0_H
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E0005C  0x60908018  #GAFR1_L
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E0000C  0x0280E000  #GPDR0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00010  0x821C88B2  #GPDR1
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00014  0x000F03DB  #GPDR2
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x40E00000  0x000F03DB  #GPLR0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init 
-append /ram/pxa255.init 
-append /ram/pxa255.init mww    0x40F00004  0x00000020  #PSSR
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init 
-append /ram/pxa255.init #
-append /ram/pxa255.init # setup memory controller
-append /ram/pxa255.init #
-append /ram/pxa255.init mww    0x48000008  0x01111998  #MSC0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000010  0x00047ff0  #MSC2
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000014  0x00000000  #MECR
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000028  0x00010504  #MCMEM0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x4800002C  0x00010504  #MCMEM1
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000030  0x00010504  #MCATT0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000034  0x00010504  #MCATT1
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000038  0x00004715  #MCIO0
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x4800003C  0x00004715  #MCIO1
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init #
-append /ram/pxa255.init mww    0x48000004  0x03CA4018  #MDREF
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000004  0x004B4018  #MDREF
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000004  0x000B4018  #MDREF
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000004  0x000BC018  #MDREF
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000000  0x00001AC8  #MDCNFG
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init 
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init 
-append /ram/pxa255.init mww    0x48000000  0x00001AC9  #MDCNFG
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init mww    0x48000040  0x00000000  #MDMRS
-append /ram/pxa255.init sleep   20
-append /ram/pxa255.init 
diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg
index a5fea1730612a1a4e7998c72a843a06a3fd9df8b..01d63e41bc1acefd089fec13d1be76995f89e95a 100644 (file)
--- a/src/target/target/pxa255_sst.cfg
+++ b/src/target/target/pxa255_sst.cfg
@@ -7,7 +7,7 @@
 # RAM at 0x40000000
 # Flash at 0x00000000
 #
-script /target/pxa255.cfg
+script target/pxa255.cfg
 # flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
 flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
 working_area 0 0x4000000 0x4000 nobackup 0
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