flash/stm32l4x: add support of STM32WLEx devices

STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.

there is 3 variants with different Flash/RAM sizes:
  STM32WLE5JC : 256K/64K
  STM32WLE5JB : 128K/48K
  STM32WLE5J8 :  64K/20K

the work-area size is set to 20 kb to fit in STM32WLE5J8

Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 97c5a728daac338b63758ddabe845b0ad3ecc8c8..25554f87a4014fa3499238c4cb2274283dc1e53c 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6892,7 +6892,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
 @deffn {Flash Driver} stm32l4x
 @end deffn
 
 @deffn {Flash Driver} stm32l4x

-All members of the STM32L4, STM32L4+, STM32WB and STM32G4
+All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4

 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M4 cores.
 Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.
 microcontroller families from STMicroelectronics include internal flash
 and use ARM Cortex-M4 cores.
 Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index b6f0d714d8ccc336a30375c7409eb369dcbccb2b..42f3394ec8e2100319d3deadea9190fc3e41af83 100644 (file)
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -75,6 +75,12 @@
  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
  */
 
  * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
  */
 

+/* STM32WLxxx series for reference.
+ *
+ * RM0461 (STM32WLEx)
+ * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
+ */
+

 /*
  * STM32G0xxx series for reference.
  *
 /*
  * STM32G0xxx series for reference.
  *


@@ -132,7 +138,7 @@ struct stm32l4_flash_bank {
 };
 
 /* human readable list of families this drivers supports */
 };
 
 /* human readable list of families this drivers supports */

-static const char *device_families = "STM32L4/L4+/WB/G4/G0";
+static const char *device_families = "STM32L4/L4+/WB/WL/G4/G0";

 
 static const struct stm32l4_rev stm32_415_revs[] = {
        { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
 
 static const struct stm32l4_rev stm32_415_revs[] = {
        { 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }


@@ -182,6 +188,10 @@ static const struct stm32l4_rev stm32_495_revs[] = {
        { 0x2001, "2.1" },
 };
 
        { 0x2001, "2.1" },
 };
 

+static const struct stm32l4_rev stm32_497_revs[] = {
+       { 0x1000, "1.0" },
+};
+

 static const struct stm32l4_part_info stm32l4_parts[] = {
        {
          .id                    = 0x415,
 static const struct stm32l4_part_info stm32l4_parts[] = {
        {
          .id                    = 0x415,


@@ -303,6 +313,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
          .flash_regs_base       = 0x58004000,
          .fsize_addr            = 0x1FFF75E0,
        },
          .flash_regs_base       = 0x58004000,
          .fsize_addr            = 0x1FFF75E0,
        },

+       {
+         .id                    = 0x497,
+         .revs                  = stm32_497_revs,
+         .num_revs              = ARRAY_SIZE(stm32_497_revs),
+         .device_str            = "STM32WLEx",
+         .max_flash_size_kb     = 256,
+         .has_dual_bank         = false,
+         .flash_regs_base       = 0x58004000,
+         .fsize_addr            = 0x1FFF75E0,
+       },

 };
 
 /* flash bank stm32l4x <base> <size> 0 0 <target#> */
 };
 
 /* flash bank stm32l4x <base> <size> 0 0 <target#> */


@@ -918,6 +938,7 @@ static int stm32l4_probe(struct flash_bank *bank)
        case 0x464: /* STM32L41/L42xx */
        case 0x466: /* STM32G03/G04xx */
        case 0x468: /* STM32G43/G44xx */
        case 0x464: /* STM32L41/L42xx */
        case 0x466: /* STM32G03/G04xx */
        case 0x468: /* STM32G43/G44xx */

+       case 0x497: /* STM32WLEx */

                /* single bank flash */
                page_size_kb = 2;
                num_pages = flash_size_kb / page_size_kb;
                /* single bank flash */
                page_size_kb = 2;
                num_pages = flash_size_kb / page_size_kb;

diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 9d8e91014374ec80610630b84650a7d9969aafb1..aafb939cd6c1b2f2c07f245926a004cec7db240b 100644 (file)
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -113,10 +113,11 @@ proc stm32f7x args { eval stm32f2x $args }
 proc stm32l0x args { eval stm32lx $args }
 proc stm32l1x args { eval stm32lx $args }
 
 proc stm32l0x args { eval stm32lx $args }
 proc stm32l1x args { eval stm32lx $args }
 

-# stm32[g0|g4|wb] uses the same flash driver as the stm32l4x
+# stm32[g0|g4|wb|wl] uses the same flash driver as the stm32l4x

 proc stm32g0x args { eval stm32l4x $args }
 proc stm32g4x args { eval stm32l4x $args }
 proc stm32wbx args { eval stm32l4x $args }
 proc stm32g0x args { eval stm32l4x $args }
 proc stm32g4x args { eval stm32l4x $args }
 proc stm32wbx args { eval stm32l4x $args }

+proc stm32wlx args { eval stm32l4x $args }

 
 # ease migration to updated flash driver
 proc stm32x args {
 
 # ease migration to updated flash driver
 proc stm32x args {

diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
new file mode 100644 (file)
index 0000000..98c9a7e
--- /dev/null
+++ b/tcl/target/stm32wlx.cfg
@@ -0,0 +1,100 @@
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+       set _CHIPNAME $CHIPNAME
+} else {
+       set _CHIPNAME stm32wlx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 20kB
+if { [info exists WORKAREASIZE] } {
+       set _WORKAREASIZE $WORKAREASIZE
+} else {
+       set _WORKAREASIZE 0x5000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+       set _CPUTAPID $CPUTAPID
+} else {
+       if { [using_jtag] } {
+               set _CPUTAPID 0x6ba00477
+       } else {
+               # SWD IDCODE (single drop, arm)
+               set _CPUTAPID 0x6ba02477
+       }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+       swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+       jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+       # if srst is not fitted use SYSRESETREQ to
+       # perform a soft reset
+       cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+       # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+       # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+       # 2 WS compliant with VOS=Range1 and 24 MHz.
+       mmw 0x58004000 0x00000102 0  ;# FLASH_ACR |= PRFTEN | 2(Latency)
+       mmw 0x58000000 0x00000091 0  ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+       # Boost JTAG frequency
+       adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+       # Reset clock is MSI (4 MHz)
+       adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+       # Enable debug during low power modes (uses more power)
+       # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+       mmw 0xE0042004 0x00000007 0
+
+       # Stop watchdog counters during halt
+       # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+       mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+       # nothing to do
+}