- arm11_read_memory_word(arm11, R(PC), &next_instruction);
+ if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
+ return retval;
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
+ return retval;
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- arm11_leave_debug_state(arm11);
+ if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
arm11_sc7_clear_vbw(arm11);
/* save state */
arm11_sc7_clear_vbw(arm11);
/* save state */
- arm11_on_enter_debug_state(arm11);
+ if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
+ return retval;
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
-void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
+int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
-void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
+int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
-void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
-void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
+int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
function returns. */
} arm11_sc7_action_t;
function returns. */
} arm11_sc7_action_t;
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
* \param count Number of opcodes to execute
*
*/
* \param count Number of opcodes to execute
*
*/
-void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
}
/** Execute one instruction via ITR
}
/** Execute one instruction via ITR
* \param count Number of data words and instruction repetitions
*
*/
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
}
/** JTAG path for arm11_run_instr_data_to_core_noack
}
/** JTAG path for arm11_run_instr_data_to_core_noack
* \param count Number of data words and instruction repetitions
*
*/
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
* \param data Data word to be passed to the core via DTR
*
*/
* \param data Data word to be passed to the core via DTR
*
*/
-void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
- arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
+ return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
* \param count Number of data words and instruction repetitions
*
*/
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
}
/** Execute one instruction via ITR
}
/** Execute one instruction via ITR
* \param count Number of instructions in the list.
*
*/
* \param count Number of instructions in the list.
*
*/
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
}}
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
}}
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
* \param result Pointer where to store result
*
*/
* \param result Pointer where to store result
*
*/
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
+ return retval;
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
+ if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
+ return retval;
arm11_run_instr_data_finish(arm11);
arm11_run_instr_data_finish(arm11);
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