Remove misleading typedef and just use struct arm.
14 files changed:
{
target_t *target = nand->target;
struct armv4_5_algorithm algo;
{
target_t *target = nand->target;
struct armv4_5_algorithm algo;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit = 0;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit = 0;
FLASH_BANK_COMMAND_HANDLER(ocl_flash_bank_command)
{
int retval;
FLASH_BANK_COMMAND_HANDLER(ocl_flash_bank_command)
{
int retval;
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
struct ocl_priv *ocl;
struct arm7_9_common *arm7_9;
struct ocl_priv *ocl;
FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
{
struct str9xpec_flash_controller *str9xpec_info;
FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
{
struct str9xpec_flash_controller *str9xpec_info;
- armv4_5_common_t *armv4_5 = NULL;
+ struct arm *armv4_5 = NULL;
struct arm7_9_common *arm7_9 = NULL;
struct arm_jtag *jtag_info = NULL;
struct arm7_9_common *arm7_9 = NULL;
struct arm_jtag *jtag_info = NULL;
* targets
* @return ERROR_OK if successful
*/
* targets
* @return ERROR_OK if successful
*/
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p)
+int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct armv4_5_common_s *armv4_5 = &arm7_9->armv4_5_common;
int spsr;
int retval;
target_t *target = get_current_target(cmd_ctx);
int spsr;
int retval;
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
int spsr;
int retval;
target_t *target = get_current_target(cmd_ctx);
int spsr;
int retval;
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
uint32_t mode;
int num;
target_t *target = get_current_target(cmd_ctx);
uint32_t mode;
int num;
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
{
target_t *target = get_current_target(cmd_ctx);
COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
{
target_t *target = get_current_target(cmd_ctx);
COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
{
target_t *target = get_current_target(cmd_ctx);
COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
{
target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
struct arm7_9_common *arm7_9;
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
+ struct arm *armv4_5 = &arm7_9->armv4_5_common;
arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
int arm7_9_execute_sys_speed(struct target_s *target);
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
int arm7_9_execute_sys_speed(struct target_s *target);
int arm7_9_init_arch_info(target_t *target, struct arm7_9_common *arm7_9);
-int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, struct arm7_9_common **arm7_9_p);
+int arm7_9_get_arch_pointers(target_t *target, struct arm **armv4_5_p, struct arm7_9_common **arm7_9_p);
#endif /* ARM7_9_COMMON_H */
#endif /* ARM7_9_COMMON_H */
int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap)
{
int arm9tdmi_init_arch_info(target_t *target, struct arm9tdmi_common *arm9tdmi, struct jtag_tap *tap)
{
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
struct arm7_9_common *arm7_9;
arm7_9 = &arm9tdmi->arm7_9_common;
static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
{
static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
}
static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
{
return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
}
static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
}
static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
{
buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
}
static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32);
return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32);
static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
{
static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32, value);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, reg).value, 0, 32, value);
static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
{
static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
}
static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
{
return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
}
static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
return armv4_5->core_state;
}
static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
{
return armv4_5->core_state;
}
static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
armv4_5->core_state = mode;
}
armv4_5->core_state = mode;
}
static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
{
static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
{
- armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+ struct arm *armv4_5 = (struct arm *)sim->user_data;
return armv4_5->core_mode;
}
return armv4_5->core_mode;
}
-struct reg_cache* armv4_5_build_reg_cache(target_t *target, armv4_5_common_t *armv4_5_common)
+struct reg_cache* armv4_5_build_reg_cache(target_t *target, struct arm *armv4_5_common)
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
{
int num_regs = 37;
struct reg_cache *cache = malloc(sizeof(struct reg_cache));
return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
}
return armv4_5_run_algorithm_inner(target, num_mem_params, mem_params, num_reg_params, reg_params, entry_point, exit_point, timeout_ms, arch_info, armv4_5_run_algorithm_completion);
}
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5)
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5)
{
target->arch_info = armv4_5;
{
target->arch_info = armv4_5;
* Cortex-M series cores do not support as many core states or shadowed
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
* Cortex-M series cores do not support as many core states or shadowed
* registers as traditional ARM cores, and only support Thumb2 instructions.
*/
{
int common_magic;
struct reg_cache *core_cache;
{
int common_magic;
struct reg_cache *core_cache;
int (*write_core_reg)(struct target_s *target,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
int (*write_core_reg)(struct target_s *target,
int num, enum armv4_5_mode mode, uint32_t value);
void *arch_info;
#define target_to_armv4_5 target_to_arm
#define target_to_armv4_5 target_to_arm
int num;
enum armv4_5_mode mode;
target_t *target;
int num;
enum armv4_5_mode mode;
target_t *target;
- armv4_5_common_t *armv4_5_common;
+ struct arm *armv4_5_common;
};
struct reg_cache* armv4_5_build_reg_cache(target_t *target,
};
struct reg_cache* armv4_5_build_reg_cache(target_t *target,
- armv4_5_common_t *armv4_5_common);
+ struct arm *armv4_5_common);
/* map psr mode bits to linear number */
static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
/* map psr mode bits to linear number */
static __inline int armv4_5_mode_to_number(enum armv4_5_mode mode)
reg_t **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
reg_t **reg_list[], int *reg_list_size);
int armv4_5_register_commands(struct command_context_s *cmd_ctx);
-int armv4_5_init_arch_info(target_t *target, armv4_5_common_t *armv4_5);
+int armv4_5_init_arch_info(target_t *target, struct arm *armv4_5);
int armv4_5_run_algorithm(struct target_s *target,
int num_mem_params, struct mem_param *mem_params,
int armv4_5_run_algorithm(struct target_s *target,
int num_mem_params, struct mem_param *mem_params,
/* Cache and Memory Management Unit */
struct armv4_5_mmu_common armv4_5_mmu;
/* Cache and Memory Management Unit */
struct armv4_5_mmu_common armv4_5_mmu;
- armv4_5_common_t armv4_5_common;
+ struct arm armv4_5_common;
// int (*full_context)(struct target_s *target);
// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
// int (*full_context)(struct target_s *target);
// int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
int cortex_a8_init_arch_info(target_t *target,
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
int cortex_a8_init_arch_info(target_t *target,
struct cortex_a8_common *cortex_a8, struct jtag_tap *tap)
{
- armv4_5_common_t *armv4_5;
struct armv7a_common *armv7a;
armv7a = &cortex_a8->armv7a_common;
struct armv7a_common *armv7a;
armv7a = &cortex_a8->armv7a_common;
int feroceon_assert_reset(target_t *target)
{
int feroceon_assert_reset(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int ud = arm7_9->use_dbgrq;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
int ud = arm7_9->use_dbgrq;
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
void feroceon_change_to_arm(target_t *target, uint32_t *r0, uint32_t *pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
void feroceon_read_core_regs(target_t *target, uint32_t mask, uint32_t* core_regs[16])
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
{
int i;
void feroceon_read_core_regs_target_buffer(target_t *target, uint32_t mask, void* buffer, int size)
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
void feroceon_read_xpsr(target_t *target, uint32_t *xpsr, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
void feroceon_write_xpsr(target_t *target, uint32_t xpsr, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
void feroceon_write_xpsr_im8(target_t *target, uint8_t xpsr_im, int rot, int spsr)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
void feroceon_write_core_regs(target_t *target, uint32_t mask, uint32_t core_regs[16])
{
int i;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_branch_resume(target_t *target)
{
void feroceon_branch_resume(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
int feroceon_read_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int err;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
int err;
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
int feroceon_write_cp15(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
struct arm_jtag *jtag_info = &arm7_9->jtag_info;
void feroceon_set_dbgrq(target_t *target)
{
void feroceon_set_dbgrq(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
void feroceon_enable_single_step(target_t *target, uint32_t next_pc)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* set a breakpoint there */
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* set a breakpoint there */
void feroceon_disable_single_step(target_t *target)
{
void feroceon_disable_single_step(target_t *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int retval;
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
enum armv4_5_state core_state = armv4_5->core_state;
uint32_t x, flip, shift, save[7];
void feroceon_common_setup(struct target_s *target)
{
void feroceon_common_setup(struct target_s *target)
{
- armv4_5_common_t *armv4_5 = target->arch_info;
+ struct arm *armv4_5 = target->arch_info;
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
struct arm7_9_common *arm7_9 = armv4_5->arch_info;
/* override some insn sequence functions */
int feroceon_examine(struct target_s *target)
{
int feroceon_examine(struct target_s *target)
{
- armv4_5_common_t *armv4_5;
struct arm7_9_common *arm7_9;
int retval;
struct arm7_9_common *arm7_9;
int retval;
static int xscale_init_arch_info(target_t *target,
struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
{
static int xscale_init_arch_info(target_t *target,
struct xscale_common *xscale, struct jtag_tap *tap, const char *variant)
{
- armv4_5_common_t *armv4_5;
uint32_t high_reset_branch, low_reset_branch;
int i;
uint32_t high_reset_branch, low_reset_branch;
int i;
struct xscale_common
{
/* armv4/5 common stuff */
struct xscale_common
{
/* armv4/5 common stuff */
- armv4_5_common_t armv4_5_common;
+ struct arm armv4_5_common;
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