at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
+ fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
- cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
+ cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
#define KB 1024
#define MB (1024*1024)
-#define ERASE_REGION(num, size) (((size/256)<<16)|(num-1))
+#define ERASE_REGION(num, size) (((size/256) << 16)|(num-1))
/* non-CFI compatible flashes */
non_cfi_t non_cfi_flashes[] = {
*dcc_bufptr &= *(buffer++) | 0xffffff00;
break;
case 1:
- *dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
+ *dcc_bufptr &= ((*(buffer++)) << 8) | 0xffff00ff;
break;
case 2:
- *dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
+ *dcc_bufptr &= ((*(buffer++)) << 16) | 0xff00ffff;
break;
case 3:
- *dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
+ *dcc_bufptr &= ((*(buffer++)) << 24) | 0x00ffffff;
chksum ^= *(dcc_bufptr++);
*dcc_bufptr = 0xffffffff;
byteofs = 0;
dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */
- dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
+ dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
break;
case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE|flash_erase_all());
}
/* page number and page write command to FCR */
- outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
- outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
}
target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
- if ((devcfg0 & (1<<28)) == 0) /* code protect bit */
+ if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
{
- if (devcfg0 & (1<<24))
+ if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
num_pages = 0xffff; /* All pages protected */
#define PIC32MX_NVMCONCLR 0xBF80F404
#define PIC32MX_NVMCONSET 0xBF80F408
#define PIC32MX_NVMCONINV 0xBF80F40C
-#define NVMCON_NVMWR (1<<15)
-#define NVMCON_NVMWREN (1<<14)
-#define NVMCON_NVMERR (1<<13)
-#define NVMCON_LVDERR (1<<12)
-#define NVMCON_LVDSTAT (1<<11)
+#define NVMCON_NVMWR (1 << 15)
+#define NVMCON_NVMWREN (1 << 14)
+#define NVMCON_NVMERR (1 << 13)
+#define NVMCON_LVDERR (1 << 12)
+#define NVMCON_LVDSTAT (1 << 11)
#define NVMCON_OP_PFM_ERASE 0x5
#define NVMCON_OP_PAGE_ERASE 0x4
#define NVMCON_OP_ROW_PROG 0x3
#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
-#define S3C2410_NFCONF_EN (1<<15)
-#define S3C2410_NFCONF_512BYTE (1<<14)
-#define S3C2410_NFCONF_4STEP (1<<13)
-#define S3C2410_NFCONF_INITECC (1<<12)
-#define S3C2410_NFCONF_nFCE (1<<11)
-#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
-#define S3C2440_NFCONF_ADVFLASH (1<<3)
-#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
-#define S3C2440_NFCONT_SOFTLOCK (1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
-#define S3C2440_NFCONT_RNBINT_EN (1<<9)
-#define S3C2440_NFCONT_RN_FALLING (1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
-#define S3C2440_NFCONT_INITECC (1<<4)
-#define S3C2440_NFCONT_nFCE (1<<1)
-#define S3C2440_NFCONT_ENABLE (1<<0)
-
-#define S3C2440_NFSTAT_READY (1<<0)
-#define S3C2440_NFSTAT_nCE (1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT (1<<31)
-#define S3C2412_NFCONF_ECCCLKCON (1<<30)
-#define S3C2412_NFCONF_ECC_MLC (1<<24)
-#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
-#define S3C2412_NFCONT_SOFTLOCK (1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
-#define S3C2412_NFCONT_nFCE1 (1<<2)
-#define S3C2412_NFCONT_nFCE0 (1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
-#define S3C2412_NFSTAT_nFCE1 (1<<3)
-#define S3C2412_NFSTAT_nFCE0 (1<<2)
-#define S3C2412_NFSTAT_Res1 (1<<1)
-#define S3C2412_NFSTAT_READY (1<<0)
+#define S3C2410_NFCONF_EN (1 << 15)
+#define S3C2410_NFCONF_512BYTE (1 << 14)
+#define S3C2410_NFCONF_4STEP (1 << 13)
+#define S3C2410_NFCONF_INITECC (1 << 12)
+#define S3C2410_NFCONF_nFCE (1 << 11)
+#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
+#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
+#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
+
+#define S3C2410_NFSTAT_BUSY (1 << 0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8 (0 << 0)
+#define S3C2440_NFCONF_BUSWIDTH_16 (1 << 0)
+#define S3C2440_NFCONF_ADVFLASH (1 << 3)
+#define S3C2440_NFCONF_TACLS(x) ((x) << 12)
+#define S3C2440_NFCONF_TWRPH0(x) ((x) << 8)
+#define S3C2440_NFCONF_TWRPH1(x) ((x) << 4)
+
+#define S3C2440_NFCONT_LOCKTIGHT (1 << 13)
+#define S3C2440_NFCONT_SOFTLOCK (1 << 12)
+#define S3C2440_NFCONT_ILLEGALACC_EN (1 << 10)
+#define S3C2440_NFCONT_RNBINT_EN (1 << 9)
+#define S3C2440_NFCONT_RN_FALLING (1 << 8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
+#define S3C2440_NFCONT_INITECC (1 << 4)
+#define S3C2440_NFCONT_nFCE (1 << 1)
+#define S3C2440_NFCONT_ENABLE (1 << 0)
+
+#define S3C2440_NFSTAT_READY (1 << 0)
+#define S3C2440_NFSTAT_nCE (1 << 1)
+#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
+
+#define S3C2412_NFCONF_NANDBOOT (1 << 31)
+#define S3C2412_NFCONF_ECCCLKCON (1 << 30)
+#define S3C2412_NFCONF_ECC_MLC (1 << 24)
+#define S3C2412_NFCONF_TACLS_MASK (7 << 12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR (1 << 18)
+#define S3C2412_NFCONT_LOCKTIGHT (1 << 17)
+#define S3C2412_NFCONT_SOFTLOCK (1 << 16)
+#define S3C2412_NFCONT_ECC4_ENCINT (1 << 13)
+#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
+#define S3C2412_NFCONT_nFCE1 (1 << 2)
+#define S3C2412_NFCONT_nFCE0 (1 << 1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
+#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
+#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
+#define S3C2412_NFSTAT_nFCE1 (1 << 3)
+#define S3C2412_NFSTAT_nFCE0 (1 << 2)
+#define S3C2412_NFSTAT_Res1 (1 << 1)
+#define S3C2412_NFSTAT_READY (1 << 0)
#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
for (lockregion = first; lockregion <= last; lockregion++)
{
if (set)
- fmppe &= ~(1<<lockregion);
+ fmppe &= ~(1 << lockregion);
else
- fmppe |= (1<<lockregion);
+ fmppe |= (1 << lockregion);
}
/* Clear and disable flash programming interrupts */
#define PMASK 2
/* Flash Controller Command bits */
-#define FMC_WRKEY (0xA442<<16)
-#define FMC_COMT (1<<3)
-#define FMC_MERASE (1<<2)
-#define FMC_ERASE (1<<1)
-#define FMC_WRITE (1<<0)
+#define FMC_WRKEY (0xA442 << 16)
+#define FMC_COMT (1 << 3)
+#define FMC_MERASE (1 << 2)
+#define FMC_ERASE (1 << 1)
+#define FMC_WRITE (1 << 0)
/* STELLARIS constants */
if (strcmp(args[1], "SWWDG") == 0)
{
- optionbyte |= (1<<0);
+ optionbyte |= (1 << 0);
}
else
{
- optionbyte &= ~(1<<0);
+ optionbyte &= ~(1 << 0);
}
if (strcmp(args[2], "NORSTSTNDBY") == 0)
{
- optionbyte |= (1<<1);
+ optionbyte |= (1 << 1);
}
else
{
- optionbyte &= ~(1<<1);
+ optionbyte &= ~(1 << 1);
}
if (strcmp(args[3], "NORSTSTOP") == 0)
{
- optionbyte |= (1<<2);
+ optionbyte |= (1 << 2);
}
else
{
- optionbyte &= ~(1<<2);
+ optionbyte &= ~(1 << 2);
}
if (stm32x_erase_options(bank) != ERROR_OK)
/* FLASH_CR register bits */
-#define FLASH_PG (1<<0)
-#define FLASH_PER (1<<1)
-#define FLASH_MER (1<<2)
-#define FLASH_OPTPG (1<<4)
-#define FLASH_OPTER (1<<5)
-#define FLASH_STRT (1<<6)
-#define FLASH_LOCK (1<<7)
-#define FLASH_OPTWRE (1<<9)
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER (1 << 2)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_STRT (1 << 6)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_OPTWRE (1 << 9)
/* FLASH_SR register bits */
-#define FLASH_BSY (1<<0)
-#define FLASH_PGERR (1<<2)
-#define FLASH_WRPRTERR (1<<4)
-#define FLASH_EOP (1<<5)
+#define FLASH_BSY (1 << 0)
+#define FLASH_PGERR (1 << 2)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_EOP (1 << 5)
/* STM32_FLASH_OBR bit definitions (reading) */
/* set default bits for str71x flash */
str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA1|FLASH_BSYA0);
- str7x_info->disable_bit = (1<<1);
+ str7x_info->disable_bit = (1 << 1);
if (strcmp(args[6], "STR71x") == 0)
{
else if (strcmp(args[6], "STR75x") == 0)
{
str7x_info->register_base = 0x20100000;
- str7x_info->disable_bit = (1<<0);
+ str7x_info->disable_bit = (1 << 0);
}
else
{
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
- target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1<<(15+ProtectionLevel)));
+ target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1 << (15+ProtectionLevel)));
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
}
offset += bank->sectors[i].size;
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
- str9x_info->sector_bits[num_sectors++] = (1<<i);
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
}
for (i = 0; i < b1_sectors; i++)
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
if (str9x_info->variant)
- str9x_info->sector_bits[num_sectors++] = (1<<i);
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
else
- str9x_info->sector_bits[num_sectors++] = (1<<(i+8));
+ str9x_info->sector_bits[num_sectors++] = (1 << (i+8));
}
return ERROR_OK;
{
if ((num==32) && (first==0))
{
- return (((uint32_t)buffer[3])<<24)|(((uint32_t)buffer[2])<<16)|(((uint32_t)buffer[1])<<8)|(((uint32_t)buffer[0])<<0);
+ return (((uint32_t)buffer[3]) << 24)|(((uint32_t)buffer[2]) << 16)|(((uint32_t)buffer[1]) << 8)|(((uint32_t)buffer[0]) << 0);
} else
{
uint32_t result = 0;
{
unsigned int h = 0;
while (len--)
- h += (h<<3)+*buf++;
+ h += (h << 3)+*buf++;
return h;
}
case JIM_EXPROP_GT: wC = wA>wB; break;
case JIM_EXPROP_LTE: wC = wA <= wB; break;
case JIM_EXPROP_GTE: wC = wA >= wB; break;
- case JIM_EXPROP_LSHIFT: wC = wA<<wB; break;
+ case JIM_EXPROP_LSHIFT: wC = wA << wB; break;
case JIM_EXPROP_RSHIFT: wC = wA >> wB; break;
case JIM_EXPROP_NUMEQ: wC = wA==wB; break;
case JIM_EXPROP_NUMNE: wC = wA != wB; break;
wC = _rotl(uA,(unsigned long)wB);
#else
const unsigned int S = sizeof(unsigned long) * 8;
- wC = (unsigned long)((uA<<wB)|(uA >> (S-wB)));
+ wC = (unsigned long)((uA << wB)|(uA >> (S-wB)));
#endif
break;
}
wC = _rotr(uA,(unsigned long)wB);
#else
const unsigned int S = sizeof(unsigned long) * 8;
- wC = (unsigned long)((uA >> wB)|(uA<<(S-wB)));
+ wC = (unsigned long)((uA >> wB)|(uA << (S-wB)));
#endif
break;
}
return JIM_ERR;
}
-#define JIM_MATCHVER_EXACT (1<<JIM_PRIV_FLAG_SHIFT)
+#define JIM_MATCHVER_EXACT (1 << JIM_PRIV_FLAG_SHIFT)
static int JimPackageMatchVersion(int needed, int actual, int flags)
{
if (needed == JIM_PKG_ANY_VERSION) return 1;
static void armjtagew_reset(int trst, int srst)
{
- const uint8_t trst_mask = (1u<<5);
- const uint8_t srst_mask = (1u<<6);
+ const uint8_t trst_mask = (1u << 5);
+ const uint8_t srst_mask = (1u << 6);
uint8_t val = 0;
uint8_t outp_en = 0;
uint8_t change_mask = 0;
int tms=(bit_cnt==scan_size-1) ? 1 : 0;
int tdi;
int bytec=bit_cnt/8;
- int bcval=1<<(bit_cnt % 8);
+ int bcval=1 << (bit_cnt % 8);
/* if we're just reading the scan, but don't care about the output
* default to outputting 'low', this also makes valgrind traces more readable,
static int dummy_read(void)
{
int data = 1 & dummy_data;
- dummy_data = (dummy_data >> 1) | (1<<31);
+ dummy_data = (dummy_data >> 1) | (1 << 31);
return data;
}
bool bit = tms_bits & 1;
if (bit)
- tms_byte |= (1<<tms_ndx);
+ tms_byte |= (1 << tms_ndx);
/* always do state transitions in public view */
tap_set_state(tap_state_transition(tap_get_state(), bit));
if (tap_state_transition(walker, false) == desired_next_state)
; /* bit within tms_bits at index state_ndx is already zero */
else if (tap_state_transition(walker, true) == desired_next_state)
- tms_bits |= (1<<state_ndx);
+ tms_bits |= (1 << state_ndx);
else
{
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
#define HEX__(n) 0x##n##LU
#define B8__(x) \
- (((x) & 0x0000000FLU)?(1<<0):0) \
- +(((x) & 0x000000F0LU)?(1<<1):0) \
- +(((x) & 0x00000F00LU)?(1<<2):0) \
- +(((x) & 0x0000F000LU)?(1<<3):0) \
- +(((x) & 0x000F0000LU)?(1<<4):0) \
- +(((x) & 0x00F00000LU)?(1<<5):0) \
- +(((x) & 0x0F000000LU)?(1<<6):0) \
- +(((x) & 0xF0000000LU)?(1<<7):0)
+ (((x) & 0x0000000FLU)?(1 << 0):0) \
+ +(((x) & 0x000000F0LU)?(1 << 1):0) \
+ +(((x) & 0x00000F00LU)?(1 << 2):0) \
+ +(((x) & 0x0000F000LU)?(1 << 3):0) \
+ +(((x) & 0x000F0000LU)?(1 << 4):0) \
+ +(((x) & 0x00F00000LU)?(1 << 5):0) \
+ +(((x) & 0x0F000000LU)?(1 << 6):0) \
+ +(((x) & 0xF0000000LU)?(1 << 7):0)
#define B8(bits,count) { ((uint8_t)B8__(HEX__(bits))), (count) }
unsigned char output_value=0x00;
if (tms)
- output_value |= (1<<TMS_BIT);
+ output_value |= (1 << TMS_BIT);
if (tdi)
- output_value |= (1<<TDI_BIT);
+ output_value |= (1 << TDI_BIT);
if (tck)
- output_value |= (1<<TCK_BIT);
+ output_value |= (1 << TCK_BIT);
usbprog_jtag_write_slice(usbprog_jtag_handle,output_value);
}
}
waitQueue();
sampleShiftRegister();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|a);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|a);
}
}
/* shift out value */
waitIdle();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x28, (((value >> i)&1)<<1)|tms);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x28, (((value >> i)&1) << 1)|tms);
}
waitIdle();
ZY1000_POKE(ZY1000_JTAG_BASE+0x28, 0);
setCurrentState(endState);
} else
{
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
}
#else
/* fast version */
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
#endif
#else
/* maximum debug version */
{
sampleShiftRegister();
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value >> i);
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<8)|(a<<4)|a);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 8)|(a << 4)|a);
}
sampleShiftRegister();
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value >> (repeat-1));
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 8)|(a << 4)|b);
} else
{
sampleShiftRegister();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
}
sampleShiftRegister();
#endif
a=state;
b=endState;
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value);
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<15)|(repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 15)|(repeat << 8)|(a << 4)|b);
VERBOSE(getShiftValueFlip());
}
#endif
}
}
/* mask away unused bits for easier debugging */
- value&=~(((uint32_t)0xffffffff)<<k);
+ value&=~(((uint32_t)0xffffffff) << k);
shiftValueInner(shiftState, pause_state, k, value);
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
- shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1 << 5));
buffer += 4;
}
} else
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
- shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1 << 5));
buffer += 4;
}
}
int i;
for (i = 0; i < str_len; i += 2)
{
- uint8_t t = hextoint(tstr[i])<<4;
+ uint8_t t = hextoint(tstr[i]) << 4;
t |= hextoint(tstr[i+1]);
int j = gdb_reg_pos(target, i/2, str_len/2);
int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
{
uint32_t select;
- select = (apsel<<24) & 0xFF000000;
+ select = (apsel << 24) & 0xFF000000;
if (select != swjdp->apsel)
{
#define DP_SELECT 0x8
#define DP_RDBUFF 0xC
-#define CORUNDETECT (1<<0)
-#define SSTICKYORUN (1<<1)
-#define SSTICKYERR (1<<5)
-#define CDBGRSTREQ (1<<26)
-#define CDBGRSTACK (1<<27)
-#define CDBGPWRUPREQ (1<<28)
-#define CDBGPWRUPACK (1<<29)
-#define CSYSPWRUPREQ (1<<30)
-#define CSYSPWRUPACK (1<<31)
+#define CORUNDETECT (1 << 0)
+#define SSTICKYORUN (1 << 1)
+#define SSTICKYERR (1 << 5)
+#define CDBGRSTREQ (1 << 26)
+#define CDBGRSTACK (1 << 27)
+#define CDBGPWRUPREQ (1 << 28)
+#define CDBGPWRUPACK (1 << 29)
+#define CSYSPWRUPREQ (1 << 30)
+#define CSYSPWRUPACK (1 << 31)
#define AP_REG_CSW 0x00
#define AP_REG_TAR 0x04
#define CSW_16BIT 1
#define CSW_32BIT 2
-#define CSW_ADDRINC_MASK (3<<4)
+#define CSW_ADDRINC_MASK (3 << 4)
#define CSW_ADDRINC_OFF 0
-#define CSW_ADDRINC_SINGLE (1<<4)
-#define CSW_ADDRINC_PACKED (2<<4)
-#define CSW_HPROT (1<<25)
-#define CSW_MASTER_DEBUG (1<<29)
-#define CSW_DBGSWENABLE (1<<31)
+#define CSW_ADDRINC_SINGLE (1 << 4)
+#define CSW_ADDRINC_PACKED (2 << 4)
+#define CSW_HPROT (1 << 25)
+#define CSW_MASTER_DEBUG (1 << 29)
+#define CSW_DBGSWENABLE (1 << 31)
/* transaction mode */
#define TRANS_MODE_NONE 0
if (((opc==0) || (opc==2)) && (offset & 0x00000400))
offset = 0xfffff800 | offset;
- target_address = address + 4 + (offset<<1);
+ target_address = address + 4 + (offset << 1);
switch (opc)
{
case 2:
instruction->type = ARM_UNKNOWN_INSTUCTION;
mnemonic = "prefix";
- target_address = offset<<12;
+ target_address = offset << 12;
break;
/* BL suffix */
case 3:
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
uint8_t Rm_imm = (opcode >> 6) & 0x7;
- uint32_t opc = opcode & (1<<9);
- uint32_t reg_imm = opcode & (1<<10);
+ uint32_t opc = opcode & (1 << 9);
+ uint32_t reg_imm = opcode & (1 << 10);
char *mnemonic;
if (opc)
uint32_t offset = (opcode >> 6) & 0x1f;
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
- uint32_t L = opcode & (1<<11);
- uint32_t B = opcode & (1<<12);
+ uint32_t L = opcode & (1 << 11);
+ uint32_t B = opcode & (1 << 12);
char *mnemonic;
char suffix = ' ';
uint32_t shift = 2;
shift = 0;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
+ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = Rn;
instruction->info.load_store.index_mode = 0; /*offset*/
instruction->info.load_store.offset_mode = 0; /*immediate*/
- instruction->info.load_store.offset.offset = offset<<shift;
+ instruction->info.load_store.offset.offset = offset << shift;
return ERROR_OK;
}
{
uint32_t offset = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
- uint32_t L = opcode & (1<<11);
+ uint32_t L = opcode & (1 << 11);
char *mnemonic;
if (L)
uint32_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
uint8_t Rn;
- uint32_t SP = opcode & (1<<11);
+ uint32_t SP = opcode & (1 << 11);
char *reg_name;
instruction->type = ARM_ADD;
int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
{
uint32_t imm = opcode & 0x7f;
- uint8_t opc = opcode & (1<<7);
+ uint8_t opc = opcode & (1 << 7);
char *mnemonic;
int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
{
uint32_t reg_list = opcode & 0xff;
- uint32_t L = opcode & (1<<11);
- uint32_t R = opcode & (1<<8);
+ uint32_t L = opcode & (1 << 11);
+ uint32_t R = opcode & (1 << 8);
uint8_t Rn = (opcode >> 8) & 7;
uint8_t addr_mode = 0 /* IA */;
char reg_names[40];
instruction->type = ARM_LDM;
mnemonic = "POP";
if (R)
- reg_list |= (1<<15) /*PC*/;
+ reg_list |= (1 << 15) /*PC*/;
}
else
{
mnemonic = "PUSH";
addr_mode = 3; /*DB*/
if (R)
- reg_list |= (1<<14) /*LR*/;
+ reg_list |= (1 << 14) /*LR*/;
}
}
reg_names_p = reg_names;
for (i = 0; i <= 15; i++)
{
- if (reg_list & (1<<i))
+ if (reg_list & (1 << i))
reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i);
}
if (reg_names_p>reg_names)
if (offset & 0x00000080)
offset = 0xffffff00 | offset;
- target_address = address + 4 + (offset<<1);
+ target_address = address + 4 + (offset << 1);
snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
arm_condition_strings[cond], target_address);
* Rd: destination register
* SYSm: source special register
*/
-#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
+#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
* Rd: source register
* SYSm: destination special register
*/
-#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
+#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16))
/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
*/
#define I_FLAG 2
#define F_FLAG 1
-#define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
-#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
+#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
+#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
/* Breakpoint (Thumb mode) v5 onwards
* Im: immediate value used by debugger
/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
armv7m->swjdp_info.memaccess_tck = 8;
- armv7m->swjdp_info.tar_autoincr_block = (1<<12); /* Cortex-M3 has 4096 bytes autoincrement range */
+ armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
/* initialize arch-specific breakpoint handling */
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
-#define DCRSR_WnR (1<<16)
+#define DCRSR_WnR (1 << 16)
#define DWT_CTRL 0xE0001000
#define DWT_COMP0 0xE0001020
#define DWT_CTRL 0xE0001000
/* DCB_DHCSR bit and field definitions */
-#define DBGKEY (0xA05F<<16)
-#define C_DEBUGEN (1<<0)
-#define C_HALT (1<<1)
-#define C_STEP (1<<2)
-#define C_MASKINTS (1<<3)
-#define S_REGRDY (1<<16)
-#define S_HALT (1<<17)
-#define S_SLEEP (1<<18)
-#define S_LOCKUP (1<<19)
-#define S_RETIRE_ST (1<<24)
-#define S_RESET_ST (1<<25)
+#define DBGKEY (0xA05F << 16)
+#define C_DEBUGEN (1 << 0)
+#define C_HALT (1 << 1)
+#define C_STEP (1 << 2)
+#define C_MASKINTS (1 << 3)
+#define S_REGRDY (1 << 16)
+#define S_HALT (1 << 17)
+#define S_SLEEP (1 << 18)
+#define S_LOCKUP (1 << 19)
+#define S_RETIRE_ST (1 << 24)
+#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1<<24)
-#define VC_HARDERR (1<<10)
-#define VC_BUSERR (1<<8)
-#define VC_CORERESET (1<<0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_BUSERR (1 << 8)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
#define NVIC_BFAR 0xE000ED38
/* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY (0x5FA<<16)
-#define AIRCR_SYSRESETREQ (1<<2)
-#define AIRCR_VECTCLRACTIVE (1<<1)
-#define AIRCR_VECTRESET (1<<0)
+#define AIRCR_VECTKEY (0x5FA << 16)
+#define AIRCR_SYSRESETREQ (1 << 2)
+#define AIRCR_VECTCLRACTIVE (1 << 1)
+#define AIRCR_VECTRESET (1 << 0)
/* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA (1<<17)
+#define SHCSR_BUSFAULTENA (1 << 17)
/* NVIC_DFSR bits */
#define DFSR_HALTED 1
#define DFSR_BKPT 2
#define FPCR_CODE 0
#define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP (0<<30)
-#define FPCR_REPLACE_BKPT_LOW (1<<30)
-#define FPCR_REPLACE_BKPT_HIGH (2<<30)
-#define FPCR_REPLACE_BKPT_BOTH (3<<30)
+#define FPCR_REPLACE_REMAP (0 << 30)
+#define FPCR_REPLACE_BKPT_LOW (1 << 30)
+#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
+#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
typedef struct cortex_m3_fp_comparator_s
{
if (enable)
{
- if (!(dcr & (1<<4)))
+ if (!(dcr & (1 << 4)))
{
/* enable interrupts */
- dcr |= (1<<4);
+ dcr |= (1 << 4);
update = 1;
}
}
else
{
- if (dcr & (1<<4))
+ if (dcr & (1 << 4))
{
/* disable interrupts */
- dcr &= ~(1<<4);
+ dcr &= ~(1 << 4);
update = 1;
}
}
#define MIPS32_COP0_MF 0x00
#define MIPS32_COP0_MT 0x04
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr) (((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|(immd))
+#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
#define MIPS32_NOP 0
#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
break;
}
LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
- ejtag_info->impcode & (1<<28) ? " R3k": " R4k",
- ejtag_info->impcode & (1<<24) ? " DINT": "",
- ejtag_info->impcode & (1<<22) ? " ASID_8": "",
- ejtag_info->impcode & (1<<21) ? " ASID_6": "",
- ejtag_info->impcode & (1<<16) ? " MIPS16": "",
- ejtag_info->impcode & (1<<14) ? " noDMA": " DMA",
- ejtag_info->impcode & (1<<0) ? " MIPS64": " MIPS32"
+ ejtag_info->impcode & (1 << 28) ? " R3k": " R4k",
+ ejtag_info->impcode & (1 << 24) ? " DINT": "",
+ ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
+ ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
+ ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
+ ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
+ ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
);
- if ((ejtag_info->impcode & (1<<14)) == 0)
+ if ((ejtag_info->impcode & (1 << 14)) == 0)
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
/* set initial state for ejtag control reg */
Code Review / openocd.git / commitdiff