build: cleanup src/flash/nor directory
authorSpencer Oliver <spen@spen-soft.co.uk>
Tue, 31 Jan 2012 17:55:03 +0000 (17:55 +0000)
committerSpencer Oliver <spen@spen-soft.co.uk>
Mon, 6 Feb 2012 10:54:14 +0000 (10:54 +0000)
Change-Id: Ic299de969ce566282c055ba4dd8b94892c4c4311
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/420
Tested-by: jenkins
36 files changed:
src/flash/nor/aduc702x.c
src/flash/nor/at91sam3.c
src/flash/nor/at91sam7.c
src/flash/nor/avrf.c
src/flash/nor/cfi.c
src/flash/nor/cfi.h
src/flash/nor/core.c
src/flash/nor/core.h
src/flash/nor/driver.h
src/flash/nor/drivers.c
src/flash/nor/dsp5680xx_flash.c
src/flash/nor/ecos.c
src/flash/nor/em357.c
src/flash/nor/faux.c
src/flash/nor/fm3.c
src/flash/nor/imp.h
src/flash/nor/kinetis.c
src/flash/nor/lpc2000.c
src/flash/nor/lpc288x.c
src/flash/nor/lpc2900.c
src/flash/nor/non_cfi.c
src/flash/nor/non_cfi.h
src/flash/nor/ocl.c
src/flash/nor/ocl.h
src/flash/nor/pic32mx.c
src/flash/nor/stellaris.c
src/flash/nor/stm32f1x.c
src/flash/nor/stm32f2x.c
src/flash/nor/stm32lx.c
src/flash/nor/stmsmi.c
src/flash/nor/str7x.c
src/flash/nor/str9x.c
src/flash/nor/str9xpec.c
src/flash/nor/tcl.c
src/flash/nor/tms470.c
src/flash/nor/virtual.c

index 02270ae..dde4e69 100644 (file)
 #include <target/algorithm.h>
 #include <target/arm.h>
 
-
 static int aduc702x_build_sector_list(struct flash_bank *bank);
-static int aduc702x_check_flash_completion(struct targettarget, unsigned int timeout_ms);
+static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
 static int aduc702x_set_write_enable(struct target *target, int enable);
 
-#define ADUC702x_FLASH                         0xfffff800
-#define ADUC702x_FLASH_FEESTA          (0*4)
-#define ADUC702x_FLASH_FEEMOD          (1*4)
-#define ADUC702x_FLASH_FEECON          (2*4)
-#define ADUC702x_FLASH_FEEDAT          (3*4)
-#define ADUC702x_FLASH_FEEADR          (4*4)
-#define ADUC702x_FLASH_FEESIGN         (5*4)
-#define ADUC702x_FLASH_FEEPRO          (6*4)
-#define ADUC702x_FLASH_FEEHIDE         (7*4)
+#define ADUC702x_FLASH                          0xfffff800
+#define ADUC702x_FLASH_FEESTA           (0*4)
+#define ADUC702x_FLASH_FEEMOD           (1*4)
+#define ADUC702x_FLASH_FEECON           (2*4)
+#define ADUC702x_FLASH_FEEDAT           (3*4)
+#define ADUC702x_FLASH_FEEADR           (4*4)
+#define ADUC702x_FLASH_FEESIGN          (5*4)
+#define ADUC702x_FLASH_FEEPRO           (6*4)
+#define ADUC702x_FLASH_FEEHIDE          (7*4)
 
 struct aduc702x_flash_bank {
        struct working_area *write_algorithm;
@@ -56,33 +55,32 @@ FLASH_BANK_COMMAND_HANDLER(aduc702x_flash_bank_command)
 
        nbank = malloc(sizeof(struct aduc702x_flash_bank));
 
-        bank->base = 0x80000;
-        bank->size = 0xF800; // top 4k not accessible
+       bank->base = 0x80000;
+       bank->size = 0xF800;    /* top 4k not accessible */
        bank->driver_priv = nbank;
 
-        aduc702x_build_sector_list(bank);
+       aduc702x_build_sector_list(bank);
 
-        return ERROR_OK;
+       return ERROR_OK;
 }
 
 static int aduc702x_build_sector_list(struct flash_bank *bank)
 {
-       //aduc7026_struct flash_bank *aduc7026_info = bank->driver_priv;
-
-        int i = 0;
-        uint32_t offset = 0;
-
-        // sector size is 512
-        bank->num_sectors = bank->size / 512;
-        bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
-        for (i = 0; i < bank->num_sectors; ++i)
-        {
-                bank->sectors[i].offset = offset;
-                bank->sectors[i].size = 512;
-                offset += bank->sectors[i].size;
-                bank->sectors[i].is_erased = -1;
-                bank->sectors[i].is_protected = 0;
-        }
+       /* aduc7026_struct flash_bank *aduc7026_info = bank->driver_priv; */
+
+       int i = 0;
+       uint32_t offset = 0;
+
+       /* sector size is 512 */
+       bank->num_sectors = bank->size / 512;
+       bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+       for (i = 0; i < bank->num_sectors; ++i) {
+               bank->sectors[i].offset = offset;
+               bank->sectors[i].size = 512;
+               offset += bank->sectors[i].size;
+               bank->sectors[i].is_erased = -1;
+               bank->sectors[i].is_protected = 0;
+       }
 
        return ERROR_OK;
 }
@@ -95,13 +93,13 @@ static int aduc702x_protect_check(struct flash_bank *bank)
 
 static int aduc702x_erase(struct flash_bank *bank, int first, int last)
 {
-        //int res;
+       /* int res; */
        int x;
        int count;
-       //uint32_t v;
+       /* uint32_t v; */
        struct target *target = bank->target;
 
-        aduc702x_set_write_enable(target, 1);
+       aduc702x_set_write_enable(target, 1);
 
        /* mass erase */
        if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
@@ -110,38 +108,35 @@ static int aduc702x_erase(struct flash_bank *bank, int first, int last)
                target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
                target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
 
-                if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK)
-               {
+               if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
                        LOG_ERROR("mass erase failed");
-                        aduc702x_set_write_enable(target, 0);
+                       aduc702x_set_write_enable(target, 0);
                        return ERROR_FLASH_OPERATION_FAILED;
                }
 
                LOG_DEBUG("mass erase successful.");
                return ERROR_OK;
        } else {
-                unsigned long adr;
+               unsigned long adr;
 
-                count = last - first + 1;
-                for (x = 0; x < count; ++x)
-                {
-                        adr = bank->base + ((first + x) * 512);
+               count = last - first + 1;
+               for (x = 0; x < count; ++x) {
+                       adr = bank->base + ((first + x) * 512);
 
-                        target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
-                        target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
+                       target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
+                       target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
 
-                        if (aduc702x_check_flash_completion(target, 50) != ERROR_OK)
-                        {
-                                LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
-                                aduc702x_set_write_enable(target, 0);
-                                return ERROR_FLASH_SECTOR_NOT_ERASED;
-                        }
+                       if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
+                               LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
+                               aduc702x_set_write_enable(target, 0);
+                               return ERROR_FLASH_SECTOR_NOT_ERASED;
+                       }
 
-                        LOG_DEBUG("erased sector at address 0x%08lX", adr);
-                }
-        }
+                       LOG_DEBUG("erased sector at address 0x%08lX", adr);
+               }
+       }
 
-        aduc702x_set_write_enable(target, 0);
+       aduc702x_set_write_enable(target, 0);
 
        return ERROR_OK;
 }
@@ -157,7 +152,10 @@ static int aduc702x_protect(struct flash_bank *bank, int set, int first, int las
  *
  * Caller should not check for other return values specifically
  */
-static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int aduc702x_write_block(struct flash_bank *bank,
+       uint8_t *buffer,
+       uint32_t offset,
+       uint32_t count)
 {
        struct aduc702x_flash_bank *aduc702x_info = bank->driver_priv;
        struct target *target = bank->target;
@@ -168,71 +166,66 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
        struct arm_algorithm armv4_5_info;
        int retval = ERROR_OK;
 
-       if (((count%2)!=0)||((offset%2)!=0))
-       {
+       if (((count%2) != 0) || ((offset%2) != 0)) {
                LOG_ERROR("write block must be multiple of two bytes in offset & length");
                return ERROR_FAIL;
        }
 
-        /* parameters:
-
-        r0 - address of source data (absolute)
-        r1 - number of halfwords to be copied
-        r2 - start address in flash (offset from beginning of flash memory)
-        r3 - exit code
-        r4 - base address of flash controller (0xFFFFF800)
-
-        registers:
-
-        r5 - scratch
-        r6 - set to 2, used to write flash command
-
-        */
-        static const uint32_t aduc702x_flash_write_code[] = {
-        //<_start>:
-                0xe3a05008,    // mov  r5, #8  ; 0x8
-                0xe5845004,    // str  r5, [r4, #4]
-                0xe3a06002,    // mov  r6, #2  ; 0x2
-        //<next>:
-                0xe1c421b0,    // strh r2, [r4, #16]
-                0xe0d050b2,    // ldrh r5, [r0], #2
-                0xe1c450bc,    // strh r5, [r4, #12]
-                0xe5c46008,    // strb r6, [r4, #8]
-        //<wait_complete>:
-                0xe1d430b0,    // ldrh r3, [r4]
-                0xe3130004,    // tst  r3, #4  ; 0x4
-                0x1afffffc,    // bne  1001c <wait_complete>
-                0xe2822002,    // add  r2, r2, #2      ; 0x2
-                0xe2511001,    // subs r1, r1, #1      ; 0x1
-                0x0a000001,    // beq  1003c <done>
-                0xe3130001,    // tst  r3, #1  ; 0x1
-                0x1afffff3,    // bne  1000c <next>
-        //<done>:
-                0xeafffffe     // b    1003c <done>
+       /* parameters:
+
+       r0 - address of source data (absolute)
+       r1 - number of halfwords to be copied
+       r2 - start address in flash (offset from beginning of flash memory)
+       r3 - exit code
+       r4 - base address of flash controller (0xFFFFF800)
+
+       registers:
+
+       r5 - scratch
+       r6 - set to 2, used to write flash command
+
+       */
+       static const uint32_t aduc702x_flash_write_code[] = {
+               /* <_start>: */
+               0xe3a05008,     /* mov  r5, #8  ; 0x8 */
+               0xe5845004,     /* str  r5, [r4, #4] */
+               0xe3a06002,     /* mov  r6, #2  ; 0x2 */
+               /* <next>: */
+               0xe1c421b0,     /* strh r2, [r4, #16] */
+               0xe0d050b2,     /* ldrh r5, [r0], #2 */
+               0xe1c450bc,     /* strh r5, [r4, #12] */
+               0xe5c46008,     /* strb r6, [r4, #8] */
+               /* <wait_complete>: */
+               0xe1d430b0,     /* ldrh r3, [r4] */
+               0xe3130004,     /* tst  r3, #4  ; 0x4 */
+               0x1afffffc,     /* bne  1001c <wait_complete> */
+               0xe2822002,     /* add  r2, r2, #2      ; 0x2 */
+               0xe2511001,     /* subs r1, r1, #1      ; 0x1 */
+               0x0a000001,     /* beq  1003c <done> */
+               0xe3130001,     /* tst  r3, #1  ; 0x1 */
+               0x1afffff3,     /* bne  1000c <next> */
+               /* <done>: */
+               0xeafffffe      /* b    1003c <done> */
        };
 
        /* flash write code */
        if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
-                &aduc702x_info->write_algorithm) != ERROR_OK)
-       {
+                       &aduc702x_info->write_algorithm) != ERROR_OK) {
                LOG_WARNING("no working area available, can't do block memory writes");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       };
+       }
 
-       retval=target_write_buffer(target, aduc702x_info->write_algorithm->address,
-                sizeof(aduc702x_flash_write_code), (uint8_t*)aduc702x_flash_write_code);
-       if (retval!=ERROR_OK)
-       {
+       retval = target_write_buffer(target, aduc702x_info->write_algorithm->address,
+                       sizeof(aduc702x_flash_write_code), (uint8_t *)aduc702x_flash_write_code);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        /* memory buffer */
-       while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
-       {
+       while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
                buffer_size /= 2;
-               if (buffer_size <= 256)
-               {
-                       /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
+               if (buffer_size <= 256) {
+                       /* if we already allocated the writing code, but failed to get a buffer,
+                        *free the algorithm */
                        if (aduc702x_info->write_algorithm)
                                target_free_working_area(target, aduc702x_info->write_algorithm);
 
@@ -251,32 +244,29 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
        init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
        init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
 
-       while (count > 0)
-       {
+       while (count > 0) {
                uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
 
-               retval=target_write_buffer(target, source->address, thisrun_count, buffer);
-               if (retval!=ERROR_OK)
-               {
+               retval = target_write_buffer(target, source->address, thisrun_count, buffer);
+               if (retval != ERROR_OK)
                        break;
-               }
 
                buf_set_u32(reg_params[0].value, 0, 32, source->address);
                buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
                buf_set_u32(reg_params[2].value, 0, 32, address);
                buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
 
-               if ((retval = target_run_algorithm(target, 0, NULL, 5,
-                        reg_params, aduc702x_info->write_algorithm->address,
-                        aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4,
-                        10000, &armv4_5_info)) != ERROR_OK)
-               {
+               retval = target_run_algorithm(target, 0, NULL, 5,
+                               reg_params, aduc702x_info->write_algorithm->address,
+                               aduc702x_info->write_algorithm->address +
+                               sizeof(aduc702x_flash_write_code) - 4,
+                               10000, &armv4_5_info);
+               if (retval != ERROR_OK) {
                        LOG_ERROR("error executing aduc702x flash write algorithm");
                        break;
                }
 
-               if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1)
-               {
+               if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
                        /* FIX!!!! what does this mean??? replace w/sensible error message */
                        LOG_ERROR("aduc702x detected error writing flash");
                        retval = ERROR_FAIL;
@@ -302,43 +292,44 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
 
 /* All-JTAG, single-access method.  Very slow.  Used only if there is no
  * working area available. */
-static int aduc702x_write_single(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int aduc702x_write_single(struct flash_bank *bank,
+       uint8_t *buffer,
+       uint32_t offset,
+       uint32_t count)
 {
        uint32_t x;
-        uint8_t b;
+       uint8_t b;
        struct target *target = bank->target;
 
-        aduc702x_set_write_enable(target, 1);
+       aduc702x_set_write_enable(target, 1);
 
        for (x = 0; x < count; x += 2) {
-                // FEEADR = address
+               /* FEEADR = address */
                target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
 
-                // set up data
-               if ((x + 1) == count)
-                {
-                        // last byte
-                        target_read_u8(target, offset + x + 1, &b);
-                }
-                else
-                        b = buffer[x + 1];
+               /* set up data */
+               if ((x + 1) == count) {
+                       /* last byte */
+                       target_read_u8(target, offset + x + 1, &b);
+               } else
+                       b = buffer[x + 1];
 
-                target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
+               target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
 
-                // do single-write command
+               /* do single-write command */
                target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
 
-                if (aduc702x_check_flash_completion(target, 1) != ERROR_OK)
-                {
-                       LOG_ERROR("single write failed for address 0x%08lX", (unsigned long)(offset + x));
-                        aduc702x_set_write_enable(target, 0);
+               if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
+                       LOG_ERROR("single write failed for address 0x%08lX",
+                               (unsigned long)(offset + x));
+                       aduc702x_set_write_enable(target, 0);
                        return ERROR_FLASH_OPERATION_FAILED;
                }
 
        }
-        LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
+       LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
 
-        aduc702x_set_write_enable(target, 0);
+       aduc702x_set_write_enable(target, 0);
 
        return ERROR_OK;
 }
@@ -347,24 +338,23 @@ static int aduc702x_write(struct flash_bank *bank, uint8_t *buffer, uint32_t off
 {
        int retval;
 
-        /* try using a block write */
-        if ((retval = aduc702x_write_block(bank, buffer, offset, count)) != ERROR_OK)
-        {
-                if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
-                {
-                        /* if block write failed (no sufficient working area),
-                         * use normal (slow) JTAG method */
-                        LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
-
-                        if ((retval = aduc702x_write_single(bank, buffer, offset, count)) != ERROR_OK)
-                        {
-                                LOG_ERROR("slow write failed");
-                                return ERROR_FLASH_OPERATION_FAILED;
-                        }
-                }
-        }
-
-        return retval;
+       /* try using a block write */
+       retval = aduc702x_write_block(bank, buffer, offset, count);
+       if (retval != ERROR_OK) {
+               if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+                       /* if block write failed (no sufficient working area),
+                        * use normal (slow) JTAG method */
+                       LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+
+                       retval = aduc702x_write_single(bank, buffer, offset, count);
+                       if (retval != ERROR_OK) {
+                               LOG_ERROR("slow write failed");
+                               return ERROR_FLASH_OPERATION_FAILED;
+                       }
+               }
+       }
+
+       return retval;
 }
 
 static int aduc702x_probe(struct flash_bank *bank)
@@ -382,10 +372,10 @@ static int aduc702x_info(struct flash_bank *bank, char *buf, int buf_size)
  * enable = 1 enables writes & erases, 0 disables them */
 static int aduc702x_set_write_enable(struct target *target, int enable)
 {
-        // don't bother to preserve int enable bit here
-        target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
+       /* don't bother to preserve int enable bit here */
+       target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
 
-        return ERROR_OK;
+       return ERROR_OK;
 }
 
 /* wait up to timeout_ms for controller to not be busy,
@@ -393,22 +383,27 @@ static int aduc702x_set_write_enable(struct target *target, int enable)
  *
  * this function sleeps 1ms between checks (after the first one),
  * so in some cases may slow things down without a usleep after the first read */
-static int aduc702x_check_flash_completion(struct targettarget, unsigned int timeout_ms)
+static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms)
 {
-        uint8_t v = 4;
-
-        long long endtime = timeval_ms() + timeout_ms;
-        while (1) {
-                target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
-                if ((v & 4) == 0) break;
-                alive_sleep(1);
-                if (timeval_ms() >= endtime) break;
-        }
-
-        if (v & 2) return ERROR_FAIL;
-        // if a command is ignored, both the success and fail bits may be 0
-        else if ((v & 3) == 0) return ERROR_FAIL;
-        else return ERROR_OK;
+       uint8_t v = 4;
+
+       long long endtime = timeval_ms() + timeout_ms;
+       while (1) {
+               target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
+               if ((v & 4) == 0)
+                       break;
+               alive_sleep(1);
+               if (timeval_ms() >= endtime)
+                       break;
+       }
+
+       if (v & 2)
+               return ERROR_FAIL;
+       /* if a command is ignored, both the success and fail bits may be 0 */
+       else if ((v & 3) == 0)
+               return ERROR_FAIL;
+       else
+               return ERROR_OK;
 }
 
 struct flash_driver aduc702x_flash = {
index 21bfa39..b5074de 100644 (file)
 #include "config.h"
 #endif
 
-
 #include "imp.h"
 #include <helper/time_support.h>
 
 #define REG_NAME_WIDTH  (12)
 
-// at91sam3u series (has one or two flash banks)
+/* at91sam3u series (has one or two flash banks) */
 #define FLASH_BANK0_BASE_U   0x00080000
 #define FLASH_BANK1_BASE_U   0x00100000
 
-// at91sam3s series (has always one flash bank)
+/* at91sam3s series (has always one flash bank) */
 #define FLASH_BANK_BASE_S   0x00400000
 
-// at91sam3n series (has always one flash bank)
+/* at91sam3n series (has always one flash bank) */
 #define FLASH_BANK_BASE_N   0x00400000
 
-#define        AT91C_EFC_FCMD_GETD                 (0x0) // (EFC) Get Flash Descriptor
-#define        AT91C_EFC_FCMD_WP                   (0x1) // (EFC) Write Page
-#define        AT91C_EFC_FCMD_WPL                  (0x2) // (EFC) Write Page and Lock
-#define        AT91C_EFC_FCMD_EWP                  (0x3) // (EFC) Erase Page and Write Page
-#define        AT91C_EFC_FCMD_EWPL                 (0x4) // (EFC) Erase Page and Write Page then Lock
-#define        AT91C_EFC_FCMD_EA                   (0x5) // (EFC) Erase All
-// cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
-// #define     AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane?
-// cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
-// #define     AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages?
-#define        AT91C_EFC_FCMD_SLB                  (0x8) // (EFC) Set Lock Bit
-#define        AT91C_EFC_FCMD_CLB                  (0x9) // (EFC) Clear Lock Bit
-#define        AT91C_EFC_FCMD_GLB                  (0xA) // (EFC) Get Lock Bit
-#define        AT91C_EFC_FCMD_SFB                  (0xB) // (EFC) Set Fuse Bit
-#define        AT91C_EFC_FCMD_CFB                  (0xC) // (EFC) Clear Fuse Bit
-#define        AT91C_EFC_FCMD_GFB                  (0xD) // (EFC) Get Fuse Bit
-#define        AT91C_EFC_FCMD_STUI                 (0xE) // (EFC) Start Read Unique ID
-#define        AT91C_EFC_FCMD_SPUI                 (0xF) // (EFC) Stop Read Unique ID
+#define         AT91C_EFC_FCMD_GETD                 (0x0)      /* (EFC) Get Flash Descriptor */
+#define         AT91C_EFC_FCMD_WP                   (0x1)      /* (EFC) Write Page */
+#define         AT91C_EFC_FCMD_WPL                  (0x2)      /* (EFC) Write Page and Lock */
+#define         AT91C_EFC_FCMD_EWP                  (0x3)      /* (EFC) Erase Page and Write Page */
+#define         AT91C_EFC_FCMD_EWPL                 (0x4)      /* (EFC) Erase Page and Write Page
+                                                                * then Lock */
+#define         AT91C_EFC_FCMD_EA                   (0x5)      /* (EFC) Erase All */
+/* cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
+/* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
+/* cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2 */
+/* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
+#define         AT91C_EFC_FCMD_SLB                  (0x8)      /* (EFC) Set Lock Bit */
+#define         AT91C_EFC_FCMD_CLB                  (0x9)      /* (EFC) Clear Lock Bit */
+#define         AT91C_EFC_FCMD_GLB                  (0xA)      /* (EFC) Get Lock Bit */
+#define         AT91C_EFC_FCMD_SFB                  (0xB)      /* (EFC) Set Fuse Bit */
+#define         AT91C_EFC_FCMD_CFB                  (0xC)      /* (EFC) Clear Fuse Bit */
+#define         AT91C_EFC_FCMD_GFB                  (0xD)      /* (EFC) Get Fuse Bit */
+#define         AT91C_EFC_FCMD_STUI                 (0xE)      /* (EFC) Start Read Unique ID */
+#define         AT91C_EFC_FCMD_SPUI                 (0xF)      /* (EFC) Stop Read Unique ID */
 
 #define  offset_EFC_FMR   0
 #define  offset_EFC_FCR   4
 #define  offset_EFC_FSR   8
 #define  offset_EFC_FRR   12
 
-
 extern struct flash_driver at91sam3_flash;
 
-static float
-_tomhz(uint32_t freq_hz)
+static float _tomhz(uint32_t freq_hz)
 {
        float f;
 
@@ -112,7 +110,7 @@ _tomhz(uint32_t freq_hz)
        return f;
 }
 
-// How the chip is configured.
+/* How the chip is configured. */
 struct sam3_cfg {
        uint32_t unique_id[4];
 
@@ -179,15 +177,15 @@ struct sam3_cfg {
 
 struct sam3_bank_private {
        int probed;
-       // DANGER: THERE ARE DRAGONS HERE..
-       // NOTE: If you add more 'ghost' pointers
-       // be aware that you must *manually* update
-       // these pointers in the function sam3_GetDetails()
-       // See the comment "Here there be dragons"
+       /* DANGER: THERE ARE DRAGONS HERE.. */
+       /* NOTE: If you add more 'ghost' pointers */
+       /* be aware that you must *manually* update */
+       /* these pointers in the function sam3_GetDetails() */
+       /* See the comment "Here there be dragons" */
 
-       // so we can find the chip we belong to
+       /* so we can find the chip we belong to */
        struct sam3_chip *pChip;
-       // so we can find the orginal bank pointer
+       /* so we can find the orginal bank pointer */
        struct flash_bank *pBank;
        unsigned bank_number;
        uint32_t controller_address;
@@ -201,33 +199,32 @@ struct sam3_bank_private {
 };
 
 struct sam3_chip_details {
-       // THERE ARE DRAGONS HERE..
-       // note: If you add pointers here
-       // becareful about them as they
-       // may need to be updated inside
-       // the function: "sam3_GetDetails()
-       // which copy/overwrites the
-       // 'runtime' copy of this structure
+       /* THERE ARE DRAGONS HERE.. */
+       /* note: If you add pointers here */
+       /* becareful about them as they */
+       /* may need to be updated inside */
+       /* the function: "sam3_GetDetails() */
+       /* which copy/overwrites the */
+       /* 'runtime' copy of this structure */
        uint32_t chipid_cidr;
        const char *name;
 
        unsigned n_gpnvms;
 #define SAM3_N_NVM_BITS 3
-       unsigned  gpnvm[SAM3_N_NVM_BITS];
-       unsigned  total_flash_size;
-       unsigned  total_sram_size;
-       unsigned  n_banks;
+       unsigned gpnvm[SAM3_N_NVM_BITS];
+       unsigned total_flash_size;
+       unsigned total_sram_size;
+       unsigned n_banks;
 #define SAM3_MAX_FLASH_BANKS 2
-       // these are "initialized" from the global const data
+       /* these are "initialized" from the global const data */
        struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 };
 
-
 struct sam3_chip {
        struct sam3_chip *next;
-       int    probed;
+       int probed;
 
-       // this is "initialized" from the global const structure
+       /* this is "initialized" from the global const structure */
        struct sam3_chip_details details;
        struct target *target;
        struct sam3_cfg cfg;
@@ -239,11 +236,9 @@ struct sam3_reg_list {
        void (*explain_func)(struct sam3_chip *pInfo);
 };
 
-
 static struct sam3_chip *all_sam3_chips;
 
-static struct sam3_chip *
-get_current_sam3(struct command_context *cmd_ctx)
+static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
 {
        struct target *t;
        static struct sam3_chip *p;
@@ -256,26 +251,24 @@ get_current_sam3(struct command_context *cmd_ctx)
 
        p = all_sam3_chips;
        if (!p) {
-               // this should not happen
-               // the command is not registered until the chip is created?
+               /* this should not happen */
+               /* the command is not registered until the chip is created? */
                command_print(cmd_ctx, "No SAM3 chips exist?");
                return NULL;
        }
 
        while (p) {
-               if (p->target == t) {
+               if (p->target == t)
                        return p;
-               }
                p = p->next;
        }
        command_print(cmd_ctx, "Cannot find SAM3 chip?");
        return NULL;
 }
 
-
-// these are used to *initialize* the "pChip->details" structure.
+/* these are used to *initialize* the "pChip->details" structure. */
 static const struct sam3_chip_details all_sam3_details[] = {
-       // Start at91sam3u* series
+       /* Start at91sam3u* series */
        {
                .chipid_cidr    = 0x28100960,
                .name           = "at91sam3u4e",
@@ -284,53 +277,53 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 2,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 1,
-                       .base_address = FLASH_BANK1_BASE_U,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_U,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
                },
        },
 
@@ -338,40 +331,40 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .chipid_cidr    = 0x281a0760,
                .name           = "at91sam3u2e",
                .total_flash_size     = 128 * 1024,
-               .total_sram_size      =  36 * 1024,
+               .total_sram_size      = 36 * 1024,
                .n_gpnvms       = 2,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//               .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*               .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
        {
@@ -382,39 +375,39 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  64 * 1024,
-                       .nsectors   =  8,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -426,52 +419,52 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 2,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
                {
-                 {
-//             .bank[0] = {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 1,
-                       .base_address = FLASH_BANK1_BASE_U,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
+                       {
+/*             .bank[0] = { */
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 1,
+                               .base_address = FLASH_BANK1_BASE_U,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
                },
        },
 
@@ -483,36 +476,36 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
        {
@@ -523,47 +516,47 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
 
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK0_BASE_U,
-                       .controller_address = 0x400e0800,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  64 * 1024,
-                       .nsectors   =  8,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK0_BASE_U,
+                               .controller_address = 0x400e0800,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
 
-       // Start at91sam3s* series
+       /* Start at91sam3s* series */
 
-       // Note: The preliminary at91sam3s datasheet says on page 302
-       // that the flash controller is at address 0x400E0800.
-       // This is _not_ the case, the controller resides at address 0x400e0a0.
+       /* Note: The preliminary at91sam3s datasheet says on page 302 */
+       /* that the flash controller is at address 0x400E0800. */
+       /* This is _not_ the case, the controller resides at address 0x400e0a0. */
        {
                .chipid_cidr    = 0x28A00960,
                .name           = "at91sam3s4c",
@@ -572,28 +565,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  256 * 1024,
-                       .nsectors   =  32,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 32,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
 
@@ -605,28 +598,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  256 * 1024,
-                       .nsectors   =  32,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 32,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -637,28 +630,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  256 * 1024,
-                       .nsectors   =  32,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 32,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -669,28 +662,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  128 * 1024,
-                       .nsectors   =  16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -701,28 +694,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  128 * 1024,
-                       .nsectors   =  16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -733,28 +726,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  128 * 1024,
-                       .nsectors   =  16,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -765,28 +758,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  64 * 1024,
-                       .nsectors   =  8,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -797,28 +790,28 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  64 * 1024,
-                       .nsectors   =  8,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
        {
@@ -829,32 +822,32 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 2,
                .n_banks        = 1,
                {
-//             .bank[0] = {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_S,
-                       .controller_address = 0x400e0a00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes =  64 * 1024,
-                       .nsectors   =  8,
-                       .sector_size = 8192,
-                       .page_size   = 256,
-                 },
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-
-                 },
+/*             .bank[0] = { */
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_S,
+                               .controller_address = 0x400e0a00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 8192,
+                               .page_size   = 256,
+                       },
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+
+                       },
                },
        },
 
-       // Start at91sam3n* series
+       /* Start at91sam3n* series */
        {
                .chipid_cidr    = 0x29540960,
                .name           = "at91sam3n4c",
@@ -863,44 +856,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 256 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -912,44 +905,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 256 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -961,44 +954,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 256 * 1024,
-                       .nsectors   = 16,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 256 * 1024,
+                               .nsectors   = 16,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1010,44 +1003,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 8,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1059,44 +1052,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 8,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1108,44 +1101,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 128 * 1024,
-                       .nsectors   = 8,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 128 * 1024,
+                               .nsectors   = 8,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1157,44 +1150,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 64 * 1024,
-                       .nsectors   = 4,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 4,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1206,44 +1199,44 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 64 * 1024,
-                       .nsectors   = 4,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 4,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
@@ -1255,51 +1248,51 @@ static const struct sam3_chip_details all_sam3_details[] = {
                .n_gpnvms       = 3,
                .n_banks        = 1,
 
-               // System boots at address 0x0
-               // gpnvm[1] = selects boot code
-               //     if gpnvm[1] == 0
-               //         boot is via "SAMBA" (rom)
-               //     else
-               //         boot is via FLASH
-               //         Selection is via gpnvm[2]
-               //     endif
-               //
-               // NOTE: banks 0 & 1 switch places
-               //     if gpnvm[2] == 0
-               //         Bank0 is the boot rom
-               //      else
-               //         Bank1 is the boot rom
-               //      endif
-//             .bank[0] = {
+               /* System boots at address 0x0 */
+               /* gpnvm[1] = selects boot code */
+               /*     if gpnvm[1] == 0 */
+               /*         boot is via "SAMBA" (rom) */
+               /*     else */
+               /*         boot is via FLASH */
+               /*         Selection is via gpnvm[2] */
+               /*     endif */
+               /*  */
+               /* NOTE: banks 0 & 1 switch places */
+               /*     if gpnvm[2] == 0 */
+               /*         Bank0 is the boot rom */
+               /*      else */
+               /*         Bank1 is the boot rom */
+               /*      endif */
+/*             .bank[0] = { */
                {
-                 {
-                       .probed = 0,
-                       .pChip  = NULL,
-                       .pBank  = NULL,
-                       .bank_number = 0,
-                       .base_address = FLASH_BANK_BASE_N,
-                       .controller_address = 0x400e0A00,
-                       .flash_wait_states = 6, /* workaround silicon bug */
-                       .present = 1,
-                       .size_bytes = 64 * 1024,
-                       .nsectors   = 4,
-                       .sector_size = 16384,
-                       .page_size   = 256,
-                 },
-
-//             .bank[1] = {
-                 {
-                       .present = 0,
-                       .probed = 0,
-                       .bank_number = 1,
-                 },
+                       {
+                               .probed = 0,
+                               .pChip  = NULL,
+                               .pBank  = NULL,
+                               .bank_number = 0,
+                               .base_address = FLASH_BANK_BASE_N,
+                               .controller_address = 0x400e0A00,
+                               .flash_wait_states = 6, /* workaround silicon bug */
+                               .present = 1,
+                               .size_bytes = 64 * 1024,
+                               .nsectors   = 4,
+                               .sector_size = 16384,
+                               .page_size   = 256,
+                       },
+
+/*             .bank[1] = { */
+                       {
+                               .present = 0,
+                               .probed = 0,
+                               .bank_number = 1,
+                       },
                },
        },
 
-       // terminate
+       /* terminate */
        {
-               .chipid_cidr    = 0,
-               .name                   = NULL,
+               .chipid_cidr    = 0,
+               .name                   = NULL,
        }
 };
 
@@ -1318,16 +1311,17 @@ static const struct sam3_chip_details all_sam3_details[] = {
  * @param pPrivate - info about the bank
  * @param v        - result goes here
  */
-static int
-EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
 {
        int r;
-       r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FSR, v);
+       r = target_read_u32(pPrivate->pChip->target,
+                       pPrivate->controller_address + offset_EFC_FSR,
+                       v);
        LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
-                         (unsigned int)(*v),
-                         ((unsigned int)((*v >> 2) & 1)),
-                         ((unsigned int)((*v >> 1) & 1)),
-                         ((unsigned int)((*v >> 0) & 1)));
+               (unsigned int)(*v),
+               ((unsigned int)((*v >> 2) & 1)),
+               ((unsigned int)((*v >> 1) & 1)),
+               ((unsigned int)((*v >> 0) & 1)));
 
        return r;
 }
@@ -1337,95 +1331,93 @@ EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
  * @param pPrivate - info about the bank
  * @param v        - result goes here
  */
-static int
-EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
 {
        int r;
        uint32_t rv;
-       r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address + offset_EFC_FRR, &rv);
-       if (v) {
+       r = target_read_u32(pPrivate->pChip->target,
+                       pPrivate->controller_address + offset_EFC_FRR,
+                       &rv);
+       if (v)
                *v = rv;
-       }
        LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
        return r;
 }
 
-static int
-EFC_StartCommand(struct sam3_bank_private *pPrivate,
-                                unsigned command, unsigned argument)
+static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
+       unsigned command, unsigned argument)
 {
-       uint32_t n,v;
+       uint32_t n, v;
        int r;
        int retry;
 
        retry = 0;
- do_retry:
-
-    // Check command & argument
-    switch (command) {
-
-       case AT91C_EFC_FCMD_WP:
-       case AT91C_EFC_FCMD_WPL:
-       case AT91C_EFC_FCMD_EWP:
-       case AT91C_EFC_FCMD_EWPL:
-               // case AT91C_EFC_FCMD_EPL:
-               // case AT91C_EFC_FCMD_EPA:
-       case AT91C_EFC_FCMD_SLB:
-       case AT91C_EFC_FCMD_CLB:
-               n = (pPrivate->size_bytes / pPrivate->page_size);
-               if (argument >= n) {
-                       LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
-               }
-               break;
+do_retry:
+
+       /* Check command & argument */
+       switch (command) {
+
+               case AT91C_EFC_FCMD_WP:
+               case AT91C_EFC_FCMD_WPL:
+               case AT91C_EFC_FCMD_EWP:
+               case AT91C_EFC_FCMD_EWPL:
+               /* case AT91C_EFC_FCMD_EPL: */
+               /* case AT91C_EFC_FCMD_EPA: */
+               case AT91C_EFC_FCMD_SLB:
+               case AT91C_EFC_FCMD_CLB:
+                       n = (pPrivate->size_bytes / pPrivate->page_size);
+                       if (argument >= n)
+                               LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
+                       break;
 
-       case AT91C_EFC_FCMD_SFB:
-       case AT91C_EFC_FCMD_CFB:
-               if (argument >= pPrivate->pChip->details.n_gpnvms) {
-                       LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
-                                         pPrivate->pChip->details.n_gpnvms);
-               }
-               break;
-
-       case AT91C_EFC_FCMD_GETD:
-       case AT91C_EFC_FCMD_EA:
-       case AT91C_EFC_FCMD_GLB:
-       case AT91C_EFC_FCMD_GFB:
-       case AT91C_EFC_FCMD_STUI:
-       case AT91C_EFC_FCMD_SPUI:
-               if (argument != 0) {
-                       LOG_ERROR("Argument is meaningless for cmd: %d", command);
-               }
-               break;
-       default:
-               LOG_ERROR("Unknown command %d", command);
-               break;
-    }
+               case AT91C_EFC_FCMD_SFB:
+               case AT91C_EFC_FCMD_CFB:
+                       if (argument >= pPrivate->pChip->details.n_gpnvms) {
+                               LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
+                                               pPrivate->pChip->details.n_gpnvms);
+                       }
+                       break;
+
+               case AT91C_EFC_FCMD_GETD:
+               case AT91C_EFC_FCMD_EA:
+               case AT91C_EFC_FCMD_GLB:
+               case AT91C_EFC_FCMD_GFB:
+               case AT91C_EFC_FCMD_STUI:
+               case AT91C_EFC_FCMD_SPUI:
+                       if (argument != 0)
+                               LOG_ERROR("Argument is meaningless for cmd: %d", command);
+                       break;
+               default:
+                       LOG_ERROR("Unknown command %d", command);
+                       break;
+       }
 
        if (command == AT91C_EFC_FCMD_SPUI) {
-               // this is a very special situation.
-               // Situation (1) - error/retry - see below
-               //      And we are being called recursively
-               // Situation (2) - normal, finished reading unique id
+               /* this is a very special situation. */
+               /* Situation (1) - error/retry - see below */
+               /*      And we are being called recursively */
+               /* Situation (2) - normal, finished reading unique id */
        } else {
-               // it should be "ready"
+               /* it should be "ready" */
                EFC_GetStatus(pPrivate, &v);
                if (v & 1) {
-                       // then it is ready
-                       // we go on
+                       /* then it is ready */
+                       /* we go on */
                } else {
                        if (retry) {
-                               // we have done this before
-                               // the controller is not responding.
-                               LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate->bank_number);
+                               /* we have done this before */
+                               /* the controller is not responding. */
+                               LOG_ERROR("flash controller(%d) is not ready! Error",
+                                       pPrivate->bank_number);
                                return ERROR_FAIL;
                        } else {
                                retry++;
                                LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
-                                                 pPrivate->bank_number);
-                               // we do that by issuing the *STOP* command
+                                       pPrivate->bank_number);
+                               /* we do that by issuing the *STOP* command */
                                EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
-                               // above is recursive, and further recursion is blocked by
-                               // if (command == AT91C_EFC_FCMD_SPUI) above
+                               /* above is recursive, and further recursion is blocked by */
+                               /* if (command == AT91C_EFC_FCMD_SPUI) above */
                                goto do_retry;
                        }
                }
@@ -1434,11 +1426,9 @@ EFC_StartCommand(struct sam3_bank_private *pPrivate,
        v = (0x5A << 24) | (argument << 8) | command;
        LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
        r = target_write_u32(pPrivate->pBank->target,
-                                                 pPrivate->controller_address + offset_EFC_FCR,
-                                                 v);
-       if (r != ERROR_OK) {
+                       pPrivate->controller_address + offset_EFC_FCR, v);
+       if (r != ERROR_OK)
                LOG_DEBUG("Error Write failed");
-       }
        return r;
 }
 
@@ -1449,97 +1439,82 @@ EFC_StartCommand(struct sam3_bank_private *pPrivate,
  * @param argument - Optional command argument.
  * @param status   - put command status bits here
  */
-static int
-EFC_PerformCommand(struct sam3_bank_private *pPrivate,
-                                       unsigned command,
-                                       unsigned argument,
-                                       uint32_t *status)
+static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
+       unsigned command,
+       unsigned argument,
+       uint32_t *status)
 {
 
        int r;
        uint32_t v;
        long long ms_now, ms_end;
 
-       // default
-       if (status) {
+       /* default */
+       if (status)
                *status = 0;
-       }
 
        r = EFC_StartCommand(pPrivate, command, argument);
-       if (r != ERROR_OK) {
+       if (r != ERROR_OK)
                return r;
-       }
 
        ms_end = 500 + timeval_ms();
 
-
-    do {
+       do {
                r = EFC_GetStatus(pPrivate, &v);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        return r;
-               }
                ms_now = timeval_ms();
                if (ms_now > ms_end) {
-                       // error
+                       /* error */
                        LOG_ERROR("Command timeout");
                        return ERROR_FAIL;
                }
-    }
-    while ((v & 1) == 0)
-               ;
+       } while ((v & 1) == 0);
 
-       // error bits..
-       if (status) {
+       /* error bits.. */
+       if (status)
                *status = (v & 0x6);
-       }
        return ERROR_OK;
 
 }
 
-
-
-
-
 /**
  * Read the unique ID.
  * @param pPrivate - info about the bank
  * The unique ID is stored in the 'pPrivate' structure.
  */
-static int
-FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
+static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
 {
        int r;
        uint32_t v;
        int x;
-       // assume 0
-    pPrivate->pChip->cfg.unique_id[0] = 0;
-    pPrivate->pChip->cfg.unique_id[1] = 0;
-    pPrivate->pChip->cfg.unique_id[2] = 0;
-    pPrivate->pChip->cfg.unique_id[3] = 0;
+       /* assume 0 */
+       pPrivate->pChip->cfg.unique_id[0] = 0;
+       pPrivate->pChip->cfg.unique_id[1] = 0;
+       pPrivate->pChip->cfg.unique_id[2] = 0;
+       pPrivate->pChip->cfg.unique_id[3] = 0;
 
        LOG_DEBUG("Begin");
        r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
-       if (r < 0) {
+       if (r < 0)
                return r;
-       }
 
-       for (x = 0 ; x < 4 ; x++) {
+       for (x = 0; x < 4; x++) {
                r = target_read_u32(pPrivate->pChip->target,
-                                                        pPrivate->pBank->base + (x * 4),
-                                                        &v);
-               if (r < 0) {
+                               pPrivate->pBank->base + (x * 4),
+                               &v);
+               if (r < 0)
                        return r;
-               }
                pPrivate->pChip->cfg.unique_id[x] = v;
        }
 
-    r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
+       r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
        LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
-                         r,
-                         (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
-                         (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
-                         (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
-                         (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
+               r,
+               (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
+               (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
+               (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
+               (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
        return r;
 
 }
@@ -1548,24 +1523,20 @@ FLASHD_ReadUniqueID (struct sam3_bank_private *pPrivate)
  * Erases the entire flash.
  * @param pPrivate - the info about the bank.
  */
-static int
-FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
+static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
 {
        LOG_DEBUG("Here");
        return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
 }
 
-
-
 /**
  * Gets current GPNVM state.
  * @param pPrivate - info about the bank.
  * @param gpnvm    -  GPNVM bit index.
  * @param puthere  - result stored here.
  */
-//------------------------------------------------------------------------------
-static int
-FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
+/* ------------------------------------------------------------------------------ */
+static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
 {
        uint32_t v;
        int r;
@@ -1578,39 +1549,35 @@ FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *pu
 
        if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
                LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
-                                 gpnvm,pPrivate->pChip->details.n_gpnvms);
+                       gpnvm, pPrivate->pChip->details.n_gpnvms);
                return ERROR_FAIL;
        }
 
-    // Get GPNVMs status
+       /* Get GPNVMs status */
        r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
        if (r != ERROR_OK) {
                LOG_ERROR("Failed");
                return r;
        }
 
-    r = EFC_GetResult(pPrivate, &v);
+       r = EFC_GetResult(pPrivate, &v);
 
        if (puthere) {
-               // Check if GPNVM is set
-               // get the bit and make it a 0/1
+               /* Check if GPNVM is set */
+               /* get the bit and make it a 0/1 */
                *puthere = (v >> gpnvm) & 1;
        }
 
        return r;
 }
 
-
-
-
 /**
  * Clears the selected GPNVM bit.
  * @param pPrivate info about the bank
  * @param gpnvm GPNVM index.
  * @returns 0 if successful; otherwise returns an error code.
  */
-static int
-FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
 {
        int r;
        unsigned v;
@@ -1623,29 +1590,26 @@ FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
 
        if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
                LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
-                                 gpnvm,pPrivate->pChip->details.n_gpnvms);
+                       gpnvm, pPrivate->pChip->details.n_gpnvms);
                return ERROR_FAIL;
        }
 
        r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
        if (r != ERROR_OK) {
-               LOG_DEBUG("Failed: %d",r);
+               LOG_DEBUG("Failed: %d", r);
                return r;
        }
        r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
-       LOG_DEBUG("End: %d",r);
+       LOG_DEBUG("End: %d", r);
        return r;
 }
 
-
-
 /**
  * Sets the selected GPNVM bit.
  * @param pPrivate info about the bank
  * @param gpnvm GPNVM index.
  */
-static int
-FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
+static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
 {
        int r;
        unsigned v;
@@ -1657,44 +1621,39 @@ FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
 
        if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
                LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
-                                 gpnvm,pPrivate->pChip->details.n_gpnvms);
+                       gpnvm, pPrivate->pChip->details.n_gpnvms);
                return ERROR_FAIL;
        }
 
        r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
-       if (r != ERROR_OK) {
+       if (r != ERROR_OK)
                return r;
-       }
        if (v) {
-               // already set
+               /* already set */
                r = ERROR_OK;
        } else {
-               // set it
+               /* set it */
                r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
        }
        return r;
 }
 
-
 /**
  * Returns a bit field (at most 64) of locked regions within a page.
  * @param pPrivate info about the bank
  * @param v where to store locked bits
  */
-static int
-FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
+static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
 {
        int r;
        LOG_DEBUG("Here");
-    r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
-       if (r == ERROR_OK) {
+       r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
+       if (r == ERROR_OK)
                r = EFC_GetResult(pPrivate, v);
-       }
-       LOG_DEBUG("End: %d",r);
+       LOG_DEBUG("End: %d", r);
        return r;
 }
 
-
 /**
  * Unlocks all the regions in the given address range.
  * @param pPrivate info about the bank
@@ -1702,10 +1661,9 @@ FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
  * @param end_sector last (inclusive) to unlock
  */
 
-static int
-FLASHD_Unlock(struct sam3_bank_private *pPrivate,
-                          unsigned start_sector,
-                          unsigned end_sector)
+static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
+       unsigned start_sector,
+       unsigned end_sector)
 {
        int r;
        uint32_t status;
@@ -1714,31 +1672,28 @@ FLASHD_Unlock(struct sam3_bank_private *pPrivate,
 
        pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
 
-    /* Unlock all pages */
-    while (start_sector <= end_sector) {
+       /* Unlock all pages */
+       while (start_sector <= end_sector) {
                pg = start_sector * pages_per_sector;
 
-        r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
-        if (r != ERROR_OK) {
-            return r;
-        }
-        start_sector++;
-    }
+               r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
+               if (r != ERROR_OK)
+                       return r;
+               start_sector++;
+       }
 
-    return ERROR_OK;
+       return ERROR_OK;
 }
 
-
 /**
  * Locks regions
  * @param pPrivate - info about the bank
  * @param start_sector - first sector to lock
  * @param end_sector   - last sector (inclusive) to lock
  */
-static int
-FLASHD_Lock(struct sam3_bank_private *pPrivate,
-                        unsigned start_sector,
-                        unsigned end_sector)
+static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
+       unsigned start_sector,
+       unsigned end_sector)
 {
        uint32_t status;
        uint32_t pg;
@@ -1747,36 +1702,33 @@ FLASHD_Lock(struct sam3_bank_private *pPrivate,
 
        pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
 
-    /* Lock all pages */
-    while (start_sector <= end_sector) {
+       /* Lock all pages */
+       while (start_sector <= end_sector) {
                pg = start_sector * pages_per_sector;
 
-        r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
-        if (r != ERROR_OK) {
-            return r;
-        }
-        start_sector++;
-    }
-    return ERROR_OK;
+               r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
+               if (r != ERROR_OK)
+                       return r;
+               start_sector++;
+       }
+       return ERROR_OK;
 }
 
-
 /****** END SAM3 CODE ********/
 
 /* begin helpful debug code */
-// print the fieldname, the field value, in dec & hex, and return field value
-static uint32_t
-sam3_reg_fieldname(struct sam3_chip *pChip,
-                                       const char *regname,
-                                       uint32_t value,
-                                       unsigned shift,
-                                       unsigned width)
+/* print the fieldname, the field value, in dec & hex, and return field value */
+static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
+       const char *regname,
+       uint32_t value,
+       unsigned shift,
+       unsigned width)
 {
        uint32_t v;
        int hwidth, dwidth;
 
 
-       // extract the field
+       /* extract the field */
        v = value >> shift;
        v = v & ((1 << width)-1);
        if (width <= 16) {
@@ -1787,188 +1739,175 @@ sam3_reg_fieldname(struct sam3_chip *pChip,
                dwidth = 12;
        }
 
-       // show the basics
+       /* show the basics */
        LOG_USER_N("\t%*s: %*d [0x%0*x] ",
-                                 REG_NAME_WIDTH, regname,
-                                 dwidth, v,
-                                 hwidth, v);
+               REG_NAME_WIDTH, regname,
+               dwidth, v,
+               hwidth, v);
        return v;
 }
 
-
 static const char _unknown[] = "unknown";
-static const char * const eproc_names[] = {
-       _unknown,                                       // 0
-       "arm946es",                                     // 1
-       "arm7tdmi",                                     // 2
-       "cortex-m3",                            // 3
-       "arm920t",                                      // 4
-       "arm926ejs",                            // 5
-       _unknown,                                       // 6
-       _unknown,                                       // 7
-       _unknown,                                       // 8
-       _unknown,                                       // 9
-       _unknown,                                       // 10
-       _unknown,                                       // 11
-       _unknown,                                       // 12
-       _unknown,                                       // 13
-       _unknown,                                       // 14
-       _unknown,                                       // 15
+static const char *const eproc_names[] = {
+       _unknown,                                       /* 0 */
+       "arm946es",                                     /* 1 */
+       "arm7tdmi",                                     /* 2 */
+       "cortex-m3",                            /* 3 */
+       "arm920t",                                      /* 4 */
+       "arm926ejs",                            /* 5 */
+       _unknown,                                       /* 6 */
+       _unknown,                                       /* 7 */
+       _unknown,                                       /* 8 */
+       _unknown,                                       /* 9 */
+       _unknown,                                       /* 10 */
+       _unknown,                                       /* 11 */
+       _unknown,                                       /* 12 */
+       _unknown,                                       /* 13 */
+       _unknown,                                       /* 14 */
+       _unknown,                                       /* 15 */
 };
 
-#define nvpsize2 nvpsize               // these two tables are identical
-static const char * const nvpsize[] = {
-       "none",                                         //  0
-       "8K bytes",                                     //  1
-       "16K bytes",                            //  2
-       "32K bytes",                            //  3
-       _unknown,                                       //  4
-       "64K bytes",                            //  5
-       _unknown,                                       //  6
-       "128K bytes",                           //  7
-       _unknown,                                       //  8
-       "256K bytes",                           //  9
-       "512K bytes",                           // 10
-       _unknown,                                       // 11
-       "1024K bytes",                          // 12
-       _unknown,                                       // 13
-       "2048K bytes",                          // 14
-       _unknown,                                       // 15
+#define nvpsize2 nvpsize               /* these two tables are identical */
+static const char *const nvpsize[] = {
+       "none",                                         /*  0 */
+       "8K bytes",                                     /*  1 */
+       "16K bytes",                            /*  2 */
+       "32K bytes",                            /*  3 */
+       _unknown,                                       /*  4 */
+       "64K bytes",                            /*  5 */
+       _unknown,                                       /*  6 */
+       "128K bytes",                           /*  7 */
+       _unknown,                                       /*  8 */
+       "256K bytes",                           /*  9 */
+       "512K bytes",                           /* 10 */
+       _unknown,                                       /* 11 */
+       "1024K bytes",                          /* 12 */
+       _unknown,                                       /* 13 */
+       "2048K bytes",                          /* 14 */
+       _unknown,                                       /* 15 */
 };
 
-
-static const char * const sramsize[] = {
-       "48K Bytes",                            //  0
-       "1K Bytes",                                     //  1
-       "2K Bytes",                                     //  2
-       "6K Bytes",                                     //  3
-       "112K Bytes",                           //  4
-       "4K Bytes",                                     //  5
-       "80K Bytes",                            //  6
-       "160K Bytes",                           //  7
-       "8K Bytes",                                     //  8
-       "16K Bytes",                            //  9
-       "32K Bytes",                            // 10
-       "64K Bytes",                            // 11
-       "128K Bytes",                           // 12
-       "256K Bytes",                           // 13
-       "96K Bytes",                            // 14
-       "512K Bytes",                           // 15
+static const char *const sramsize[] = {
+       "48K Bytes",                            /*  0 */
+       "1K Bytes",                                     /*  1 */
+       "2K Bytes",                                     /*  2 */
+       "6K Bytes",                                     /*  3 */
+       "112K Bytes",                           /*  4 */
+       "4K Bytes",                                     /*  5 */
+       "80K Bytes",                            /*  6 */
+       "160K Bytes",                           /*  7 */
+       "8K Bytes",                                     /*  8 */
+       "16K Bytes",                            /*  9 */
+       "32K Bytes",                            /* 10 */
+       "64K Bytes",                            /* 11 */
+       "128K Bytes",                           /* 12 */
+       "256K Bytes",                           /* 13 */
+       "96K Bytes",                            /* 14 */
+       "512K Bytes",                           /* 15 */
 
 };
 
 static const struct archnames { unsigned value; const char *name; } archnames[] = {
-       { 0x19,  "AT91SAM9xx Series"                                            },
-       { 0x29,  "AT91SAM9XExx Series"                                          },
-       { 0x34,  "AT91x34 Series"                                                       },
-       { 0x37,  "CAP7 Series"                                                          },
-       { 0x39,  "CAP9 Series"                                                          },
-       { 0x3B,  "CAP11 Series"                                                         },
-       { 0x40,  "AT91x40 Series"                                                       },
-       { 0x42,  "AT91x42 Series"                                                       },
-       { 0x55,  "AT91x55 Series"                                                       },
-       { 0x60,  "AT91SAM7Axx Series"                                           },
-       { 0x61,  "AT91SAM7AQxx Series"                                          },
-       { 0x63,  "AT91x63 Series"                                                       },
-       { 0x70,  "AT91SAM7Sxx Series"                                           },
-       { 0x71,  "AT91SAM7XCxx Series"                                          },
-       { 0x72,  "AT91SAM7SExx Series"                                          },
-       { 0x73,  "AT91SAM7Lxx Series"                                           },
-       { 0x75,  "AT91SAM7Xxx Series"                                           },
-       { 0x76,  "AT91SAM7SLxx Series"                                          },
-       { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
-       { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
-       { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
-       { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
-       { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
-       { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
-       { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
-       { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
-       { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
-       { 0x92,  "AT91x92 Series"                                                       },
-       { 0xF0,  "AT75Cxx Series"                                                       },
+       { 0x19,  "AT91SAM9xx Series"                                            },
+       { 0x29,  "AT91SAM9XExx Series"                                          },
+       { 0x34,  "AT91x34 Series"                                                       },
+       { 0x37,  "CAP7 Series"                                                          },
+       { 0x39,  "CAP9 Series"                                                          },
+       { 0x3B,  "CAP11 Series"                                                         },
+       { 0x40,  "AT91x40 Series"                                                       },
+       { 0x42,  "AT91x42 Series"                                                       },
+       { 0x55,  "AT91x55 Series"                                                       },
+       { 0x60,  "AT91SAM7Axx Series"                                           },
+       { 0x61,  "AT91SAM7AQxx Series"                                          },
+       { 0x63,  "AT91x63 Series"                                                       },
+       { 0x70,  "AT91SAM7Sxx Series"                                           },
+       { 0x71,  "AT91SAM7XCxx Series"                                          },
+       { 0x72,  "AT91SAM7SExx Series"                                          },
+       { 0x73,  "AT91SAM7Lxx Series"                                           },
+       { 0x75,  "AT91SAM7Xxx Series"                                           },
+       { 0x76,  "AT91SAM7SLxx Series"                                          },
+       { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
+       { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
+       { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
+       { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
+       { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
+       { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
+       { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
+       { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
+       { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
+       { 0x92,  "AT91x92 Series"                                                       },
+       { 0xF0,  "AT75Cxx Series"                                                       },
        { -1, NULL },
-
 };
 
-static const char * const nvptype[] = {
-       "rom", // 0
-       "romless or onchip flash", // 1
-       "embedded flash memory", // 2
-       "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
-       "sram emulating flash", // 4
-       _unknown, // 5
-       _unknown, // 6
-       _unknown, // 7
-
+static const char *const nvptype[] = {
+       "rom",  /* 0 */
+       "romless or onchip flash",      /* 1 */
+       "embedded flash memory",/* 2 */
+       "rom(nvpsiz) + embedded flash (nvpsiz2)",       /* 3 */
+       "sram emulating flash", /* 4 */
+       _unknown,       /* 5 */
+       _unknown,       /* 6 */
+       _unknown,       /* 7 */
 };
 
 static const char *_yes_or_no(uint32_t v)
 {
-       if (v) {
+       if (v)
                return "YES";
-       } else {
+       else
                return "NO";
-       }
 }
 
-static const char * const _rc_freq[] = {
+static const char *const _rc_freq[] = {
        "4 MHz", "8 MHz", "12 MHz", "reserved"
 };
 
-static void
-sam3_explain_ckgr_mor(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
 {
        uint32_t v;
        uint32_t rcen;
 
        v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
-       LOG_USER("(main xtal enabled: %s)",
-                                 _yes_or_no(v));
+       LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
        v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
-       LOG_USER("(main osc bypass: %s)",
-                                 _yes_or_no(v));
+       LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
        rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
-       LOG_USER("(onchip RC-OSC enabled: %s)",
-                                 _yes_or_no(rcen));
+       LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
        v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
-       LOG_USER("(onchip RC-OSC freq: %s)",
-                                 _rc_freq[v]);
+       LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
 
        pChip->cfg.rc_freq = 0;
        if (rcen) {
                switch (v) {
-               default:
-                       pChip->cfg.rc_freq = 0;
-                       break;
-               case 0:
-                       pChip->cfg.rc_freq = 4 * 1000 * 1000;
-                       break;
-               case 1:
-                       pChip->cfg.rc_freq = 8 * 1000 * 1000;
-                       break;
-               case 2:
-                       pChip->cfg.rc_freq = 12* 1000 * 1000;
-                       break;
+                       default:
+                               pChip->cfg.rc_freq = 0;
+                               break;
+                       case 0:
+                               pChip->cfg.rc_freq = 4 * 1000 * 1000;
+                               break;
+                       case 1:
+                               pChip->cfg.rc_freq = 8 * 1000 * 1000;
+                               break;
+                       case 2:
+                               pChip->cfg.rc_freq = 12 * 1000 * 1000;
+                               break;
                }
        }
 
-       v = sam3_reg_fieldname(pChip,"MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
+       v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
        LOG_USER("(startup clks, time= %f uSecs)",
-                                 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
+               ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
        v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
        LOG_USER("(mainosc source: %s)",
-                                 v ? "external xtal" : "internal RC");
+               v ? "external xtal" : "internal RC");
 
-       v = sam3_reg_fieldname(pChip,"CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
+       v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
        LOG_USER("(clock failure enabled: %s)",
-                                _yes_or_no(v));
+               _yes_or_no(v));
 }
 
-
-
-static void
-sam3_explain_chipid_cidr(struct sam3_chip *pChip)
+static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
 {
        int x;
        uint32_t v;
@@ -1986,12 +1925,12 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
        v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
        LOG_USER("%s", nvpsize2[v]);
 
-       v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16,4);
-       LOG_USER("%s", sramsize[ v ]);
+       v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
+       LOG_USER("%s", sramsize[v]);
 
        v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
        cp = _unknown;
-       for (x = 0 ; archnames[x].name ; x++) {
+       for (x = 0; archnames[x].name; x++) {
                if (v == archnames[x].value) {
                        cp = archnames[x].name;
                        break;
@@ -2001,18 +1940,16 @@ sam3_explain_chipid_cidr(struct sam3_chip *pChip)
        LOG_USER("%s", cp);
 
        v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
-       LOG_USER("%s", nvptype[ v ]);
+       LOG_USER("%s", nvptype[v]);
 
        v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
        LOG_USER("(exists: %s)", _yes_or_no(v));
 }
 
-static void
-sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
 {
        uint32_t v;
 
-
        v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
        LOG_USER("(main ready: %s)", _yes_or_no(v));
 
@@ -2022,36 +1959,32 @@ sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
        pChip->cfg.mainosc_freq = v;
 
        LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
-                                _tomhz(v),
-                                pChip->cfg.slow_freq / 1000,
-                                pChip->cfg.slow_freq % 1000);
-
+               _tomhz(v),
+               pChip->cfg.slow_freq / 1000,
+               pChip->cfg.slow_freq % 1000);
 }
 
-static void
-sam3_explain_ckgr_plla(struct sam3_chip *pChip)
+static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
 {
-       uint32_t mula,diva;
+       uint32_t mula, diva;
 
        diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
        LOG_USER_N("\n");
        mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
        LOG_USER_N("\n");
        pChip->cfg.plla_freq = 0;
-       if (mula == 0) {
+       if (mula == 0)
                LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
-       } else if (diva == 0) {
+       else if (diva == 0)
                LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
-       else if (diva == 1) {
+       else if (diva == 1) {
                pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1));
                LOG_USER("\tPLLA Freq: %3.03f MHz",
-                                        _tomhz(pChip->cfg.plla_freq));
+                       _tomhz(pChip->cfg.plla_freq));
        }
 }
 
-
-static void
-sam3_explain_mckr(struct sam3_chip *pChip)
+static void sam3_explain_mckr(struct sam3_chip *pChip)
 {
        uint32_t css, pres, fin = 0;
        int pdiv = 0;
@@ -2059,150 +1992,144 @@ sam3_explain_mckr(struct sam3_chip *pChip)
 
        css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
        switch (css & 3) {
-       case 0:
-               fin = pChip->cfg.slow_freq;
-               cp = "slowclk";
-               break;
-       case 1:
-               fin = pChip->cfg.mainosc_freq;
-               cp  = "mainosc";
-               break;
-       case 2:
-               fin = pChip->cfg.plla_freq;
-               cp  = "plla";
-               break;
-       case 3:
-               if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
-                       fin = 480 * 1000 * 1000;
-                       cp = "upll";
-               } else {
-                       fin = 0;
-                       cp  = "upll (*ERROR* UPLL is disabled)";
-               }
-               break;
-       default:
-               assert(0);
-               break;
+               case 0:
+                       fin = pChip->cfg.slow_freq;
+                       cp = "slowclk";
+                       break;
+               case 1:
+                       fin = pChip->cfg.mainosc_freq;
+                       cp  = "mainosc";
+                       break;
+               case 2:
+                       fin = pChip->cfg.plla_freq;
+                       cp  = "plla";
+                       break;
+               case 3:
+                       if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
+                               fin = 480 * 1000 * 1000;
+                               cp = "upll";
+                       } else {
+                               fin = 0;
+                               cp  = "upll (*ERROR* UPLL is disabled)";
+                       }
+                       break;
+               default:
+                       assert(0);
+                       break;
        }
 
        LOG_USER("%s (%3.03f Mhz)",
-                                 cp,
-                                 _tomhz(fin));
+               cp,
+               _tomhz(fin));
        pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
        switch (pres & 0x07) {
-       case 0:
-               pdiv = 1;
-               cp = "selected clock";
-               break;
-       case 1:
-               pdiv = 2;
-               cp = "clock/2";
-               break;
-       case 2:
-               pdiv = 4;
-               cp = "clock/4";
-               break;
-       case 3:
-               pdiv = 8;
-               cp = "clock/8";
-               break;
-       case 4:
-               pdiv = 16;
-               cp = "clock/16";
-               break;
-       case 5:
-               pdiv = 32;
-               cp = "clock/32";
-               break;
-       case 6:
-               pdiv = 64;
-               cp = "clock/64";
-               break;
-       case 7:
-               pdiv = 6;
-               cp = "clock/6";
-               break;
-       default:
-               assert(0);
-               break;
+               case 0:
+                       pdiv = 1;
+                       cp = "selected clock";
+                       break;
+               case 1:
+                       pdiv = 2;
+                       cp = "clock/2";
+                       break;
+               case 2:
+                       pdiv = 4;
+                       cp = "clock/4";
+                       break;
+               case 3:
+                       pdiv = 8;
+                       cp = "clock/8";
+                       break;
+               case 4:
+                       pdiv = 16;
+                       cp = "clock/16";
+                       break;
+               case 5:
+                       pdiv = 32;
+                       cp = "clock/32";
+                       break;
+               case 6:
+                       pdiv = 64;
+                       cp = "clock/64";
+                       break;
+               case 7:
+                       pdiv = 6;
+                       cp = "clock/6";
+                       break;
+               default:
+                       assert(0);
+                       break;
        }
        LOG_USER("(%s)", cp);
        fin = fin / pdiv;
-       // sam3 has a *SINGLE* clock -
-       // other at91 series parts have divisors for these.
+       /* sam3 has a *SINGLE* clock - */
+       /* other at91 series parts have divisors for these. */
        pChip->cfg.cpu_freq = fin;
        pChip->cfg.mclk_freq = fin;
        pChip->cfg.fclk_freq = fin;
        LOG_USER("\t\tResult CPU Freq: %3.03f",
-                                 _tomhz(fin));
+               _tomhz(fin));
 }
 
 #if 0
-static struct sam3_chip *
-target2sam3(struct target *pTarget)
+static struct sam3_chip *target2sam3(struct target *pTarget)
 {
        struct sam3_chip *pChip;
 
-       if (pTarget == NULL) {
+       if (pTarget == NULL)
                return NULL;
-       }
 
        pChip = all_sam3_chips;
        while (pChip) {
-               if (pChip->target == pTarget) {
-                       break; // return below
-               } else {
+               if (pChip->target == pTarget)
+                       break;  /* return below */
+               else
                        pChip = pChip->next;
-               }
        }
        return pChip;
 }
 #endif
 
-static uint32_t *
-sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
+static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
 {
-       // this function exists to help
-       // keep funky offsetof() errors
-       // and casting from causing bugs
+       /* this function exists to help */
+       /* keep funky offsetof() errors */
+       /* and casting from causing bugs */
 
-       // By using prototypes - we can detect what would
-       // be casting errors.
+       /* By using prototypes - we can detect what would */
+       /* be casting errors. */
 
-       return ((uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset));
+       return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
 }
 
 
-#define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
+#define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
+                                                 struct sam3_cfg, \
+                                                 NAME), # NAME, FUNC }
 static const struct sam3_reg_list sam3_all_regs[] = {
-       SAM3_ENTRY(CKGR_MOR , sam3_explain_ckgr_mor),
-       SAM3_ENTRY(CKGR_MCFR , sam3_explain_ckgr_mcfr),
-       SAM3_ENTRY(CKGR_PLLAR , sam3_explain_ckgr_plla),
-       SAM3_ENTRY(CKGR_UCKR , NULL),
-       SAM3_ENTRY(PMC_FSMR , NULL),
-       SAM3_ENTRY(PMC_FSPR , NULL),
-       SAM3_ENTRY(PMC_IMR , NULL),
-       SAM3_ENTRY(PMC_MCKR , sam3_explain_mckr),
-       SAM3_ENTRY(PMC_PCK0 , NULL),
-       SAM3_ENTRY(PMC_PCK1 , NULL),
-       SAM3_ENTRY(PMC_PCK2 , NULL),
-       SAM3_ENTRY(PMC_PCSR , NULL),
-       SAM3_ENTRY(PMC_SCSR , NULL),
-       SAM3_ENTRY(PMC_SR , NULL),
-       SAM3_ENTRY(CHIPID_CIDR , sam3_explain_chipid_cidr),
-       SAM3_ENTRY(CHIPID_EXID , NULL),
+       SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
+       SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
+       SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
+       SAM3_ENTRY(CKGR_UCKR, NULL),
+       SAM3_ENTRY(PMC_FSMR, NULL),
+       SAM3_ENTRY(PMC_FSPR, NULL),
+       SAM3_ENTRY(PMC_IMR, NULL),
+       SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
+       SAM3_ENTRY(PMC_PCK0, NULL),
+       SAM3_ENTRY(PMC_PCK1, NULL),
+       SAM3_ENTRY(PMC_PCK2, NULL),
+       SAM3_ENTRY(PMC_PCSR, NULL),
+       SAM3_ENTRY(PMC_SCSR, NULL),
+       SAM3_ENTRY(PMC_SR, NULL),
+       SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
+       SAM3_ENTRY(CHIPID_EXID, NULL),
        SAM3_ENTRY(SUPC_CR, NULL),
 
-       // TERMINATE THE LIST
+       /* TERMINATE THE LIST */
        { .name = NULL }
 };
 #undef SAM3_ENTRY
 
-
-
-
-static struct sam3_bank_private *
-get_sam3_bank_private(struct flash_bank *bank)
+static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
 {
        return (struct sam3_bank_private *)(bank->driver_priv);
 }
@@ -2211,8 +2138,7 @@ get_sam3_bank_private(struct flash_bank *bank)
  * Given a pointer to where it goes in the structure,
  * determine the register name, address from the all registers table.
  */
-static const struct sam3_reg_list *
-sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
 {
        const struct sam3_reg_list *pReg;
 
@@ -2220,49 +2146,43 @@ sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
        while (pReg->name) {
                uint32_t *pPossible;
 
-               // calculate where this one go..
-               // it is "possibly" this register.
+               /* calculate where this one go.. */
+               /* it is "possibly" this register. */
 
                pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
 
-               // well? Is it this register
+               /* well? Is it this register */
                if (pPossible == goes_here) {
-                       // Jump for joy!
+                       /* Jump for joy! */
                        return pReg;
                }
 
-               // next...
+               /* next... */
                pReg++;
        }
-       // This is *TOTAL*PANIC* - we are totally screwed.
+       /* This is *TOTAL*PANIC* - we are totally screwed. */
        LOG_ERROR("INVALID SAM3 REGISTER");
        return NULL;
 }
 
-
-static int
-sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
+static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
 {
        const struct sam3_reg_list *pReg;
        int r;
 
        pReg = sam3_GetReg(pChip, goes_here);
-       if (!pReg) {
+       if (!pReg)
                return ERROR_FAIL;
-       }
 
        r = target_read_u32(pChip->target, pReg->address, goes_here);
        if (r != ERROR_OK) {
                LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
-                                 pReg->name, (unsigned)(pReg->address), r);
+                       pReg->name, (unsigned)(pReg->address), r);
        }
        return r;
 }
 
-
-
-static int
-sam3_ReadAllRegs(struct sam3_chip *pChip)
+static int sam3_ReadAllRegs(struct sam3_chip *pChip)
 {
        int r;
        const struct sam3_reg_list *pReg;
@@ -2270,10 +2190,10 @@ sam3_ReadAllRegs(struct sam3_chip *pChip)
        pReg = &(sam3_all_regs[0]);
        while (pReg->name) {
                r = sam3_ReadThisReg(pChip,
-                                                                 sam3_get_reg_ptr(&(pChip->cfg), pReg));
+                               sam3_get_reg_ptr(&(pChip->cfg), pReg));
                if (r != ERROR_OK) {
                        LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
-                                         pReg->name, ((unsigned)(pReg->address)), r);
+                               pReg->name, ((unsigned)(pReg->address)), r);
                        return r;
                }
 
@@ -2283,26 +2203,23 @@ sam3_ReadAllRegs(struct sam3_chip *pChip)
        return ERROR_OK;
 }
 
-
-static int
-sam3_GetInfo(struct sam3_chip *pChip)
+static int sam3_GetInfo(struct sam3_chip *pChip)
 {
        const struct sam3_reg_list *pReg;
        uint32_t regval;
 
        pReg = &(sam3_all_regs[0]);
        while (pReg->name) {
-               // display all regs
+               /* display all regs */
                LOG_DEBUG("Start: %s", pReg->name);
                regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
                LOG_USER("%*s: [0x%08x] -> 0x%08x",
-                                        REG_NAME_WIDTH,
-                                        pReg->name,
-                                        pReg->address,
-                                        regval);
-               if (pReg->explain_func) {
+                       REG_NAME_WIDTH,
+                       pReg->name,
+                       pReg->address,
+                       regval);
+               if (pReg->explain_func)
                        (*(pReg->explain_func))(pChip);
-               }
                LOG_DEBUG("End: %s", pReg->name);
                pReg++;
        }
@@ -2312,20 +2229,16 @@ sam3_GetInfo(struct sam3_chip *pChip)
        LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
        LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
 
-
        LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
-                                 pChip->cfg.unique_id[0],
-                                 pChip->cfg.unique_id[1],
-                                 pChip->cfg.unique_id[2],
-                                 pChip->cfg.unique_id[3]);
-
+               pChip->cfg.unique_id[0],
+               pChip->cfg.unique_id[1],
+               pChip->cfg.unique_id[2],
+               pChip->cfg.unique_id[3]);
 
        return ERROR_OK;
 }
 
-
-static int
-sam3_erase_check(struct flash_bank *bank)
+static int sam3_erase_check(struct flash_bank *bank)
 {
        int x;
 
@@ -2340,19 +2253,17 @@ sam3_erase_check(struct flash_bank *bank)
        }
 
        LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
-       for (x = 0 ; x < bank->num_sectors ; x++) {
+       for (x = 0; x < bank->num_sectors; x++)
                bank->sectors[x].is_erased = 1;
-       }
 
        LOG_DEBUG("Done");
        return ERROR_OK;
 }
 
-static int
-sam3_protect_check(struct flash_bank *bank)
+static int sam3_protect_check(struct flash_bank *bank)
 {
        int r;
-       uint32_t v=0;
+       uint32_t v = 0;
        unsigned x;
        struct sam3_bank_private *pPrivate;
 
@@ -2367,19 +2278,17 @@ sam3_protect_check(struct flash_bank *bank)
                LOG_ERROR("no private for this bank?");
                return ERROR_FAIL;
        }
-       if (!(pPrivate->probed)) {
+       if (!(pPrivate->probed))
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       r = FLASHD_GetLockBits(pPrivate , &v);
+       r = FLASHD_GetLockBits(pPrivate, &v);
        if (r != ERROR_OK) {
-               LOG_DEBUG("Failed: %d",r);
+               LOG_DEBUG("Failed: %d", r);
                return r;
        }
 
-       for (x = 0 ; x < pPrivate->nsectors ; x++) {
+       for (x = 0; x < pPrivate->nsectors; x++)
                bank->sectors[x].is_protected = (!!(v & (1 << x)));
-       }
        LOG_DEBUG("Done");
        return ERROR_OK;
 }
@@ -2390,73 +2299,71 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
 
        pChip = all_sam3_chips;
 
-       // is this an existing chip?
+       /* is this an existing chip? */
        while (pChip) {
-               if (pChip->target == bank->target) {
+               if (pChip->target == bank->target)
                        break;
-               }
                pChip = pChip->next;
        }
 
        if (!pChip) {
-               // this is a *NEW* chip
+               /* this is a *NEW* chip */
                pChip = calloc(1, sizeof(struct sam3_chip));
                if (!pChip) {
                        LOG_ERROR("NO RAM!");
                        return ERROR_FAIL;
                }
                pChip->target = bank->target;
-               // insert at head
+               /* insert at head */
                pChip->next = all_sam3_chips;
                all_sam3_chips = pChip;
                pChip->target = bank->target;
-               // assumption is this runs at 32khz
+               /* assumption is this runs at 32khz */
                pChip->cfg.slow_freq = 32768;
                pChip->probed = 0;
        }
 
        switch (bank->base) {
-       default:
-               LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
-                       [at91sam3u series] or 0x%08x [at91sam3s series] or \
-                       0x%08x [at91sam3n series])",
-                                 ((unsigned int)(bank->base)),
-                                 ((unsigned int)(FLASH_BANK0_BASE_U)),
-                                 ((unsigned int)(FLASH_BANK1_BASE_U)),
-                                 ((unsigned int)(FLASH_BANK_BASE_S)),
-                                 ((unsigned int)(FLASH_BANK_BASE_N)));
-               return ERROR_FAIL;
-               break;
-
-       // at91sam3u series
-       case FLASH_BANK0_BASE_U:
-               bank->driver_priv = &(pChip->details.bank[0]);
-               bank->bank_number = 0;
-               pChip->details.bank[0].pChip = pChip;
-               pChip->details.bank[0].pBank = bank;
-               break;
-       case FLASH_BANK1_BASE_U:
-               bank->driver_priv = &(pChip->details.bank[1]);
-               bank->bank_number = 1;
-               pChip->details.bank[1].pChip = pChip;
-               pChip->details.bank[1].pBank = bank;
-               break;
-
-       /* at91sam3s and at91sam3n series */
-       case FLASH_BANK_BASE_S:
-               bank->driver_priv = &(pChip->details.bank[0]);
-               bank->bank_number = 0;
-               pChip->details.bank[0].pChip = pChip;
-               pChip->details.bank[0].pBank = bank;
-               break;
-       }
-
-       // we initialize after probing.
+               default:
+                       LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
+                       "[at91sam3u series] or 0x%08x [at91sam3s series] or "
+                       "0x%08x [at91sam3n series])",
+                       ((unsigned int)(bank->base)),
+                       ((unsigned int)(FLASH_BANK0_BASE_U)),
+                       ((unsigned int)(FLASH_BANK1_BASE_U)),
+                       ((unsigned int)(FLASH_BANK_BASE_S)),
+                       ((unsigned int)(FLASH_BANK_BASE_N)));
+                       return ERROR_FAIL;
+                       break;
+
+               /* at91sam3u series */
+               case FLASH_BANK0_BASE_U:
+                       bank->driver_priv = &(pChip->details.bank[0]);
+                       bank->bank_number = 0;
+                       pChip->details.bank[0].pChip = pChip;
+                       pChip->details.bank[0].pBank = bank;
+                       break;
+               case FLASH_BANK1_BASE_U:
+                       bank->driver_priv = &(pChip->details.bank[1]);
+                       bank->bank_number = 1;
+                       pChip->details.bank[1].pChip = pChip;
+                       pChip->details.bank[1].pBank = bank;
+                       break;
+
+               /* at91sam3s and at91sam3n series */
+               case FLASH_BANK_BASE_S:
+                       bank->driver_priv = &(pChip->details.bank[0]);
+                       bank->bank_number = 0;
+                       pChip->details.bank[0].pChip = pChip;
+                       pChip->details.bank[0].pBank = bank;
+                       break;
+       }
+
+       /* we initialize after probing. */
        return ERROR_OK;
 }
 
-static int
-sam3_GetDetails(struct sam3_bank_private *pPrivate)
+static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
 {
        const struct sam3_chip_details *pDetails;
        struct sam3_chip *pChip;
@@ -2466,61 +2373,56 @@ sam3_GetDetails(struct sam3_bank_private *pPrivate)
        LOG_DEBUG("Begin");
        pDetails = all_sam3_details;
        while (pDetails->name) {
-               // Compare cidr without version bits
-               if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0)) {
+               /* Compare cidr without version bits */
+               if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
                        break;
-               } else {
+               else
                        pDetails++;
-               }
        }
        if (pDetails->name == NULL) {
                LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
-                                 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
-               // Help the victim, print details about the chip
+                       (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
+               /* Help the victim, print details about the chip */
                LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
-                                               pPrivate->pChip->cfg.CHIPID_CIDR);
+                       pPrivate->pChip->cfg.CHIPID_CIDR);
                sam3_explain_chipid_cidr(pPrivate->pChip);
                return ERROR_FAIL;
        }
 
-       // DANGER: THERE ARE DRAGONS HERE
+       /* DANGER: THERE ARE DRAGONS HERE */
 
-       // get our pChip - it is going
-       // to be over-written shortly
+       /* get our pChip - it is going */
+       /* to be over-written shortly */
        pChip = pPrivate->pChip;
 
-       // Note that, in reality:
-       //
-       //     pPrivate = &(pChip->details.bank[0])
-       // or  pPrivate = &(pChip->details.bank[1])
-       //
+       /* Note that, in reality: */
+       /*  */
+       /*     pPrivate = &(pChip->details.bank[0]) */
+       /* or  pPrivate = &(pChip->details.bank[1]) */
+       /*  */
 
-       // save the "bank" pointers
-       for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
-               saved_banks[ x ] = pChip->details.bank[x].pBank;
-       }
+       /* save the "bank" pointers */
+       for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
+               saved_banks[x] = pChip->details.bank[x].pBank;
 
-       // Overwrite the "details" structure.
+       /* Overwrite the "details" structure. */
        memcpy(&(pPrivate->pChip->details),
-                       pDetails,
-                       sizeof(pPrivate->pChip->details));
+               pDetails,
+               sizeof(pPrivate->pChip->details));
 
-       // now fix the ghosted pointers
-       for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
+       /* now fix the ghosted pointers */
+       for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
                pChip->details.bank[x].pChip = pChip;
                pChip->details.bank[x].pBank = saved_banks[x];
        }
 
-       // update the *BANK*SIZE*
+       /* update the *BANK*SIZE* */
 
        LOG_DEBUG("End");
        return ERROR_OK;
 }
 
-
-
-static int
-_sam3_probe(struct flash_bank *bank, int noise)
+static int _sam3_probe(struct flash_bank *bank, int noise)
 {
        unsigned x;
        int r;
@@ -2528,8 +2430,7 @@ _sam3_probe(struct flash_bank *bank, int noise)
 
 
        LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -2541,42 +2442,38 @@ _sam3_probe(struct flash_bank *bank, int noise)
        }
 
        r = sam3_ReadAllRegs(pPrivate->pChip);
-       if (r != ERROR_OK) {
+       if (r != ERROR_OK)
                return r;
-       }
-
 
        LOG_DEBUG("Here");
-       if (pPrivate->pChip->probed) {
+       if (pPrivate->pChip->probed)
                r = sam3_GetInfo(pPrivate->pChip);
-       } else {
+       else
                r = sam3_GetDetails(pPrivate);
-       }
-       if (r != ERROR_OK) {
+       if (r != ERROR_OK)
                return r;
-       }
 
-       // update the flash bank size
-       for (x = 0 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
+       /* update the flash bank size */
+       for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
                if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
-                       bank->size =  pPrivate->pChip->details.bank[x].size_bytes;
+                       bank->size = pPrivate->pChip->details.bank[x].size_bytes;
                        break;
                }
        }
 
        if (bank->sectors == NULL) {
-               bank->sectors     = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
+               bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
                if (bank->sectors == NULL) {
                        LOG_ERROR("No memory!");
                        return ERROR_FAIL;
                }
                bank->num_sectors = pPrivate->nsectors;
 
-               for (x = 0 ; ((int)(x)) < bank->num_sectors ; x++) {
-                       bank->sectors[x].size         = pPrivate->sector_size;
-                       bank->sectors[x].offset       = x * (pPrivate->sector_size);
-                       // mark as unknown
-                       bank->sectors[x].is_erased    = -1;
+               for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
+                       bank->sectors[x].size = pPrivate->sector_size;
+                       bank->sectors[x].offset = x * (pPrivate->sector_size);
+                       /* mark as unknown */
+                       bank->sectors[x].is_erased = -1;
                        bank->sectors[x].is_protected = -1;
                }
        }
@@ -2584,37 +2481,31 @@ _sam3_probe(struct flash_bank *bank, int noise)
        pPrivate->probed = 1;
 
        r = sam3_protect_check(bank);
-       if (r != ERROR_OK) {
+       if (r != ERROR_OK)
                return r;
-       }
 
        LOG_DEBUG("Bank = %d, nbanks = %d",
-                         pPrivate->bank_number , pPrivate->pChip->details.n_banks);
+               pPrivate->bank_number, pPrivate->pChip->details.n_banks);
        if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
-               // read unique id,
-               // it appears to be associated with the *last* flash bank.
+               /* read unique id, */
+               /* it appears to be associated with the *last* flash bank. */
                FLASHD_ReadUniqueID(pPrivate);
        }
 
        return r;
 }
 
-static int
-sam3_probe(struct flash_bank *bank)
+static int sam3_probe(struct flash_bank *bank)
 {
        return _sam3_probe(bank, 1);
 }
 
-static int
-sam3_auto_probe(struct flash_bank *bank)
+static int sam3_auto_probe(struct flash_bank *bank)
 {
        return _sam3_probe(bank, 0);
 }
 
-
-
-static int
-sam3_erase(struct flash_bank *bank, int first, int last)
+static int sam3_erase(struct flash_bank *bank, int first, int last)
 {
        struct sam3_bank_private *pPrivate;
        int r;
@@ -2627,17 +2518,16 @@ sam3_erase(struct flash_bank *bank, int first, int last)
 
        r = sam3_auto_probe(bank);
        if (r != ERROR_OK) {
-               LOG_DEBUG("Here,r=%d",r);
+               LOG_DEBUG("Here,r=%d", r);
                return r;
        }
 
        pPrivate = get_sam3_bank_private(bank);
-       if (!(pPrivate->probed)) {
+       if (!(pPrivate->probed))
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       if ((first == 0) && ((last + 1)== ((int)(pPrivate->nsectors)))) {
-               // whole chip
+       if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
+               /* whole chip */
                LOG_DEBUG("Here");
                return FLASHD_EraseEntireBank(pPrivate);
        }
@@ -2645,8 +2535,7 @@ sam3_erase(struct flash_bank *bank, int first, int last)
        return ERROR_OK;
 }
 
-static int
-sam3_protect(struct flash_bank *bank, int set, int first, int last)
+static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
 {
        struct sam3_bank_private *pPrivate;
        int r;
@@ -2658,35 +2547,30 @@ sam3_protect(struct flash_bank *bank, int set, int first, int last)
        }
 
        pPrivate = get_sam3_bank_private(bank);
-       if (!(pPrivate->probed)) {
+       if (!(pPrivate->probed))
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       if (set) {
+       if (set)
                r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
-       } else {
+       else
                r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
-       }
-       LOG_DEBUG("End: r=%d",r);
+       LOG_DEBUG("End: r=%d", r);
 
        return r;
 
 }
 
-
-static int
-sam3_info(struct flash_bank *bank, char *buf, int buf_size)
+static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
 {
        if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
-       buf[ 0 ] = 0;
+       buf[0] = 0;
        return ERROR_OK;
 }
 
-static int
-sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
 {
        uint32_t adr;
        int r;
@@ -2695,112 +2579,108 @@ sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *bu
        adr += adr + pPrivate->base_address;
 
        r = target_read_memory(pPrivate->pChip->target,
-                                                       adr,
-                                                       4, /* THIS*MUST*BE* in 32bit values */
-                                                       pPrivate->page_size / 4,
-                                                       buf);
-       if (r != ERROR_OK) {
-               LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr));
-       }
+                       adr,
+                       4,                                      /* THIS*MUST*BE* in 32bit values */
+                       pPrivate->page_size / 4,
+                       buf);
+       if (r != ERROR_OK)
+               LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
+                       (unsigned int)(adr));
        return r;
 }
 
-// The code below is basically this:
-// compiled with
-// arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
-//
-// Only the *CPU* can write to the flash buffer.
-// the DAP cannot... so - we download this 28byte thing
-// Run the algorithm - (below)
-// to program the device
-//
-// ========================================
-// #include <stdint.h>
-//
-// struct foo {
-//   uint32_t *dst;
-//   const uint32_t *src;
-//   int   n;
-//   volatile uint32_t *base;
-//   uint32_t   cmd;
-// };
-//
-//
-// uint32_t sam3_function(struct foo *p)
-// {
-//   volatile uint32_t *v;
-//   uint32_t *d;
-//   const uint32_t *s;
-//   int   n;
-//   uint32_t r;
-//
-//   d = p->dst;
-//   s = p->src;
-//   n = p->n;
-//
-//   do {
-//     *d++ = *s++;
-//   } while (--n)
-//     ;
-//
-//   v = p->base;
-//
-//   v[ 1 ] = p->cmd;
-//   do {
-//     r = v[8/4];
-//   } while (!(r&1))
-//     ;
-//   return r;
-// }
-// ========================================
-
-
+/* The code below is basically this: */
+/* compiled with */
+/* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
+/*  */
+/* Only the *CPU* can write to the flash buffer. */
+/* the DAP cannot... so - we download this 28byte thing */
+/* Run the algorithm - (below) */
+/* to program the device */
+/*  */
+/* ======================================== */
+/* #include <stdint.h> */
+/*  */
+/* struct foo { */
+/*   uint32_t *dst; */
+/*   const uint32_t *src; */
+/*   int   n; */
+/*   volatile uint32_t *base; */
+/*   uint32_t   cmd; */
+/* }; */
+/*  */
+/*  */
+/* uint32_t sam3_function(struct foo *p) */
+/* { */
+/*   volatile uint32_t *v; */
+/*   uint32_t *d; */
+/*   const uint32_t *s; */
+/*   int   n; */
+/*   uint32_t r; */
+/*  */
+/*   d = p->dst; */
+/*   s = p->src; */
+/*   n = p->n; */
+/*  */
+/*   do { */
+/*     *d++ = *s++; */
+/*   } while (--n) */
+/*     ; */
+/*  */
+/*   v = p->base; */
+/*  */
+/*   v[ 1 ] = p->cmd; */
+/*   do { */
+/*     r = v[8/4]; */
+/*   } while (!(r&1)) */
+/*     ; */
+/*   return r; */
+/* } */
+/* ======================================== */
 
 static const uint8_t
-sam3_page_write_opcodes[] = {
-       //  24 0000 0446                mov     r4, r0
-       0x04,0x46,
-       //  25 0002 6168                ldr     r1, [r4, #4]
-       0x61,0x68,
-       //  26 0004 0068                ldr     r0, [r0, #0]
-       0x00,0x68,
-       //  27 0006 A268                ldr     r2, [r4, #8]
-       0xa2,0x68,
-       //  28                          @ lr needed for prologue
-       //  29                  .L2:
-       //  30 0008 51F8043B            ldr     r3, [r1], #4
-       0x51,0xf8,0x04,0x3b,
-       //  31 000c 12F1FF32            adds    r2, r2, #-1
-       0x12,0xf1,0xff,0x32,
-       //  32 0010 40F8043B            str     r3, [r0], #4
-       0x40,0xf8,0x04,0x3b,
-       //  33 0014 F8D1                bne     .L2
-       0xf8,0xd1,
-       //  34 0016 E268                ldr     r2, [r4, #12]
-       0xe2,0x68,
-       //  35 0018 2369                ldr     r3, [r4, #16]
-       0x23,0x69,
-       //  36 001a 5360                str     r3, [r2, #4]
-       0x53,0x60,
-       //  37 001c 0832                adds    r2, r2, #8
-       0x08,0x32,
-       //  38                  .L4:
-       //  39 001e 1068                ldr     r0, [r2, #0]
-       0x10,0x68,
-       //  40 0020 10F0010F            tst     r0, #1
-       0x10,0xf0,0x01,0x0f,
-       //  41 0024 FBD0                beq     .L4
-       0xfb,0xd0,
-       0x00,0xBE                               /* bkpt #0 */
+       sam3_page_write_opcodes[] = {
+       /*  24 0000 0446                mov     r4, r0 */
+       0x04, 0x46,
+       /*  25 0002 6168                ldr     r1, [r4, #4] */
+       0x61, 0x68,
+       /*  26 0004 0068                ldr     r0, [r0, #0] */
+       0x00, 0x68,
+       /*  27 0006 A268                ldr     r2, [r4, #8] */
+       0xa2, 0x68,
+       /*  28                          @ lr needed for prologue */
+       /*  29                  .L2: */
+       /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
+       0x51, 0xf8, 0x04, 0x3b,
+       /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
+       0x12, 0xf1, 0xff, 0x32,
+       /*  32 0010 40F8043B            str     r3, [r0], #4 */
+       0x40, 0xf8, 0x04, 0x3b,
+       /*  33 0014 F8D1                bne     .L2 */
+       0xf8, 0xd1,
+       /*  34 0016 E268                ldr     r2, [r4, #12] */
+       0xe2, 0x68,
+       /*  35 0018 2369                ldr     r3, [r4, #16] */
+       0x23, 0x69,
+       /*  36 001a 5360                str     r3, [r2, #4] */
+       0x53, 0x60,
+       /*  37 001c 0832                adds    r2, r2, #8 */
+       0x08, 0x32,
+       /*  38                  .L4: */
+       /*  39 001e 1068                ldr     r0, [r2, #0] */
+       0x10, 0x68,
+       /*  40 0020 10F0010F            tst     r0, #1 */
+       0x10, 0xf0, 0x01, 0x0f,
+       /*  41 0024 FBD0                beq     .L4 */
+       0xfb, 0xd0,
+       0x00, 0xBE                              /* bkpt #0 */
 };
 
-
-static int
-sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
+static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
 {
        uint32_t adr;
        uint32_t status;
-       uint32_t fmr; /* EEFC Flash Mode Register */
+       uint32_t fmr;   /* EEFC Flash Mode Register */
        int r;
 
        adr = pagenum * pPrivate->page_size;
@@ -2824,24 +2704,25 @@ sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *b
 
        LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
        r = target_write_memory(pPrivate->pChip->target,
-                                                        adr,
-                                                        4, /* THIS*MUST*BE* in 32bit values */
-                                                        pPrivate->page_size / 4,
-                                                        buf);
+                       adr,
+                       4,                                      /* THIS*MUST*BE* in 32bit values */
+                       pPrivate->page_size / 4,
+                       buf);
        if (r != ERROR_OK) {
-               LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr));
+               LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
+                       (unsigned int)(adr));
                return r;
        }
 
        r = EFC_PerformCommand(pPrivate,
-                                                       // send Erase & Write Page
-                                                       AT91C_EFC_FCMD_EWP,
-                                                       pagenum,
-                                                       &status);
+                       /* send Erase & Write Page */
+                       AT91C_EFC_FCMD_EWP,
+                       pagenum,
+                       &status);
 
-       if (r != ERROR_OK) {
-               LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr));
-       }
+       if (r != ERROR_OK)
+               LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
+                       (unsigned int)(adr));
        if (status & (1 << 2)) {
                LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
                return ERROR_FAIL;
@@ -2853,15 +2734,10 @@ sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *b
        return ERROR_OK;
 }
 
-
-
-
-
-static int
-sam3_write(struct flash_bank *bank,
-                  uint8_t *buffer,
-                  uint32_t offset,
-                  uint32_t count)
+static int sam3_write(struct flash_bank *bank,
+       uint8_t *buffer,
+       uint32_t offset,
+       uint32_t count)
 {
        int n;
        unsigned page_cur;
@@ -2871,10 +2747,10 @@ sam3_write(struct flash_bank *bank,
        struct sam3_bank_private *pPrivate;
        uint8_t *pagebuffer;
 
-       // incase we bail further below, set this to null
+       /* incase we bail further below, set this to null */
        pagebuffer = NULL;
 
-       // ignore dumb requests
+       /* ignore dumb requests */
        if (count == 0) {
                r = ERROR_OK;
                goto done;
@@ -2892,79 +2768,74 @@ sam3_write(struct flash_bank *bank,
                goto done;
        }
 
-
        if ((offset + count) > pPrivate->size_bytes) {
                LOG_ERROR("Flash write error - past end of bank");
                LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
-                                 (unsigned int)(offset),
-                                 (unsigned int)(count),
-                                 (unsigned int)(pPrivate->size_bytes));
+                       (unsigned int)(offset),
+                       (unsigned int)(count),
+                       (unsigned int)(pPrivate->size_bytes));
                r = ERROR_FAIL;
                goto done;
        }
 
        pagebuffer = malloc(pPrivate->page_size);
-       if( !pagebuffer ){
+       if (!pagebuffer) {
                LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
                r = ERROR_FAIL;
                goto done;
        }
 
-       // what page do we start & end in?
+       /* what page do we start & end in? */
        page_cur = offset / pPrivate->page_size;
        page_end = (offset + count - 1) / pPrivate->page_size;
 
        LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
        LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
 
-       // Special case: all one page
-       //
-       // Otherwise:
-       //    (1) non-aligned start
-       //    (2) body pages
-       //    (3) non-aligned end.
+       /* Special case: all one page */
+       /*  */
+       /* Otherwise: */
+       /*    (1) non-aligned start */
+       /*    (2) body pages */
+       /*    (3) non-aligned end. */
 
-       // Handle special case - all one page.
+       /* Handle special case - all one page. */
        if (page_cur == page_end) {
                LOG_DEBUG("Special case, all in one page");
                r = sam3_page_read(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
 
                page_offset = (offset & (pPrivate->page_size-1));
                memcpy(pagebuffer + page_offset,
-                               buffer,
-                               count);
+                       buffer,
+                       count);
 
                r = sam3_page_write(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
                r = ERROR_OK;
                goto done;
        }
 
-       // non-aligned start
+       /* non-aligned start */
        page_offset = offset & (pPrivate->page_size - 1);
        if (page_offset) {
                LOG_DEBUG("Not-Aligned start");
-               // read the partial
+               /* read the partial */
                r = sam3_page_read(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
 
-               // over-write with new data
+               /* over-write with new data */
                n = (pPrivate->page_size - page_offset);
                memcpy(pagebuffer + page_offset,
-                               buffer,
-                               n);
+                       buffer,
+                       n);
 
                r = sam3_page_write(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
 
                count  -= n;
                offset += n;
@@ -2976,45 +2847,41 @@ sam3_write(struct flash_bank *bank,
        fix a clang warning */
        assert(offset == pPrivate->page_size);
 
-       // intermediate large pages
-       // also - the final *terminal*
-       // if that terminal page is a full page
+       /* intermediate large pages */
+       /* also - the final *terminal* */
+       /* if that terminal page is a full page */
        LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
-                         (int)page_cur, (int)page_end, (unsigned int)(count));
+               (int)page_cur, (int)page_end, (unsigned int)(count));
 
        while ((page_cur < page_end) &&
-                  (count >= pPrivate->page_size)) {
+                       (count >= pPrivate->page_size)) {
                r = sam3_page_write(pPrivate, page_cur, buffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
-               count    -= pPrivate->page_size;
-               buffer   += pPrivate->page_size;
+               count -= pPrivate->page_size;
+               buffer += pPrivate->page_size;
                page_cur += 1;
        }
 
-       // terminal partial page?
+       /* terminal partial page? */
        if (count) {
                LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
-               // we have a partial page
+               /* we have a partial page */
                r = sam3_page_read(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
-               // data goes at start
+                                       /* data goes at start */
                memcpy(pagebuffer, buffer, count);
                r = sam3_page_write(pPrivate, page_cur, pagebuffer);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        goto done;
-               }
                buffer += count;
        }
        LOG_DEBUG("Done!");
        r = ERROR_OK;
- done:
-       if( pagebuffer ){
+done:
+       if (pagebuffer)
                free(pagebuffer);
-       }
        return r;
 }
 
@@ -3022,61 +2889,53 @@ COMMAND_HANDLER(sam3_handle_info_command)
 {
        struct sam3_chip *pChip;
        pChip = get_current_sam3(CMD_CTX);
-       if (!pChip) {
+       if (!pChip)
                return ERROR_OK;
-       }
 
        unsigned x;
        int r;
 
-       // bank0 must exist before we can do anything
+       /* bank0 must exist before we can do anything */
        if (pChip->details.bank[0].pBank == NULL) {
                x = 0;
-       need_define:
+need_define:
                command_print(CMD_CTX,
-                                          "Please define bank %d via command: flash bank %s ... ",
-                                          x,
-                                          at91sam3_flash.name);
+                       "Please define bank %d via command: flash bank %s ... ",
+                       x,
+                       at91sam3_flash.name);
                return ERROR_FAIL;
        }
 
-       // if bank 0 is not probed, then probe it
+       /* if bank 0 is not probed, then probe it */
        if (!(pChip->details.bank[0].probed)) {
                r = sam3_auto_probe(pChip->details.bank[0].pBank);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        return ERROR_FAIL;
-               }
        }
-       // above guarantees the "chip details" structure is valid
-       // and thus, bank private areas are valid
-       // and we have a SAM3 chip, what a concept!
+       /* above guarantees the "chip details" structure is valid */
+       /* and thus, bank private areas are valid */
+       /* and we have a SAM3 chip, what a concept! */
 
-
-       // auto-probe other banks, 0 done above
-    for (x = 1 ; x < SAM3_MAX_FLASH_BANKS ; x++) {
-               // skip banks not present
-               if (!(pChip->details.bank[x].present)) {
+       /* auto-probe other banks, 0 done above */
+       for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
+               /* skip banks not present */
+               if (!(pChip->details.bank[x].present))
                        continue;
-               }
 
-               if (pChip->details.bank[x].pBank == NULL) {
+               if (pChip->details.bank[x].pBank == NULL)
                        goto need_define;
-               }
 
-               if (pChip->details.bank[x].probed) {
+               if (pChip->details.bank[x].probed)
                        continue;
-               }
 
                r = sam3_auto_probe(pChip->details.bank[x].pBank);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        return r;
-               }
        }
 
-
        r = sam3_GetInfo(pChip);
        if (r != ERROR_OK) {
-               LOG_DEBUG("Sam3Info, Failed %d",r);
+               LOG_DEBUG("Sam3Info, Failed %d", r);
                return r;
        }
 
@@ -3085,63 +2944,59 @@ COMMAND_HANDLER(sam3_handle_info_command)
 
 COMMAND_HANDLER(sam3_handle_gpnvm_command)
 {
-       unsigned x,v;
-       int r,who;
+       unsigned x, v;
+       int r, who;
        struct sam3_chip *pChip;
 
        pChip = get_current_sam3(CMD_CTX);
-       if (!pChip) {
+       if (!pChip)
                return ERROR_OK;
-       }
 
        if (pChip->target->state != TARGET_HALTED) {
                LOG_ERROR("sam3 - target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-
        if (pChip->details.bank[0].pBank == NULL) {
                command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
-                                          at91sam3_flash.name);
+                       at91sam3_flash.name);
                return ERROR_FAIL;
        }
        if (!pChip->details.bank[0].probed) {
                r = sam3_auto_probe(pChip->details.bank[0].pBank);
-               if (r != ERROR_OK) {
+               if (r != ERROR_OK)
                        return r;
-               }
        }
 
        switch (CMD_ARGC) {
-       default:
-               return ERROR_COMMAND_SYNTAX_ERROR;
-               break;
-       case 0:
-               goto showall;
-               break;
-       case 1:
-               who = -1;
-               break;
-       case 2:
-               if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all"))) {
+               default:
+                       return ERROR_COMMAND_SYNTAX_ERROR;
+                       break;
+               case 0:
+                       goto showall;
+                       break;
+               case 1:
                        who = -1;
-               } else {
-                       uint32_t v32;
-                       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
-                       who = v32;
-               }
-               break;
+                       break;
+               case 2:
+                       if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
+                               who = -1;
+                       else {
+                               uint32_t v32;
+                               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
+                               who = v32;
+                       }
+                       break;
        }
 
        if (0 == strcmp("show", CMD_ARGV[0])) {
                if (who == -1) {
 showall:
                        r = ERROR_OK;
-                       for (x = 0 ; x < pChip->details.n_gpnvms ; x++) {
+                       for (x = 0; x < pChip->details.n_gpnvms; x++) {
                                r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
-                               if (r != ERROR_OK) {
+                               if (r != ERROR_OK)
                                        break;
-                               }
                                command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
                        }
                        return r;
@@ -3161,12 +3016,12 @@ showall:
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
-       if (0 == strcmp("set", CMD_ARGV[0])) {
+       if (0 == strcmp("set", CMD_ARGV[0]))
                r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
-       else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
-                          (0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
+       else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
+                (0 == strcmp("clear", CMD_ARGV[0])))                   /* quietly accept both */
                r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
-       else {
+       else {
                command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
                r = ERROR_COMMAND_SYNTAX_ERROR;
        }
@@ -3178,37 +3033,35 @@ COMMAND_HANDLER(sam3_handle_slowclk_command)
        struct sam3_chip *pChip;
 
        pChip = get_current_sam3(CMD_CTX);
-       if (!pChip) {
+       if (!pChip)
                return ERROR_OK;
-       }
-
 
        switch (CMD_ARGC) {
-       case 0:
-               // show
-               break;
-       case 1:
-       {
-               // set
-               uint32_t v;
-               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
-               if (v > 200000) {
-                       // absurd slow clock of 200Khz?
-                       command_print(CMD_CTX,"Absurd/illegal slow clock freq: %d\n", (int)(v));
-                       return ERROR_COMMAND_SYNTAX_ERROR;
+               case 0:
+                       /* show */
+                       break;
+               case 1:
+               {
+                       /* set */
+                       uint32_t v;
+                       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
+                       if (v > 200000) {
+                               /* absurd slow clock of 200Khz? */
+                               command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
+                               return ERROR_COMMAND_SYNTAX_ERROR;
+                       }
+                       pChip->cfg.slow_freq = v;
+                       break;
                }
-               pChip->cfg.slow_freq = v;
-               break;
-       }
-       default:
-               // error
-               command_print(CMD_CTX,"Too many parameters");
-               return ERROR_COMMAND_SYNTAX_ERROR;
-               break;
+               default:
+                       /* error */
+                       command_print(CMD_CTX, "Too many parameters");
+                       return ERROR_COMMAND_SYNTAX_ERROR;
+                       break;
        }
        command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
-                                  (int)(pChip->cfg.slow_freq/ 1000),
-                                  (int)(pChip->cfg.slow_freq% 1000));
+               (int)(pChip->cfg.slow_freq / 1000),
+               (int)(pChip->cfg.slow_freq % 1000));
        return ERROR_OK;
 }
 
index c2506be..e46122a 100644 (file)
 #include "imp.h"
 #include <helper/binarybuffer.h>
 
-
 /* AT91SAM7 control registers */
-#define DBGU_CIDR                      0xFFFFF240
-#define CKGR_MCFR                      0xFFFFFC24
-#define CKGR_MOR                       0xFFFFFC20
-#define CKGR_MCFR_MAINRDY      0x10000
-#define CKGR_PLLR                      0xFFFFFC2c
-#define CKGR_PLLR_DIV          0xff
-#define CKGR_PLLR_MUL          0x07ff0000
-#define PMC_MCKR                       0xFFFFFC30
-#define PMC_MCKR_CSS           0x03
-#define PMC_MCKR_PRES          0x1c
+#define DBGU_CIDR                       0xFFFFF240
+#define CKGR_MCFR                       0xFFFFFC24
+#define CKGR_MOR                        0xFFFFFC20
+#define CKGR_MCFR_MAINRDY       0x10000
+#define CKGR_PLLR                       0xFFFFFC2c
+#define CKGR_PLLR_DIV           0xff
+#define CKGR_PLLR_MUL           0x07ff0000
+#define PMC_MCKR                        0xFFFFFC30
+#define PMC_MCKR_CSS            0x03
+#define PMC_MCKR_PRES           0x1c
 
 /* Flash Controller Commands */
-#define WP             0x01
-#define SLB            0x02
-#define WPL            0x03
-#define CLB            0x04
-#define EA             0x08
-#define SGPB   0x0B
-#define CGPB   0x0D
-#define SSB            0x0F
+#define WP              0x01
+#define SLB             0x02
+#define WPL             0x03
+#define CLB             0x04
+#define EA              0x08
+#define SGPB    0x0B
+#define CGPB    0x0D
+#define SSB             0x0F
 
 /* MC_FSR bit definitions */
-#define MC_FSR_FRDY                    1
-#define MC_FSR_EOL                     2
+#define MC_FSR_FRDY                     1
+#define MC_FSR_EOL                      2
 
 /* AT91SAM7 constants */
-#define RC_FREQ                                32000
+#define RC_FREQ                         32000
 
 /* Flash timing modes */
-#define FMR_TIMING_NONE                0
-#define FMR_TIMING_NVBITS      1
-#define FMR_TIMING_FLASH       2
+#define FMR_TIMING_NONE         0
+#define FMR_TIMING_NVBITS       1
+#define FMR_TIMING_FLASH        2
 
 /* Flash size constants */
-#define FLASH_SIZE_8KB         1
-#define FLASH_SIZE_16KB                2
-#define FLASH_SIZE_32KB                3
-#define FLASH_SIZE_64KB                5
-#define FLASH_SIZE_128KB       7
-#define FLASH_SIZE_256KB       9
-#define FLASH_SIZE_512KB       10
-#define FLASH_SIZE_1024KB      12
-#define FLASH_SIZE_2048KB      14
-
+#define FLASH_SIZE_8KB          1
+#define FLASH_SIZE_16KB         2
+#define FLASH_SIZE_32KB         3
+#define FLASH_SIZE_64KB         5
+#define FLASH_SIZE_128KB        7
+#define FLASH_SIZE_256KB        9
+#define FLASH_SIZE_512KB        10
+#define FLASH_SIZE_1024KB       12
+#define FLASH_SIZE_2048KB       14
 
 static int at91sam7_protect_check(struct flash_bank *bank);
-static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
+static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset,
+               uint32_t count);
 
 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
@@ -111,10 +110,11 @@ static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
 static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
 static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
 
-static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
+static char *EPROC[8] = {
+       "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
+};
 
-struct at91sam7_flash_bank
-{
+struct at91sam7_flash_bank {
        /* chip id register */
        uint32_t cidr;
        uint16_t cidr_ext;
@@ -128,7 +128,7 @@ struct at91sam7_flash_bank
        const char *target_name;
 
        /* flash auto-detection */
-       uint8_t  flash_autodetection;
+       uint8_t flash_autodetection;
 
        /* flash geometry */
        uint16_t pages_per_sector;
@@ -141,15 +141,15 @@ struct at91sam7_flash_bank
        uint16_t num_nvmbits;
        uint16_t num_nvmbits_on;
        uint16_t nvmbits;
-       uint8_t  securitybit;
+       uint8_t securitybit;
 
        /* 0: not init
         * 1: fmcn for nvbits (1uS)
         * 2: fmcn for flash (1.5uS) */
-       uint8_t  flashmode;
+       uint8_t flashmode;
 
        /* main clock status */
-       uint8_t  mck_valid;
+       uint8_t mck_valid;
        uint32_t mck_freq;
 
        /* external clock frequency */
@@ -178,7 +178,6 @@ static long SRAMSIZ[16] = {
 };
 #endif
 
-
 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
 {
        uint32_t fsr;
@@ -206,8 +205,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
 
        at91sam7_info->mck_valid = 0;
        at91sam7_info->mck_freq = 0;
-       switch (mckr & PMC_MCKR_CSS)
-       {
+       switch (mckr & PMC_MCKR_CSS) {
                case 0:                 /* Slow Clock */
                        at91sam7_info->mck_valid = 1;
                        tmp = RC_FREQ;
@@ -215,13 +213,10 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
 
                case 1:                 /* Main Clock */
                        if ((mcfr & CKGR_MCFR_MAINRDY) &&
-                               (at91sam7_info->ext_freq == 0))
-                       {
+                       (at91sam7_info->ext_freq == 0)) {
                                at91sam7_info->mck_valid = 1;
                                tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
-                       }
-                       else if (at91sam7_info->ext_freq != 0)
-                       {
+                       } else if (at91sam7_info->ext_freq != 0) {
                                at91sam7_info->mck_valid = 1;
                                tmp = at91sam7_info->ext_freq;
                        }
@@ -232,35 +227,30 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
 
                case 3:                 /* PLL Clock */
                        if ((mcfr & CKGR_MCFR_MAINRDY) &&
-                               (at91sam7_info->ext_freq == 0))
-                       {
+                       (at91sam7_info->ext_freq == 0)) {
                                target_read_u32(target, CKGR_PLLR, &pllr);
                                if (!(pllr & CKGR_PLLR_DIV))
-                                       break; /* 0 Hz */
+                                       break;  /* 0 Hz */
                                at91sam7_info->mck_valid = 1;
                                mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
                                /* Integer arithmetic should have sufficient precision
                                 * as long as PLL is properly configured. */
                                tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
-                                       (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
-                       }
-                       else if ((at91sam7_info->ext_freq != 0) &&
-                               ((pllr&CKGR_PLLR_DIV) != 0))
-                       {
+                                               (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
+                       } else if ((at91sam7_info->ext_freq != 0) &&
+                                       ((pllr&CKGR_PLLR_DIV) != 0)) {
                                at91sam7_info->mck_valid = 1;
                                tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
-                                       (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
+                                               (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
                        }
                        break;
        }
 
        /* Prescaler adjust */
-       if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0))
-       {
+       if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0)) {
                at91sam7_info->mck_valid = 0;
                at91sam7_info->mck_freq = 0;
-       }
-       else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
+       } else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
                at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
        else
                at91sam7_info->mck_freq = tmp;
@@ -273,24 +263,17 @@ static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
        struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
        struct target *target = bank->target;
 
-       if (mode && (mode != at91sam7_info->flashmode))
-       {
+       if (mode && (mode != at91sam7_info->flashmode)) {
                /* Always round up (ceil) */
-               if (mode == FMR_TIMING_NVBITS)
-               {
-                       if (at91sam7_info->cidr_arch == 0x60)
-                       {
+               if (mode == FMR_TIMING_NVBITS) {
+                       if (at91sam7_info->cidr_arch == 0x60) {
                                /* AT91SAM7A3 uses master clocks in 100 ns */
                                fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
-                       }
-                       else
-                       {
+                       } else {
                                /* master clocks in 1uS for ARCH 0x7 types */
                                fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
                        }
-               }
-               else if (mode == FMR_TIMING_FLASH)
-               {
+               } else if (mode == FMR_TIMING_FLASH) {
                        /* main clocks in 1.5uS */
                        fmcn = (at91sam7_info->mck_freq/1000000ul)+
                                (at91sam7_info->mck_freq/2000000ul) + 1;
@@ -319,16 +302,15 @@ static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t wait
 {
        uint32_t status;
 
-       while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
-       {
+       while ((!((status = at91sam7_get_flash_status(bank->target,
+                       bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
                LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
                alive_sleep(1);
        }
 
        LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
 
-       if (status & 0x0C)
-       {
+       if (status & 0x0C) {
                LOG_ERROR("status register: 0x%" PRIx32 "", status);
                if (status & 0x4)
                        LOG_ERROR("Lock Error Bit Detected, Operation Abort");
@@ -350,22 +332,20 @@ static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t
 
        fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
        target_write_u32(target, MC_FCR[bank->bank_number], fcr);
-       LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
+       LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
+               fcr,
+               bank->bank_number + 1,
+               pagen);
 
-       if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB)))
-       {
+       if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB))) {
                /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
                if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
-               {
                        return ERROR_FLASH_OPERATION_FAILED;
-               }
                return ERROR_OK;
        }
 
        if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
-       {
                return ERROR_FLASH_OPERATION_FAILED;
-       }
 
        return ERROR_OK;
 }
@@ -392,14 +372,12 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 
        at91sam7_info = t_bank->driver_priv;
 
-       if (at91sam7_info->cidr != 0)
-       {
+       if (at91sam7_info->cidr != 0) {
                /* flash already configured, update clock and check for protected sectors */
                struct flash_bank *fb = bank;
                t_bank = fb;
 
-               while (t_bank)
-               {
+               while (t_bank) {
                        /* re-calculate master clock frequency */
                        at91sam7_read_clock_info(t_bank);
 
@@ -418,19 +396,16 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 
        /* Read and parse chip identification register */
        target_read_u32(target, DBGU_CIDR, &cidr);
-       if (cidr == 0)
-       {
+       if (cidr == 0) {
                LOG_WARNING("Cannot identify target as an AT91SAM");
                return ERROR_FLASH_OPERATION_FAILED;
        }
 
-       if (at91sam7_info->flash_autodetection == 0)
-       {
+       if (at91sam7_info->flash_autodetection == 0) {
                /* banks and sectors are already created, based on data from input file */
                struct flash_bank *fb = bank;
                t_bank = fb;
-               while (t_bank)
-               {
+               while (t_bank) {
                        at91sam7_info = t_bank->driver_priv;
 
                        at91sam7_info->cidr = cidr;
@@ -462,8 +437,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
        arch = (cidr >> 20)&0x00FF;
 
        /* check flash size */
-       switch ((cidr >> 8)&0x000F)
-       {
+       switch ((cidr >> 8)&0x000F) {
                case FLASH_SIZE_8KB:
                        break;
 
@@ -473,8 +447,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 32;
                        page_size  = 64;
                        base_address = 0x00100000;
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S161/16";
                        }
@@ -486,13 +459,11 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 32;
                        page_size  = 128;
                        base_address = 0x00100000;
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S321/32";
                        }
-                       if (arch == 0x72)
-                       {
+                       if (arch == 0x72) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7SE32";
                        }
@@ -504,8 +475,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 32;
                        page_size  = 128;
                        base_address = 0x00100000;
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S64";
                        }
@@ -517,23 +487,19 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 64;
                        page_size  = 256;
                        base_address = 0x00100000;
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S128";
                        }
-                       if (arch == 0x71)
-                       {
+                       if (arch == 0x71) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7XC128";
                        }
-                       if (arch == 0x72)
-                       {
+                       if (arch == 0x72) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7SE128";
                        }
-                       if (arch == 0x75)
-                       {
+                       if (arch == 0x75) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7X128";
                        }
@@ -545,28 +511,23 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 64;
                        page_size  = 256;
                        base_address = 0x00100000;
-                       if (arch == 0x60)
-                       {
+                       if (arch == 0x60) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7A3";
                        }
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S256";
                        }
-                       if (arch == 0x71)
-                       {
+                       if (arch == 0x71) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7XC256";
                        }
-                       if (arch == 0x72)
-                       {
+                       if (arch == 0x72) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7SE256";
                        }
-                       if (arch == 0x75)
-                       {
+                       if (arch == 0x75) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7X256";
                        }
@@ -578,23 +539,19 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        pages_per_sector = 64;
                        page_size  = 256;
                        base_address = 0x00100000;
-                       if (arch == 0x70)
-                       {
+                       if (arch == 0x70) {
                                num_nvmbits = 2;
                                target_name_t = "AT91SAM7S512";
                        }
-                       if (arch == 0x71)
-                       {
+                       if (arch == 0x71) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7XC512";
                        }
-                       if (arch == 0x72)
-                       {
+                       if (arch == 0x72) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7SE512";
                        }
-                       if (arch == 0x75)
-                       {
+                       if (arch == 0x75) {
                                num_nvmbits = 3;
                                target_name_t = "AT91SAM7X512";
                        }
@@ -607,9 +564,9 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                        break;
        }
 
-       if (strcmp(target_name_t, "Unknown") == 0)
-       {
-               LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
+       if (strcmp(target_name_t, "Unknown") == 0) {
+               LOG_ERROR(
+                       "Target autodetection failed! Please specify target parameters in configuration file");
                return ERROR_FLASH_OPERATION_FAILED;
        }
 
@@ -618,10 +575,8 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
        /* calculate bank size  */
        bank_size = sectors_num * pages_per_sector * page_size;
 
-       for (bnk = 0; bnk < banks_num; bnk++)
-       {
-               if (bnk > 0)
-               {
+       for (bnk = 0; bnk < banks_num; bnk++) {
+               if (bnk > 0) {
                        if (!t_bank->next) {
                                /* create a new flash bank element */
                                struct flash_bank *fb = malloc(sizeof(struct flash_bank));
@@ -646,8 +601,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 
                /* allocate sectors */
                t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
-               for (sec = 0; sec < sectors_num; sec++)
-               {
+               for (sec = 0; sec < sectors_num; sec++) {
                        t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
                        t_bank->sectors[sec].size = pages_per_sector * page_size;
                        t_bank->sectors[sec].is_erased = -1;
@@ -684,7 +638,9 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
                at91sam7_protect_check(t_bank);
        }
 
-       LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
+       LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
+               at91sam7_info->cidr_nvptyp,
+               at91sam7_info->cidr_arch);
 
        return ERROR_OK;
 }
@@ -699,8 +655,7 @@ static int at91sam7_erase_check(struct flash_bank *bank)
        uint16_t nSector;
        uint16_t nByte;
 
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -710,12 +665,12 @@ static int at91sam7_erase_check(struct flash_bank *bank)
        at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 
        fast_check = 1;
-       for (nSector = 0; nSector < bank->num_sectors; nSector++)
-       {
-               retval = target_blank_check_memory(target, bank->base + bank->sectors[nSector].offset,
-                       bank->sectors[nSector].size, &blank);
-               if (retval != ERROR_OK)
-               {
+       for (nSector = 0; nSector < bank->num_sectors; nSector++) {
+               retval = target_blank_check_memory(target,
+                               bank->base + bank->sectors[nSector].offset,
+                               bank->sectors[nSector].size,
+                               &blank);
+               if (retval != ERROR_OK) {
                        fast_check = 0;
                        break;
                }
@@ -726,25 +681,20 @@ static int at91sam7_erase_check(struct flash_bank *bank)
        }
 
        if (fast_check)
-       {
                return ERROR_OK;
-       }
 
        LOG_USER("Running slow fallback erase check - add working memory");
 
        buffer = malloc(bank->sectors[0].size);
-       for (nSector = 0; nSector < bank->num_sectors; nSector++)
-       {
+       for (nSector = 0; nSector < bank->num_sectors; nSector++) {
                bank->sectors[nSector].is_erased = 1;
                retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
-                       bank->sectors[nSector].size/4, buffer);
+                               bank->sectors[nSector].size/4, buffer);
                if (retval != ERROR_OK)
                        return retval;
 
-               for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++)
-               {
-                       if (buffer[nByte] != 0xFF)
-                       {
+               for (nByte = 0; nByte < bank->sectors[nSector].size; nByte++) {
+                       if (buffer[nByte] != 0xFF) {
                                bank->sectors[nSector].is_erased = 0;
                                break;
                        }
@@ -763,11 +713,8 @@ static int at91sam7_protect_check(struct flash_bank *bank)
        struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 
        if (at91sam7_info->cidr == 0)
-       {
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -776,14 +723,11 @@ static int at91sam7_protect_check(struct flash_bank *bank)
        at91sam7_info->lockbits = (status >> 16);
 
        at91sam7_info->num_lockbits_on = 0;
-       for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
-       {
-               if (((status >> (16 + lock_pos))&(0x0001)) == 1)
-               {
+       for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++) {
+               if (((status >> (16 + lock_pos))&(0x0001)) == 1) {
                        at91sam7_info->num_lockbits_on++;
                        bank->sectors[lock_pos].is_protected = 1;
-               }
-               else
+               } else
                        bank->sectors[lock_pos].is_protected = 0;
        }
 
@@ -794,12 +738,9 @@ static int at91sam7_protect_check(struct flash_bank *bank)
        at91sam7_info->nvmbits = (status >> 8)&0xFF;
 
        at91sam7_info->num_nvmbits_on = 0;
-       for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++)
-       {
+       for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++) {
                if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
-               {
                        at91sam7_info->num_nvmbits_on++;
-               }
        }
 
        return ERROR_OK;
@@ -837,8 +778,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
        at91sam7_info->ext_freq = 0;
        at91sam7_info->flash_autodetection = 0;
 
-       if (CMD_ARGC < 13)
-       {
+       if (CMD_ARGC < 13) {
                at91sam7_info->flash_autodetection = 1;
                return ERROR_OK;
        }
@@ -862,8 +802,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
        }
 
        if ((bus_width == 0) || (banks_num == 0) || (num_sectors == 0) ||
-               (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0))
-       {
+                       (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0)) {
                at91sam7_info->flash_autodetection = 1;
                return ERROR_OK;
        }
@@ -874,10 +813,8 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
        /* calculate bank size  */
        bank_size = num_sectors * pages_per_sector * page_size;
 
-       for (bnk = 0; bnk < banks_num; bnk++)
-       {
-               if (bnk > 0)
-               {
+       for (bnk = 0; bnk < banks_num; bnk++) {
+               if (bnk > 0) {
                        if (!t_bank->next) {
                                /* create a new bank element */
                                struct flash_bank *fb = malloc(sizeof(struct flash_bank));
@@ -902,8 +839,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
 
                /* allocate sectors */
                t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
-               for (sec = 0; sec < num_sectors; sec++)
-               {
+               for (sec = 0; sec < num_sectors; sec++) {
                        t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
                        t_bank->sectors[sec].size = pages_per_sector * page_size;
                        t_bank->sectors[sec].is_erased = -1;
@@ -933,61 +869,43 @@ static int at91sam7_erase(struct flash_bank *bank, int first, int last)
        uint8_t erase_all;
 
        if (at91sam7_info->cidr == 0)
-       {
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        if ((first < 0) || (last < first) || (last >= bank->num_sectors))
-       {
                return ERROR_FLASH_SECTOR_INVALID;
-       }
 
        erase_all = 0;
        if ((first == 0) && (last == (bank->num_sectors-1)))
-       {
                erase_all = 1;
-       }
 
        /* Configure the flash controller timing */
        at91sam7_read_clock_info(bank);
        at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 
-       if (erase_all)
-       {
+       if (erase_all) {
                if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
-               {
                        return ERROR_FLASH_OPERATION_FAILED;
-               }
-       }
-       else
-       {
+       } else {
                /* allocate and clean buffer  */
                nbytes = (last - first + 1) * bank->sectors[first].size;
                buffer = malloc(nbytes * sizeof(uint8_t));
                for (pos = 0; pos < nbytes; pos++)
-               {
                        buffer[pos] = 0xFF;
-               }
 
                if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
-               {
                        return ERROR_FLASH_OPERATION_FAILED;
-               }
 
                free(buffer);
        }
 
        /* mark erased sectors */
        for (sec = first; sec <= last; sec++)
-       {
                bank->sectors[sec].is_erased = 1;
-       }
 
        return ERROR_OK;
 }
@@ -1001,27 +919,21 @@ static int at91sam7_protect(struct flash_bank *bank, int set, int first, int las
        struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 
        if (at91sam7_info->cidr == 0)
-       {
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        if ((first < 0) || (last < first) || (last >= bank->num_sectors))
-       {
                return ERROR_FLASH_SECTOR_INVALID;
-       }
 
        /* Configure the flash controller timing */
        at91sam7_read_clock_info(bank);
        at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
 
-       for (sector = first; sector <= last; sector++)
-       {
+       for (sector = first; sector <= last; sector++) {
                if (set)
                        cmd = SLB;
                else
@@ -1032,9 +944,7 @@ static int at91sam7_protect(struct flash_bank *bank, int set, int first, int las
                pagen = sector * at91sam7_info->pages_per_sector;
 
                if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
-               {
                        return ERROR_FLASH_OPERATION_FAILED;
-               }
        }
 
        at91sam7_protect_check(bank);
@@ -1051,12 +961,9 @@ static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t off
        uint32_t first_page, last_page, pagen, buffer_pos;
 
        if (at91sam7_info->cidr == 0)
-       {
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -1066,9 +973,10 @@ static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t off
 
        dst_min_alignment = at91sam7_info->pagesize;
 
-       if (offset % dst_min_alignment)
-       {
-               LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, dst_min_alignment);
+       if (offset % dst_min_alignment) {
+               LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
+                       offset,
+                       dst_min_alignment);
                return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
        }
 
@@ -1078,14 +986,16 @@ static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t off
        first_page = offset/dst_min_alignment;
        last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
 
-       LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page, (int)last_page, (int)count);
+       LOG_DEBUG("first_page: %i, last_page: %i, count %i",
+               (int)first_page,
+               (int)last_page,
+               (int)count);
 
        /* Configure the flash controller timing */
        at91sam7_read_clock_info(bank);
        at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
 
-       for (pagen = first_page; pagen < last_page; pagen++)
-       {
+       for (pagen = first_page; pagen < last_page; pagen++) {
                if (bytes_remaining < dst_min_alignment)
                        count = bytes_remaining;
                else
@@ -1094,17 +1004,15 @@ static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t off
 
                /* Write one block to the PageWriteBuffer */
                buffer_pos = (pagen-first_page)*dst_min_alignment;
-               wcount = DIV_ROUND_UP(count,4);
-               if ((retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4, wcount, buffer + buffer_pos)) != ERROR_OK)
-               {
+               wcount = DIV_ROUND_UP(count, 4);
+               retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4,
+                               wcount, buffer + buffer_pos);
+               if (retval != ERROR_OK)
                        return retval;
-               }
 
                /* Send Write Page command to Flash Controller */
                if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
-               {
                        return ERROR_FLASH_OPERATION_FAILED;
-               }
                LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
        }
 
@@ -1117,8 +1025,7 @@ static int at91sam7_probe(struct flash_bank *bank)
         * if this is an at91sam7, it has the configured flash */
        int retval;
 
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -1136,40 +1043,44 @@ static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
        struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
 
        if (at91sam7_info->cidr == 0)
-       {
                return ERROR_FLASH_BANK_NOT_PROBED;
-       }
 
        printed = snprintf(buf, buf_size,
-               "\n at91sam7 driver information: Chip is %s\n",
-               at91sam7_info->target_name);
+                       "\n at91sam7 driver information: Chip is %s\n",
+                       at91sam7_info->target_name);
 
        buf += printed;
        buf_size -= printed;
 
        printed = snprintf(buf,
-                          buf_size,
-                          " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
-                          at91sam7_info->cidr,
-                          at91sam7_info->cidr_arch,
-                          EPROC[at91sam7_info->cidr_eproc],
-                          at91sam7_info->cidr_version,
-                          bank->size);
+                       buf_size,
+                       " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
+                       "Flashsize: 0x%8.8" PRIx32 "\n",
+                       at91sam7_info->cidr,
+                       at91sam7_info->cidr_arch,
+                       EPROC[at91sam7_info->cidr_eproc],
+                       at91sam7_info->cidr_version,
+                       bank->size);
 
        buf += printed;
        buf_size -= printed;
 
        printed = snprintf(buf, buf_size,
-               " Master clock (estimated): %u KHz | External clock: %u KHz\n",
-               (unsigned)(at91sam7_info->mck_freq / 1000), (unsigned)(at91sam7_info->ext_freq / 1000));
+                       " Master clock (estimated): %u KHz | External clock: %u KHz\n",
+                       (unsigned)(at91sam7_info->mck_freq / 1000),
+                       (unsigned)(at91sam7_info->ext_freq / 1000));
 
        buf += printed;
        buf_size -= printed;
 
-       printed = snprintf(buf, buf_size,
-               " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
-               at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
-               at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
+       printed = snprintf(buf,
+                       buf_size,
+                       " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i\n",
+                       at91sam7_info->pagesize,
+                       bank->num_sectors,
+                       at91sam7_info->num_lockbits_on,
+                       at91sam7_info->lockbits,
+                       at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
 
        buf += printed;
        buf_size -= printed;
@@ -1196,59 +1107,46 @@ COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
 {
        struct flash_bank *bank;
        int bit;
-       uint8_t  flashcmd;
+       uint8_t flashcmd;
        uint32_t status;
        struct at91sam7_flash_bank *at91sam7_info;
        int retval;
 
        if (CMD_ARGC != 2)
-       {
                return ERROR_COMMAND_SYNTAX_ERROR;
-       }
 
        bank = get_flash_bank_by_num_noprobe(0);
        if (bank ==  NULL)
-       {
                return ERROR_FLASH_BANK_INVALID;
-       }
-       if (strcmp(bank->driver->name, "at91sam7"))
-       {
+       if (strcmp(bank->driver->name, "at91sam7")) {
                command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
                return ERROR_FLASH_BANK_INVALID;
        }
-       if (bank->target->state != TARGET_HALTED)
-       {
+       if (bank->target->state != TARGET_HALTED) {
                LOG_ERROR("target has to be halted to perform flash operation");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        if (strcmp(CMD_ARGV[1], "set") == 0)
-       {
                flashcmd = SGPB;
-       }
        else if (strcmp(CMD_ARGV[1], "clear") == 0)
-       {
                flashcmd = CGPB;
-       }
        else
-       {
                return ERROR_COMMAND_SYNTAX_ERROR;
-       }
 
        at91sam7_info = bank->driver_priv;
-       if (at91sam7_info->cidr == 0)
-       {
+       if (at91sam7_info->cidr == 0) {
                retval = at91sam7_read_part_info(bank);
                if (retval != ERROR_OK)
-               {
                        return retval;
-               }
        }
 
        COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], bit);
-       if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
-       {
-               command_print(CMD_CTX, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV[0], at91sam7_info->target_name);
+       if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits)) {
+               command_print(CMD_CTX,
+                       "gpnvm bit '#%s' is out of bounds for target %s",
+                       CMD_ARGV[0],
+                       at91sam7_info->target_name);
                return ERROR_OK;
        }
 
@@ -1257,13 +1155,14 @@ COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
        at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
 
        if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
-       {
                return ERROR_FLASH_OPERATION_FAILED;
-       }
 
        /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
        status = at91sam7_get_flash_status(bank->target, 0);
-       LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32, flashcmd, bit, status);
+       LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
+               flashcmd,
+               bit,
+               status);
 
        /* check protect state */
        at91sam7_protect_check(bank);
index 462aee2..1dc5f07 100644 (file)
@@ -17,6 +17,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *