Empty lines at end of text files are useless.
Remove them.
Change-Id: I503cb0a96c7ccb132f4486c206a48831121d7abd
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5171
Tested-by: jenkins
echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
return $sr
}
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adapter speed 400
source [find target/adsp-sc58x.cfg]
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#usb_blaster_device_desc "USB-Blaster II"
adapter speed 100
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reset_config trst_only
# "amdm37x_dbginit am35x.cpu" needs to be run after init.
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# Add (A) sdram configuration
# Add (B) flash cfi programing configuration
#
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#set _FLASHNAME $_CHIPNAME.flash
#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
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mww 0xffffea04 0x0000039c
}
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set CHIPNAME at91sam7s256
source [find target/at91sam7sx.cfg]
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source [find target/at91sam3u4e.cfg]
reset_config srst_only
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source [find target/bcm281xx.cfg]
reset_config trst_and_srst
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# the bank is 32-bits wide, two 16-bit chips in parallel
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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#
mww 0xfffffd08 0xa5000001
}
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mww 0xE01FC08C 0x000000AA ;# PLLFEED
mww 0xE01FC08C 0x00000055 ;# PLLFEED
}
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#######################
# TODO: Implement NAND support.
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# startup @ 500kHz
adapter speed 500
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mww 0x600000CC 0x0000000C ;# Bank7 WST2=8
mww 0x600000C4 0x00000002 ;# Bank7 IDCY=2
}
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# for some reason this board like to startup @ 500kHz
adapter speed 500
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arm7_9 fast_memory_access enable
}
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#
source [find target/lpc17xx.cfg]
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#
source [find target/lpc2148.cfg]
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# The _TARGETNAME is set by the above.
$_TARGETNAME configure -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
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source [find target/atsame5x.cfg]
reset_config srst_only
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sysfsgpio_jtag_nums 136 139 137 138
source [find cpld/xilinx-xc6s.cfg]
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#
source [find target/lpc2378.cfg]
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#
source [find target/lpc2148.cfg]
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# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
source [find target/sam7x256.cfg]
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reset_config trst_only
# "amdm37x_dbginit dm37x.cpu" needs to be run after init.
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reset_config trst_and_srst
source [find board/ti_beaglebone-base.cfg]
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source [find target/omap4430.cfg]
reset_config trst_and_srst
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source [find target/omap4430.cfg]
reset_config trst_only
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source [find target/omap4460.cfg]
reset_config trst_only
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 $_TARGETNAME
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#flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
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set _NANDNAME $_CHIPNAME.nand
nand device $_NANDNAME s3c2410 $_TARGETNAME
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targets
nand probe 0
nand list
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set AT91_MATRIX_EBI1_VDDIOMSEL [expr (1 << 16)] ;# Memory voltage selection
set AT91_MATRIX_EBI1_VDDIOMSEL_1_8V [expr (0 << 16)]
set AT91_MATRIX_EBI1_VDDIOMSEL_3_3V [expr (1 << 16)]
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set AT91C_SLOWOSC_FREQ 32768
}
global AT91C_SLOWOSC_FREQ
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show_mmr32_reg RTTC_RTVR
show_mmr32_reg RTTC_RTSR
}
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unset str
proc show_DBGU_MR_helper { NAME ADDR VAL } { show_mmr_USx_MR_helper $NAME $ADDR $VAL }
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-
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set CPU_ARCH armv4t
set CPU_MAX_ADDRESS 0xFFFFFFFF
set CPU_NBITS 32
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set CPU_ARCH armv4t
set CPU_MAX_ADDRESS 0xFFFFFFFF
set CPU_NBITS 32
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set CPU_ARCH armv5te
set CPU_MAX_ADDRESS 0xFFFFFFFF
set CPU_NBITS 32
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set CPU_ARCH armv5te
set CPU_MAX_ADDRESS 0xFFFFFFFF
set CPU_NBITS 32
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set CPU_ARCH armv7
set CPU_MAX_ADDRESS 0xFFFFFFFF
set CPU_NBITS 32
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#
adapter driver arm-jtag-ew
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adapter driver at91rm9200
at91rm9200_device rea_ecr
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# this depends on the cable, you are safe with this option
reset_config srst_only
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adapter srst delay 200
jtag_ntrst_delay 200
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adapter driver parport
parport_cable chameleon
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ftdi_layout_init 0x0388 0x038b
ftdi_layout_signal nTRST -data 0x0100
ftdi_layout_signal nSRST -data 0x0080 -noe 0x200
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adapter driver parport
parport_port $_PARPORTADDR
parport_cable dlc5
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# number reset issues.
# eg.
#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
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#
adapter driver vsllink
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# it is not possible to halt the target unless these bits have been set
ap0.mem mww 0x31131000 0xFFFF
}
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# at this address and this bit.
$target mww phys 0x5401d030 0x00002000
}
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# serial SPI capable flash
# flash bank <driver> <base> <size> <chip_width> <bus_width>
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# We need to init now, so we can run the apsel command.
init
dap apsel 1
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# This is a 512K chip - it has the 2nd bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME at91sam3 0x0000C0000 0 1 1 $_TARGETNAME
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# at91sam3X8E
# at91sam3X8H
source [find target/at91sam3XXX.cfg]
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# size is automatically "calculated" by probing
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
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# size is automatically "calculated" by probing
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
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# size is automatically "calculated" by probing
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
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# size is automatically "calculated" by probing
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam3 0x000080000 0 1 1 $_TARGETNAME
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# This is a 256K chip, it has the 2nd bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
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# This is a 256K chip - it has the 2nd bank
set _FLASHNAME $_CHIPNAME.flash1
flash bank $_FLASHNAME at91sam3 0x000100000 0 1 1 $_TARGETNAME
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# at91sam3u1c
source [find target/at91sam3XXX.cfg]
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#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
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set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME avr32_ap7k -endian $_ENDIAN -chain-position $_TARGETNAME
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# This chip has a DCC ... use it
arm7_9 dcc_downloads enable
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reset_config trst_and_srst
adapter srst delay 200
jtag_ntrst_delay 200
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#setup flash
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
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#setup flash
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME dsp5680xx_flash 0 0 2 1 $_TARGETNAME
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reset_config trst_and_srst
adapter srst delay 200
jtag_ntrst_delay 200
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# that TAP is associated with a target
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME
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# send a router write, block is 0, register is 1, value is 0x2100
icepick_c_router $jrc 1 0x0 0x1 0x002101
}
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proc ixp42x_set_bigendian { } {
reg XSCALE_CTRL 0xF8
}
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$_TARGETNAME configure -event reset-init {
kinetis disable_wdog
}
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so one can create target subtype configurations where e.g. only
amount of DRAM, oscillator speeds differ and having a single
config file for the default/common settings.
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#reset configuration
reset_config trst_and_srst
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set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
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set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
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arc_em_init_regs
# vim:ft=tcl
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# Reduce speed since CPU speed will slow down to 16MHz with the reset
adapter speed 2000
}
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#flash bank <driver> <base> <size> <chip_width> <bus_width>
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME str7x 0x80000000 0x00040000 0 0 $_TARGETNAME STR73x
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jtag_ntrst_delay 100
reset_config trst_and_srst combined
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set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765
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Code Review / openocd.git / commitdiff