arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_UNKNOWN)
{
if (target->state == TARGET_UNKNOWN)
{
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state != TARGET_HALTED)
if (target->state != TARGET_HALTED)
FNC_INFO;
LOG_DEBUG("target->state: %s",
FNC_INFO;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
#if 0
LOG_DEBUG("target->state: %s",
#if 0
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
/* deassert reset lines */
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
{
int retval = ERROR_OK;
LOG_DEBUG("target->state: %s",
{
int retval = ERROR_OK;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
/* deassert reset lines */
jtag_add_reset(0, 0);
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
if (target->state == TARGET_HALTED)
{
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
- LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_name(target));
int cortex_m3_halt(target_t *target)
{
LOG_DEBUG("target->state: %s",
int cortex_m3_halt(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
if (target->state == TARGET_HALTED)
{
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
int cortex_m3_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
int cortex_m3_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
/* deassert reset lines */
jtag_add_reset(0, 0);
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
if (target->state == TARGET_HALTED)
{
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
/* deassert reset lines */
jtag_add_reset(0, 0);
{ .name = NULL , .value = -1 },
};
{ .name = NULL , .value = -1 },
};
+const char *
+target_state_name( target_t *t )
+{
+ const char *cp;
+ cp = Jim_Nvp_value2name_simple(nvp_target_state, t->state)->name;
+ if( !cp ){
+ LOG_ERROR("Invalid target state: %d", (int)(t->state));
+ cp = "(*BUG*unknown*BUG*)";
+ }
+ return cp;
+}
+
static int max_target_number(void)
{
target_t *t;
static int max_target_number(void)
{
target_t *t;
- LOG_USER("target state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name);
+ LOG_USER("target state: %s", target_state_name( target ));
if (target->state != TARGET_HALTED)
return ERROR_OK;
if (target->state != TARGET_HALTED)
return ERROR_OK;
char marker = ' ';
if (target->tap->enabled)
char marker = ' ';
if (target->tap->enabled)
- state = Jim_Nvp_value2name_simple(nvp_target_state,
- target->state)->name;
+ state = target_state_name( target );
else
state = "tap-disabled";
else
state = "tap-disabled";
return JIM_ERR;
}
Jim_SetResultString(goi.interp,
return JIM_ERR;
}
Jim_SetResultString(goi.interp,
- Jim_Nvp_value2name_simple(nvp_target_state,target->state)->name,-1);
+ target_state_name( target ),
+ -1);
return JIM_OK;
case TS_CMD_INVOKE_EVENT:
if (goi.argc != 1) {
return JIM_OK;
case TS_CMD_INVOKE_EVENT:
if (goi.argc != 1) {
* TARGET_RESET = 3: the target is being held in reset (only a temporary state,
* not sure how this is used with all the recent changes)
* TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
* TARGET_RESET = 3: the target is being held in reset (only a temporary state,
* not sure how this is used with all the recent changes)
* TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
- * behalf of the debugger (e.g. algorithm for flashing) */
+ * behalf of the debugger (e.g. algorithm for flashing)
+ *
+ * also see: target_state_name();
+ */
+
struct working_area_s *working_areas;/* list of allocated working areas */
enum target_debug_reason debug_reason;/* reason why the target entered debug state */
enum target_endianess endianness; /* target endianess */
struct working_area_s *working_areas;/* list of allocated working areas */
enum target_debug_reason debug_reason;/* reason why the target entered debug state */
enum target_endianess endianness; /* target endianess */
+ // also see: target_state_name()
enum target_state state; /* the current backend-state (running, halted, ...) */
struct reg_cache_s *reg_cache; /* the first register cache of the target (core regs) */
struct breakpoint_s *breakpoints; /* list of breakpoints */
enum target_state state; /* the current backend-state (running, halted, ...) */
struct reg_cache_s *reg_cache; /* the first register cache of the target (core regs) */
struct breakpoint_s *breakpoints; /* list of breakpoints */
extern int target_blank_check_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t* blank);
extern int target_wait_state(target_t *target, enum target_state state, int ms);
extern int target_blank_check_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t* blank);
extern int target_wait_state(target_t *target, enum target_state state, int ms);
+/** Return the *name* of this targets current state */
+const char *target_state_name( target_t *target );
+
/* DANGER!!!!!
*
* if "area" passed in to target_alloc_working_area() points to a memory
/* DANGER!!!!!
*
* if "area" passed in to target_alloc_working_area() points to a memory
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
if (target->state == TARGET_HALTED)
{
if (target->state == TARGET_HALTED)
{
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
- Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
+ target_state_name(target));
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
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