-#interface\r
-interface ft2232\r
-ft2232_device_desc "Amontec JTAGkey A"\r
-ft2232_layout jtagkey\r
-ft2232_vid_pid 0x0403 0xcff8\r
-jtag_speed 0\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
+#interface
+interface ft2232
+ft2232_device_desc "Amontec JTAGkey A"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xcff8
+jtag_speed 0
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
-#\r
-# Calao Systems USB-A9260-C01\r
-#\r
-# http://www.calao-systems.com/\r
-#\r
-interface ft2232\r
-ft2232_layout jtagkey\r
-ft2232_device_desc "USB-A9260"\r
-ft2232_vid_pid 0x0403 0x6010\r
-script interface/calao-usb-a9260.cfg\r
-script target/at91sam9260minimal.cfg\r
+#
+# Calao Systems USB-A9260-C01
+#
+# http://www.calao-systems.com/
+#
+interface ft2232
+ft2232_layout jtagkey
+ft2232_device_desc "USB-A9260"
+ft2232_vid_pid 0x0403 0x6010
+script interface/calao-usb-a9260.cfg
+script target/at91sam9260minimal.cfg
-#\r
-# Calao Systems USB-A9260-C02\r
-#\r
-# http://www.calao-systems.com/\r
-#\r
-interface ft2232\r
-ft2232_layout jtagkey\r
-ft2232_device_desc "USB-A9260 A"\r
-ft2232_vid_pid 0x0403 0x6001\r
-script interface/calao-usb-a9260.cfg\r
-script target/at91sam9260minimal.cfg\r
+#
+# Calao Systems USB-A9260-C02
+#
+# http://www.calao-systems.com/
+#
+interface ft2232
+ft2232_layout jtagkey
+ft2232_device_desc "USB-A9260 A"
+ft2232_vid_pid 0x0403 0x6001
+script interface/calao-usb-a9260.cfg
+script target/at91sam9260minimal.cfg
-#\r
-# Calao Systems USB-A9260 common -C01 -C02 setup\r
-#\r
-# http://www.calao-systems.com/\r
-#\r
-# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg\r
-#\r
-# note: you must have an openocd version where jtag_speed sets two values\r
-# trunk ver 606 contains the fix for this particular issue which can\r
-# be seen if jtag_speed does not set two separate values\r
-#\r
-jtag_speed 1200 0\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-\r
+#
+# Calao Systems USB-A9260 common -C01 -C02 setup
+#
+# http://www.calao-systems.com/
+#
+# See calao-usb-a9260-c01.cfg and calao-usb-a9260-c02.cfg
+#
+# note: you must have an openocd version where jtag_speed sets two values
+# trunk ver 606 contains the fix for this particular issue which can
+# be seen if jtag_speed does not set two separate values
+#
+jtag_speed 1200 0
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
-interface ft2232\r
-ft2232_device_desc "STR9-comStick A"\r
-ft2232_layout comstick\r
+interface ft2232
+ft2232_device_desc "STR9-comStick A"
+ft2232_layout comstick
-######################################\r
-# Target: Atmel AT91SAM9260\r
-######################################\r
-\r
-reset_config trst_and_srst\r
-\r
-#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-jtag_nsrst_delay 200\r
-jtag_ntrst_delay 200\r
-\r
-######################\r
-# Target configuration\r
-######################\r
-\r
-#target <type> <endianess> <reset mode> <JTAG pos> <variant>\r
-target arm926ejs little reset_run 0 arm926ejs\r
-run_and_halt_time 0 30\r
-\r
+######################################
+# Target: Atmel AT91SAM9260
+######################################
+
+reset_config trst_and_srst
+
+#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
+jtag_device 4 0x1 0xf 0xe
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+######################
+# Target configuration
+######################
+
+#target <type> <endianess> <reset mode> <JTAG pos> <variant>
+target arm926ejs little reset_run 0 arm926ejs
+run_and_halt_time 0 30
+
-# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.\r
-jtag_device 4 0x1 0xf 0xe\r
-jtag_nsrst_delay 100\r
-jtag_ntrst_delay 100\r
-#target configuration\r
-daemon_startup attach\r
-#target <type> <endianess> <reset mode>\r
-target arm920t little reset_halt 0\r
-working_area 0 0x80014000 0x1000 backup\r
-#flash configuration\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]\r
-flash bank cfi 0x60000000 0x1000000 2 2 0\r
+# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
+jtag_device 4 0x1 0xf 0xe
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#target configuration
+daemon_startup attach
+#target <type> <endianess> <reset mode>
+target arm920t little reset_halt 0
+working_area 0 0x80014000 0x1000 backup
+#flash configuration
+#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
+flash bank cfi 0x60000000 0x1000000 2 2 0
-#xscale ixp42x CPU\r
-\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-reset_config srst_only srst_pulls_trst\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 7 0x1 0x7f 0x7e\r
-#target configuration\r
-daemon_startup reset\r
-#target <type> <startup mode>\r
-#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
-target xscale big run_and_halt 0 IXP42x\r
-run_and_halt_time 0 30\r
+#xscale ixp42x CPU
+
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+#target configuration
+daemon_startup reset
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target xscale big run_and_halt 0 IXP42x
+run_and_halt_time 0 30
-#LPC-2129 CPU\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-reset_config trst_and_srst srst_pulls_trst\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-#target configuration\r
-daemon_startup reset\r
-#target <type> <startup mode>\r
-#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>\r
-target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4\r
-run_and_halt_time 0 30\r
-working_area 0 0x40000000 0x4000 nobackup\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum\r
+#LPC-2129 CPU
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+#target configuration
+daemon_startup reset
+#target <type> <startup mode>
+#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
+target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
+run_and_halt_time 0 30
+working_area 0 0x40000000 0x4000 nobackup
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
-#Hilscher netX 500 CPU\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-reset_config trst_and_srst\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-jtag_nsrst_delay 100\r
-jtag_ntrst_delay 100\r
-#target configuration\r
-daemon_startup reset\r
-#target <type> <endianness> <startup mode> <chainpos> <variant>\r
-target arm926ejs little run_and_halt 0 arm926ejs\r
-run_and_halt_time 0 500\r
+#Hilscher netX 500 CPU
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#target configuration
+daemon_startup reset
+#target <type> <endianness> <startup mode> <chainpos> <variant>
+target arm926ejs little run_and_halt 0 arm926ejs
+run_and_halt_time 0 500
-#TI OMAP5912 dual core processor - http://www.ti.com \r
-#on a OMAP5912 OSK board http://www.spectrumdigital.com.\r
-\r
-#use combined on interfaces or targets that can't set TRST/SRST separately\r
-reset_config trst_and_srst\r
-\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 38 0x0 0x0 0x0\r
-jtag_device 4 0x1 0x0 0xe\r
-jtag_device 8 0x0 0x0 0x0\r
-\r
-#target configuration\r
-daemon_startup reset\r
-\r
-#target <type> <endianness> <reset mode> <chainpos> <variant>\r
-target arm926ejs little run_and_init 1 arm926ejs\r
-target_script 0 reset event/omap5912_reset.script\r
-run_and_halt_time 0 30\r
-\r
-# omap5912 lcd frame buffer as working area\r
-working_area 0 0x20000000 0x3e800 nobackup\r
-\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-flash bank cfi 0x00000000 0x1000000 2 2 0\r
+#TI OMAP5912 dual core processor - http://www.ti.com
+#on a OMAP5912 OSK board http://www.spectrumdigital.com.
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 38 0x0 0x0 0x0
+jtag_device 4 0x1 0x0 0xe
+jtag_device 8 0x0 0x0 0x0
+
+#target configuration
+daemon_startup reset
+
+#target <type> <endianness> <reset mode> <chainpos> <variant>
+target arm926ejs little run_and_init 1 arm926ejs
+target_script 0 reset event/omap5912_reset.script
+run_and_halt_time 0 30
+
+# omap5912 lcd frame buffer as working area
+working_area 0 0x20000000 0x3e800 nobackup
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank cfi 0x00000000 0x1000000 2 2 0
-#Marvell/Intel PXA270 Script\r
-# set jtag_nsrst_delay to the delay introduced by your reset circuit\r
-# the rest of the needed delays are built into the openocd program\r
-jtag_nsrst_delay 260\r
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit\r
-# the rest of the needed delays are built into the openocd program\r
-jtag_ntrst_delay 0\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-reset_config trst_and_srst separate\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 7 0x1 0x7f 0x7e\r
-#target configuration\r
-daemon_startup reset\r
-target xscale little reset_halt 0 pxa27x\r
-# maps to PXA internal RAM. If you are using a PXA255\r
-# you must initialize SDRAM or leave this option off\r
-working_area 0 0x5c000000 0x10000 nobackup\r
-run_and_halt_time 0 30\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-# works for P30 flash\r
-flash bank cfi 0x00000000 0x1000000 2 4 0\r
+#Marvell/Intel PXA270 Script
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 260
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+reset_config trst_and_srst separate
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+#target configuration
+daemon_startup reset
+target xscale little reset_halt 0 pxa27x
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+working_area 0 0x5c000000 0x10000 nobackup
+run_and_halt_time 0 30
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# works for P30 flash
+flash bank cfi 0x00000000 0x1000000 2 4 0
-# Hitex stm32 performance stick\r
-jtag_nsrst_delay 100\r
-jtag_ntrst_delay 100\r
-\r
-#use combined on interfaces or targets that can't set TRST/SRST separately\r
-reset_config trst_and_srst\r
-\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-jtag_device 5 0x1 0x1 0x1e\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-#target <type> <startup mode>\r
-#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
-target cortex_m3 little reset_halt 0\r
-run_and_halt_time 0 30\r
-\r
-working_area 0 0x20000000 16384 nobackup\r
-\r
-#flash bank str7x <base> <size> 0 0 <target#> <variant>\r
-flash bank stm32x 0 0 0 0 0\r
-\r
-# For more information about the configuration files, take a look at:\r
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger\r
+# Hitex stm32 performance stick
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+jtag_device 5 0x1 0x1 0x1e
+jtag_device 4 0x1 0xf 0xe
+
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target cortex_m3 little reset_halt 0
+run_and_halt_time 0 30
+
+working_area 0 0x20000000 16384 nobackup
+
+#flash bank str7x <base> <size> 0 0 <target#> <variant>
+flash bank stm32x 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
-#STR730 CPU\r
-\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-#reset_config trst_and_srst srst_pulls_trst\r
-reset_config trst_and_srst srst_pulls_trst\r
-\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-#jtag nTRST and nSRST delay\r
-jtag_nsrst_delay 500\r
-jtag_ntrst_delay 500\r
-\r
-#target configuration\r
-daemon_startup reset\r
-\r
-#target <type> <startup mode>\r
-#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
-target arm7tdmi little run_and_halt 0 arm7tdmi\r
-\r
-run_and_halt_time 0 30\r
-\r
-working_area 0 0x40000000 0x4000 nobackup\r
-\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x\r
-\r
+#STR730 CPU
+
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#jtag nTRST and nSRST delay
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+#target configuration
+daemon_startup reset
+
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target arm7tdmi little run_and_halt 0 arm7tdmi
+
+run_and_halt_time 0 30
+
+working_area 0 0x40000000 0x4000 nobackup
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
+
-#STR750 CPU\r
-\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-#reset_config trst_and_srst srst_pulls_trst\r
-reset_config trst_and_srst srst_pulls_trst\r
-\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 4 0x1 0xf 0xe\r
-\r
-#jtag nTRST and nSRST delay\r
-jtag_nsrst_delay 500\r
-jtag_ntrst_delay 500\r
-\r
-#target configuration\r
-daemon_startup reset\r
-\r
-#target <type> <startup mode>\r
-#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>\r
-target arm7tdmi little run_and_halt 0 arm7tdmi\r
-\r
-run_and_halt_time 0 30\r
-\r
-working_area 0 0x40000000 0x4000 nobackup\r
-\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x\r
-flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x\r
-\r
+#STR750 CPU
+
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+#reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#jtag nTRST and nSRST delay
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+#target configuration
+daemon_startup reset
+
+#target <type> <startup mode>
+#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
+target arm7tdmi little run_and_halt 0 arm7tdmi
+
+run_and_halt_time 0 30
+
+working_area 0 0x40000000 0x4000 nobackup
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
+flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x
+
-#Hitex STR9 Comstick\r
-jtag_nsrst_delay 100\r
-jtag_ntrst_delay 100\r
-#use combined on interfaces or targets that can\92t set TRST/SRST separately\r
-reset_config trst_and_srst\r
-#jtag scan chain\r
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)\r
-jtag_device 8 0x1 0x1 0xfe\r
-jtag_device 4 0x1 0xf 0xe\r
-jtag_device 5 0x1 0x1 0x1e\r
-#target configuration\r
-daemon_startup reset\r
-#target <type> <startup mode>\r
-#target arm966e <endianness> <reset mode> <chainpos> <variant>\r
-target arm966e little reset_halt 1 arm966e\r
-run_and_halt_time 0 30\r
-working_area 0 0x50000000 16384 nobackup\r
-#flash bank <driver> <base> <size> <chip_width> <bus_width>\r
-flash bank str9x 0x00000000 0x00080000 0 0 0\r
+#Hitex STR9 Comstick
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can\92t set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 8 0x1 0x1 0xfe
+jtag_device 4 0x1 0xf 0xe
+jtag_device 5 0x1 0x1 0x1e
+#target configuration
+daemon_startup reset
+#target <type> <startup mode>
+#target arm966e <endianness> <reset mode> <chainpos> <variant>
+target arm966e little reset_halt 1 arm966e
+run_and_halt_time 0 30
+working_area 0 0x50000000 16384 nobackup
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str9x 0x00000000 0x00080000 0 0 0
Code Review / openocd.git / commitdiff