MIPS: remove ejtag_srst variant

The mips_m4k_assert_reset has now been restructured
so the variant ejtag_srst is not required anymore.
The ejtag software reset will be used if the target does not
have srst connected.

Remove ejtag_srst from docs.

Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e1bb2b770892b7ae2e4ddebcb51cb5b1a98d3ee1..780cd4d73348887d071058ee3593907d7457de8e 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3453,14 +3453,6 @@ be detected and the normal reset behaviour used.
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
 @item @code{mips_m4k} -- a MIPS core.  This supports one variant:
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
 @item @code{mips_m4k} -- a MIPS core.  This supports one variant:

-@itemize @minus
-@item @code{ejtag_srst} ... Use this when debugging targets that do not
-provide a functional SRST line on the EJTAG connector.  This causes
-OpenOCD to instead use an EJTAG software reset command to reset the
-processor.
-You still need to enable @option{srst} on the @command{reset_config}
-command to enable OpenOCD hardware reset functionality.
-@end itemize

 @item @code{xscale} -- this is actually an architecture,
 not a CPU type.  It is based on the ARMv5 architecture.
 There are several variants defined:
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type.  It is based on the ARMv5 architecture.
 There are several variants defined:

diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 389daf97c6b3a96bde69083e1dcd479403828a38..d3536d8fc8d2654ce61fbd595b1c61400b39d5b6 100644 (file)
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -212,18 +212,17 @@ int mips_m4k_halt(struct target *target)
 
 int mips_m4k_assert_reset(struct target *target)
 {
 
 int mips_m4k_assert_reset(struct target *target)
 {

-       struct mips32_common *mips32 = target_to_mips32(target);
-       struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+       struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+       struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+       int assert_srst = 1;

 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
 
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();

+

        if (!(jtag_reset_config & RESET_HAS_SRST))
        if (!(jtag_reset_config & RESET_HAS_SRST))

-       {
-               LOG_ERROR("Can't assert SRST");
-               return ERROR_FAIL;
-       }
+               assert_srst = 0;

 
        if (target->reset_halt)
        {
 
        if (target->reset_halt)
        {


@@ -237,14 +236,7 @@ int mips_m4k_assert_reset(struct target *target)
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
        }
 
                mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
        }
 

-       if (strcmp(target->variant, "ejtag_srst") == 0)
-       {
-               uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
-               LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
-               mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-               mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-       }
-       else
+       if (assert_srst)

        {
                /* here we should issue a srst only, but we may have to assert trst as well */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)
        {
                /* here we should issue a srst only, but we may have to assert trst as well */
                if (jtag_reset_config & RESET_SRST_PULLS_TRST)


@@ -256,11 +248,19 @@ int mips_m4k_assert_reset(struct target *target)
                        jtag_add_reset(0, 1);
                }
        }
                        jtag_add_reset(0, 1);
                }
        }

+       else
+       {
+                       /* use ejtag reset - not supported by all cores */
+                       uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+                       LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+                       mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+                       mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+       }

 
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 
 
        target->state = TARGET_RESET;
        jtag_add_sleep(50000);
 

-       register_cache_invalidate(mips32->core_cache);
+       register_cache_invalidate(mips_m4k->mips32.core_cache);

 
        if (target->reset_halt)
        {
 
        if (target->reset_halt)
        {

diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 4fe14a0d67b128f9e0a213494861a5bfb674bd0d..9b3302080b2509ba4b9e579cbf4fad4dd99fcbdc 100644 (file)
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,14 +32,14 @@ struct target;
 struct mips_m4k_common
 {
        int common_magic;
 struct mips_m4k_common
 {
        int common_magic;

-       struct mips32_common mips32_common;
+       struct mips32_common mips32;

 };
 
 static inline struct mips_m4k_common *
 target_to_m4k(struct target *target)
 {
        return container_of(target->arch_info,
 };
 
 static inline struct mips_m4k_common *
 target_to_m4k(struct target *target)
 {
        return container_of(target->arch_info,

-                       struct mips_m4k_common, mips32_common);
+                       struct mips_m4k_common, mips32);

 }
 
 int mips_m4k_bulk_write_memory(struct target *target,
 }
 
 int mips_m4k_bulk_write_memory(struct target *target,