- add target_to_mips32 and target_to_m4k to match test of codebase.
- mips32_arch_state now shows if processer is running mips16e isa.
Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
"status", "lo", "hi", "badvaddr", "cause", "pc"
};
"status", "lo", "hi", "badvaddr", "cause", "pc"
};
+const char *mips_isa_strings[] =
+{
+ "MIPS32", "MIPS16e"
+};
+
struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
{
{0, NULL, NULL},
struct mips32_core_reg mips32_core_reg_list_arch_info[MIPS32NUMCOREREGS] =
{
{0, NULL, NULL},
int retval;
struct mips32_core_reg *mips32_reg = reg->arch_info;
struct target *target = mips32_reg->target;
int retval;
struct mips32_core_reg *mips32_reg = reg->arch_info;
struct target *target = mips32_reg->target;
- struct mips32_common *mips32_target = target->arch_info;
+ struct mips32_common *mips32_target = target_to_mips32(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if ((num < 0) || (num >= MIPS32NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
if ((num < 0) || (num >= MIPS32NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
struct mips32_core_reg *mips_core_reg;
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if ((num < 0) || (num >= MIPS32NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
if ((num < 0) || (num >= MIPS32NUMCOREREGS))
return ERROR_INVALID_ARGUMENTS;
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
int mips32_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int *reg_list_size)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
int i;
/* include floating point registers */
int i;
/* include floating point registers */
int i;
/* get pointers to arch-specific information */
int i;
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* read core registers */
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* read core registers */
int i;
/* get pointers to arch-specific information */
int i;
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
for (i = 0; i < MIPS32NUMCOREREGS; i++)
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
for (i = 0; i < MIPS32NUMCOREREGS; i++)
int mips32_arch_state(struct target *target)
{
int mips32_arch_state(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
-
- if (mips32->common_magic != MIPS32_COMMON_MAGIC)
- {
- LOG_ERROR("BUG: called for a non-MIPS32 target");
- return ERROR_FAIL;
- }
+ struct mips32_common *mips32 = target_to_mips32(target);
- LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
+ LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
+ mips_isa_strings[mips32->isa_mode],
debug_reason_name(target),
buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
debug_reason_name(target),
buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
struct reg_cache *mips32_build_reg_cache(struct target *target)
{
/* get pointers to arch-specific information */
struct reg_cache *mips32_build_reg_cache(struct target *target)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
int num_regs = MIPS32NUMCOREREGS;
struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
int mips32_examine(struct target *target)
{
int mips32_examine(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if (!target_was_examined(target))
{
if (!target_was_examined(target))
{
int mips32_configure_break_unit(struct target *target)
{
/* get pointers to arch-specific information */
int mips32_configure_break_unit(struct target *target)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
int retval;
uint32_t dcr, bpinfo;
int i;
int retval;
uint32_t dcr, bpinfo;
int i;
if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
return retval;
if ((retval = target_read_u32(target, EJTAG_DCR, &dcr)) != ERROR_OK)
return retval;
+ if (dcr & EJTAG_DCR_IB)
{
/* get number of inst breakpoints */
if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
{
/* get number of inst breakpoints */
if ((retval = target_read_u32(target, EJTAG_IBS, &bpinfo)) != ERROR_OK)
+ if (dcr & EJTAG_DCR_DB)
{
/* get number of data breakpoints */
if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
{
/* get number of data breakpoints */
if ((retval = target_read_u32(target, EJTAG_DBS, &bpinfo)) != ERROR_OK)
+ if (!(dcr & EJTAG_DCR_INTE))
{
/* enable interrupts */
{
/* enable interrupts */
+ if (dcr & EJTAG_DCR_INTE)
{
/* disable interrupts */
{
/* disable interrupts */
+ dcr &= ~EJTAG_DCR_INTE;
#include "target.h"
#include "mips32_pracc.h"
#include "target.h"
#include "mips32_pracc.h"
#define MIPS32_COMMON_MAGIC 0xB320B320
/* offsets into mips32 core register cache */
#define MIPS32_COMMON_MAGIC 0xB320B320
/* offsets into mips32 core register cache */
+enum mips32_isa_mode
+{
+ MIPS32_ISA_MIPS32 = 0,
+ MIPS32_ISA_MIPS16E = 1,
+};
+
+extern const char *mips_isa_strings[];
+
struct mips32_comparator
{
int used;
struct mips32_comparator
{
int used;
uint32_t bp_value;
uint32_t reg_address;
};
uint32_t bp_value;
uint32_t reg_address;
};
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
uint32_t core_regs[MIPS32NUMCOREREGS];
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
uint32_t core_regs[MIPS32NUMCOREREGS];
+ enum mips32_isa_mode isa_mode;
int bp_scanned;
int num_inst_bpoints;
int bp_scanned;
int num_inst_bpoints;
int (*write_core_reg)(struct target *target, int num);
};
int (*write_core_reg)(struct target *target, int num);
};
+static inline struct mips32_common *
+target_to_mips32(struct target *target)
+{
+ return target->arch_info;
+}
+
struct mips32_core_reg
{
uint32_t num;
struct mips32_core_reg
{
uint32_t num;
MIPS32_LW(2,36*4,1), /* lw $2,36*4($1) */
MIPS32_MTC0(2,13,0), /* move $2 to cause*/
MIPS32_LW(2,37*4,1), /* lw $2,37*4($1) */
MIPS32_LW(2,36*4,1), /* lw $2,36*4($1) */
MIPS32_MTC0(2,13,0), /* move $2 to cause*/
MIPS32_LW(2,37*4,1), /* lw $2,37*4($1) */
- MIPS32_MTC0(2,24,0), /* move $2 to pc */
+ MIPS32_MTC0(2,24,0), /* move $2 to depc (pc) */
MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */
MIPS32_LW(1,0,15), /* lw $1,($15) */
MIPS32_LW(2,2*4,1), /* lw $2,2*4($1) */
MIPS32_LW(1,0,15), /* lw $1,($15) */
MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */
MIPS32_MFC0(2,13,0), /* move cause to $2 */
MIPS32_SW(2,36*4,1), /* sw $2,36*4($1) */
MIPS32_SW(2,35*4,1), /* sw $2,35*4($1) */
MIPS32_MFC0(2,13,0), /* move cause to $2 */
MIPS32_SW(2,36*4,1), /* sw $2,36*4($1) */
- MIPS32_MFC0(2,24,0), /* move pc to $2 */
+ MIPS32_MFC0(2,24,0), /* move depc (pc) to $2 */
MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */
MIPS32_LW(2,0,15), /* lw $2,($15) */
MIPS32_SW(2,37*4,1), /* sw $2,37*4($1) */
MIPS32_LW(2,0,15), /* lw $2,($15) */
break;
}
LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
break;
}
LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
- ejtag_info->impcode & (1 << 28) ? " R3k": " R4k",
- ejtag_info->impcode & (1 << 24) ? " DINT": "",
- ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
- ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
- ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
- ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
- ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
-);
-
- if ((ejtag_info->impcode & (1 << 14)) == 0)
+ ejtag_info->impcode & EJTAG_IMP_R3K ? " R3k" : " R4k",
+ ejtag_info->impcode & EJTAG_IMP_DINT ? " DINT" : "",
+ ejtag_info->impcode & (1 << 22) ? " ASID_8" : "",
+ ejtag_info->impcode & (1 << 21) ? " ASID_6" : "",
+ ejtag_info->impcode & EJTAG_IMP_MIPS16 ? " MIPS16" : "",
+ ejtag_info->impcode & EJTAG_IMP_NODMA ? " noDMA" : " DMA",
+ ejtag_info->impcode & EJTAG_DCR_MIPS64 ? " MIPS64" : " MIPS32");
+
+ if ((ejtag_info->impcode & EJTAG_IMP_NODMA) == 0)
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
/* set initial state for ejtag control reg */
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
/* set initial state for ejtag control reg */
#define EJTAG_INST_TCBDATA 0x12
#define EJTAG_INST_BYPASS 0xFF
#define EJTAG_INST_TCBDATA 0x12
#define EJTAG_INST_BYPASS 0xFF
-/* debug control register bits ECR */
+/* ejtag control register bits ECR */
#define EJTAG_CTRL_TOF (1 << 1)
#define EJTAG_CTRL_TIF (1 << 2)
#define EJTAG_CTRL_BRKST (1 << 3)
#define EJTAG_CTRL_TOF (1 << 1)
#define EJTAG_CTRL_TIF (1 << 2)
#define EJTAG_CTRL_BRKST (1 << 3)
#define EJTAG_DEBUG_DBD (1 << 31)
/* implementaion register bits */
#define EJTAG_DEBUG_DBD (1 << 31)
/* implementaion register bits */
+#define EJTAG_IMP_R3K (1 << 28)
+#define EJTAG_IMP_DINT (1 << 24)
#define EJTAG_IMP_NODMA (1 << 14)
#define EJTAG_IMP_MIPS16 (1 << 16)
#define EJTAG_IMP_NODMA (1 << 14)
#define EJTAG_IMP_MIPS16 (1 << 16)
+#define EJTAG_DCR_MIPS64 (1 << 0)
-/* breakpoint support */
+/* Debug Control Register DCR */
#define EJTAG_DCR 0xFF300000
#define EJTAG_DCR 0xFF300000
+#define EJTAG_DCR_ENM (1 << 29)
+#define EJTAG_DCR_DB (1 << 17)
+#define EJTAG_DCR_IB (1 << 16)
+#define EJTAG_DCR_INTE (1 << 4)
+
+/* breakpoint support */
#define EJTAG_IBS 0xFF301000
#define EJTAG_IBA1 0xFF301100
#define EJTAG_DBS 0xFF302000
#define EJTAG_IBS 0xFF301000
#define EJTAG_IBA1 0xFF301100
#define EJTAG_DBS 0xFF302000
struct jtag_tap *tap;
uint32_t impcode;
uint32_t idcode;
struct jtag_tap *tap;
uint32_t impcode;
uint32_t idcode;
}
/* get info about data breakpoint support */
}
/* get info about data breakpoint support */
- if ((retval = target_read_u32(target, 0xFF302000, &break_status)) != ERROR_OK)
+ if ((retval = target_read_u32(target, EJTAG_DBS, &break_status)) != ERROR_OK)
return retval;
if (break_status & 0x1f)
{
/* we have halted on a breakpoint */
return retval;
if (break_status & 0x1f)
{
/* we have halted on a breakpoint */
- if ((retval = target_write_u32(target, 0xFF302000, 0)) != ERROR_OK)
+ if ((retval = target_write_u32(target, EJTAG_DBS, 0)) != ERROR_OK)
return retval;
target->debug_reason = DBG_REASON_WATCHPOINT;
}
return retval;
target->debug_reason = DBG_REASON_WATCHPOINT;
}
int mips_m4k_debug_entry(struct target *target)
{
int mips_m4k_debug_entry(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t debug_reg;
/* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t debug_reg;
/* read debug register */
mips_ejtag_read_debug(ejtag_info, &debug_reg);
- /* make sure break uit configured */
+ /* make sure break unit configured */
mips32_configure_break_unit(target);
/* attempt to find halt reason */
mips32_configure_break_unit(target);
/* attempt to find halt reason */
mips32_save_context(target);
mips32_save_context(target);
+ /* default to mips32 isa, it will be changed below if required */
+ mips32->isa_mode = MIPS32_ISA_MIPS32;
+
+ if (ejtag_info->impcode & EJTAG_IMP_MIPS16)
+ {
+ if (buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32) & 0x01)
+ {
+ /* core is running mips16e isa */
+ mips32->isa_mode = MIPS32_ISA_MIPS16E;
+ }
+ }
+
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
- *(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
- target_state_name(target));
+ buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
+ target_state_name(target));
int mips_m4k_poll(struct target *target)
{
int retval;
int mips_m4k_poll(struct target *target)
{
int retval;
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
int mips_m4k_halt(struct target *target)
{
int mips_m4k_halt(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
int mips_m4k_assert_reset(struct target *target)
{
int mips_m4k_assert_reset(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
int mips_m4k_single_step_core(struct target *target)
{
int mips_m4k_single_step_core(struct target *target)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* configure single step mode */
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* configure single step mode */
int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
int mips_m4k_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct breakpoint *breakpoint = NULL;
uint32_t resume_pc;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct breakpoint *breakpoint = NULL;
uint32_t resume_pc;
int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
int mips_m4k_step(struct target *target, int current, uint32_t address, int handle_breakpoints)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct breakpoint *breakpoint = NULL;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct breakpoint *breakpoint = NULL;
int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int mips_m4k_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips32_comparator * comparator_list = mips32->inst_break_list;
int retval;
struct mips32_comparator * comparator_list = mips32->inst_break_list;
int retval;
int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
/* get pointers to arch-specific information */
int mips_m4k_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
- struct mips32_comparator * comparator_list = mips32->inst_break_list;
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips32_comparator *comparator_list = mips32->inst_break_list;
int retval;
if (!breakpoint->set)
int retval;
if (!breakpoint->set)
int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
int mips_m4k_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if (breakpoint->type == BKPT_HARD)
{
if (breakpoint->type == BKPT_HARD)
{
int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
/* get pointers to arch-specific information */
int mips_m4k_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int mips_m4k_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
- struct mips32_common *mips32 = target->arch_info;
- struct mips32_comparator * comparator_list = mips32->data_break_list;
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips32_comparator *comparator_list = mips32->data_break_list;
int wp_num = 0;
/*
* watchpoint enabled, ignore all byte lanes in value register
int wp_num = 0;
/*
* watchpoint enabled, ignore all byte lanes in value register
int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
int mips_m4k_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
- struct mips32_comparator * comparator_list = mips32->data_break_list;
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips32_comparator *comparator_list = mips32->data_break_list;
int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
int mips_m4k_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if (mips32->num_data_bpoints_avail < 1)
{
if (mips32->num_data_bpoints_avail < 1)
{
int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
int mips_m4k_remove_watchpoint(struct target *target, struct watchpoint *watchpoint)
{
/* get pointers to arch-specific information */
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED)
{
int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int mips_m4k_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int mips_m4k_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
{
int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
{
- struct mips_m4k_common *mips_m4k = calloc(1,sizeof(struct mips_m4k_common));
+ struct mips_m4k_common *mips_m4k = calloc(1, sizeof(struct mips_m4k_common));
mips_m4k_init_arch_info(target, mips_m4k, target->tap);
mips_m4k_init_arch_info(target, mips_m4k, target->tap);
int mips_m4k_examine(struct target *target)
{
int retval;
int mips_m4k_examine(struct target *target)
{
int retval;
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t idcode = 0;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
uint32_t idcode = 0;
int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
int mips_m4k_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
- struct mips32_common *mips32 = target->arch_info;
+ struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct working_area *source;
int retval;
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct working_area *source;
int retval;
struct mips32_common mips32_common;
};
struct mips32_common mips32_common;
};
+static inline struct mips_m4k_common *
+target_to_m4k(struct target *target)
+{
+ return container_of(target->arch_info,
+ struct mips_m4k_common, mips32_common);
+}
+
int mips_m4k_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer);
int mips_m4k_bulk_write_memory(struct target *target,
uint32_t address, uint32_t count, uint8_t *buffer);
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)