Identified by checkpatch script from Linux kernel v5.7-rc1 using
the command
find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types TYPO_SPELLING --strict -f {} \;
Change-Id: I7b523f0ab5ec047ff167742a44c29984ac672cf4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5615
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins
31 files changed:
# select PLL as main source
mww 0x80040120 0x1
# select PLL as main source
mww 0x80040120 0x1
- # disable and enble main clk to update changes?
+ # disable and enable main clk to update changes?
mww 0x80040124 0x0
mww 0x80040124 0x1
mww 0x80040124 0x0
mww 0x80040124 0x1
# TRC = 9 cycles
# TWR = 2 cycles
# 9 column, 13 row, 4 banks
# TRC = 9 cycles
# TWR = 2 cycles
# 9 column, 13 row, 4 banks
- # refresh equal to or less then 7.8 us for commerical/industrial rated devices
+ # refresh equal to or less then 7.8 us for commercial/industrial rated devices
#
# Thus SDRAM_CR = 0xa6339279
#
# Thus SDRAM_CR = 0xa6339279
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
$_TARGETNAME configure -event "reset-assert" {
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
$_TARGETNAME configure -event "reset-assert" {
mww 0xB8001010 0x00000304
#--------------------------------------------
mww 0xB8001010 0x00000304
#--------------------------------------------
- # Init 32-bit DDR2 memeory on CSD0
+ # Init 32-bit DDR2 memory on CSD0
# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
#--------------------------------------------
# COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
#--------------------------------------------
- # ESD_ESDCFG0 : set timing paramters
+ # ESD_ESDCFG0 : set timing parameters
mww 0xB8001004 0x007ffC2f
# ESD_ESDCTL0 : select Prechare-All mode
mww 0xB8001004 0x007ffC2f
# ESD_ESDCTL0 : select Prechare-All mode
adapter speed 6000
$_TARGETNAME configure -event "reset-assert" {
adapter speed 6000
$_TARGETNAME configure -event "reset-assert" {
#jtag_ntrst_delay 200
$_TARGETNAME configure -event "reset-assert" {
#jtag_ntrst_delay 200
$_TARGETNAME configure -event "reset-assert" {
# LPDDR1 Initialization script
mww 0xb8001010 0x00000002
mww 0xb8001010 0x00000004
# LPDDR1 Initialization script
mww 0xb8001010 0x00000002
mww 0xb8001010 0x00000004
- # ESDCFG0: set timing paramters
+ # ESDCFG0: set timing parameters
mww 0xb8001004 0x007fff7f
# ESDCTL0: select Prechare-All mode
mww 0xb8001000 0x92100000
mww 0xb8001004 0x007fff7f
# ESDCTL0: select Prechare-All mode
mww 0xb8001000 0x92100000
#
# Sony Ericsson J100I Phone
#
#
# Sony Ericsson J100I Phone
#
-# more informations can be found on
+# more information can be found on
# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
#
source [find target/ti_calypso.cfg]
# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
#
source [find target/ti_calypso.cfg]
-# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
# 5MHz seems to work good with all cores that might happen in 2.x
source [find interface/ftdi/digilent-hs1.cfg]
# 5MHz seems to work good with all cores that might happen in 2.x
-# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
adapter speed 10000
source [find interface/ftdi/digilent-hs1.cfg]
adapter speed 10000
-# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
source [find interface/ftdi/digilent-hs1.cfg]
# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
-# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
source [find interface/ftdi/digilent-hs1.cfg]
# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
source [find interface/ftdi/digilent-hs1.cfg]
# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
# Use for the STM207VG plug-in board (1 MiB Flash and 112+16 KiB Ram
-# comming with the STEVAL-PCC010 board
+# coming with the STEVAL-PCC010 board
# http://www.st.com/internet/evalboard/product/251530.jsp
# or any other board with only a STM32F2x in the JTAG chain
# http://www.st.com/internet/evalboard/product/251530.jsp
# or any other board with only a STM32F2x in the JTAG chain
source [find target/c100.cfg]
source [find target/c100.cfg]
-# basic register defintion for C100
+# basic register definition for C100
source [find target/c100regs.tcl]
# board-config info
source [find target/c100config.tcl]
source [find target/c100regs.tcl]
# board-config info
source [find target/c100config.tcl]
# Init SDRAM
# _PMCDRV = 0x00000071;
# //
# Init SDRAM
# _PMCDRV = 0x00000071;
# //
-# // Initialize SDRAM timing paramater
+# // Initialize SDRAM timing parameter
# //
# _DMC_CAS_LATENCY = 0x00000006;
# _DMC_T_DQSS = 0x00000000;
# //
# _DMC_CAS_LATENCY = 0x00000006;
# _DMC_T_DQSS = 0x00000000;
# Init SDRAM
# _PMCDRV = 0x00000071;
# //
# Init SDRAM
# _PMCDRV = 0x00000071;
# //
-# // Initialize SDRAM timing paramater
+# // Initialize SDRAM timing parameter
# //
# _DMC_CAS_LATENCY = 0x00000006;
# _DMC_T_DQSS = 0x00000000;
# //
# _DMC_CAS_LATENCY = 0x00000006;
# _DMC_T_DQSS = 0x00000000;
source [find target/k60.cfg]
$_TARGETNAME configure -event reset-init {
source [find target/k60.cfg]
$_TARGETNAME configure -event reset-init {
- puts "-event reset-init occured"
+ puts "-event reset-init occurred"
source [find target/k60.cfg]
$_TARGETNAME configure -event reset-init {
source [find target/k60.cfg]
$_TARGETNAME configure -event reset-init {
- puts "-event reset-init occured"
+ puts "-event reset-init occurred"
# voltages. The XADC is available both from fabric as well as through the
# JTAG TAP.
#
# voltages. The XADC is available both from fabric as well as through the
# JTAG TAP.
#
-# This code implements access throught the JTAG TAP.
+# This code implements access through the JTAG TAP.
#
# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
#
# https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf
ftdi_layout_init 0x0030 0x003b
# 0xfff8 0xfffb
# Those signal are only required on some platforms or may required to be
ftdi_layout_init 0x0030 0x003b
# 0xfff8 0xfffb
# Those signal are only required on some platforms or may required to be
-# enabled explicitely (e.g. nrf5x chips).
+# enabled explicitly (e.g. nrf5x chips).
ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020
ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020
-# Give: NAMES - an array of names accessable
+# Give: NAMES - an array of names accessible
# in the callers symbol-scope.
# VAL - the bits to display.
# in the callers symbol-scope.
# VAL - the bits to display.
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
echo "- ERROR: -"
echo "- ERROR: In one position (0x05b0203f) it selects the -"
echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
echo "- ERROR: -"
echo "- ERROR: In one position (0x05b0203f) it selects the -"
echo "- ERROR: ARM CPU, in the other position (0x1b0203f) -"
- echo "- ERROR: it selects boundry-scan not the ARM -"
+ echo "- ERROR: it selects boundary-scan not the ARM -"
echo "- ERROR: -"
echo "-------------------------------------------------------"
}
echo "- ERROR: -"
echo "-------------------------------------------------------"
}
-# board(-config) specfic parameters file.
+# board(-config) specific parameters file.
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
proc config {label} {
echo "12) ooma_board_detect: will show which version of Telo you have"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
echo "14) showDDR2: will show DDR2 config registers"
echo "12) ooma_board_detect: will show which version of Telo you have"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
echo "14) showDDR2: will show DDR2 config registers"
- echo "15) showWatchdog: will show current regster config for watchdog"
+ echo "15) showWatchdog: will show current register config for watchdog"
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
echo "17) bootNOR: will boot Telo from NOR"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
echo "17) bootNOR: will boot Telo from NOR"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
- echo "Wating for Amba PLL to lock"
+ echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
# wait for PLL to lock
- echo "Wating for Amba PLL to lock"
+ echo "Waiting for Amba PLL to lock"
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# Memory setup register
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
# Memory setup register
mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
mmw $BLOCK_RESET_REG $DDR_RST 0x0
mww $MEMORY_CR 0x0
# Take DDR controller out of reset
mmw $BLOCK_RESET_REG $DDR_RST 0x0
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
# allow the counter to count to high value before triggering
- # this is because regsiter writes are slow over JTAG and
+ # this is because register writes are slow over JTAG and
# I don't want to miss the high_bound==curr_count condition
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
# I don't want to miss the high_bound==curr_count condition
mww $TIMER_WDT_HIGH_BOUND 0xffffff
mww $TIMER_WDT_CURRENT_COUNT 0x0
adapter speed 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
adapter speed 100
mww $TIMER_WDT_CONTROL 0x1
# wait until the reset
- echo -n "Wating for watchdog to trigger..."
+ echo -n "Waiting for watchdog to trigger..."
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# sleep 1
#while {[mrw $TIMER_WDT_CONTROL] == 1} {
# echo [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
# sleep 1
target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
# Setup the interesting tap
target create $_TARGETNAME dsp5680xx -endian $_ENDIAN -chain-position $_TARGETNAME
# Setup the interesting tap
-# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations requiere certain instruction to be in the IR register during reset, and polling would change this)
+# Disable polling to be able to get idcode from core tap. If re enabled, can be re enabled, but it should be disabled to correctly unlock flash (operations require certain instruction to be in the IR register during reset, and polling would change this)
jtag configure $_CHIPNAME.chp -event setup "
jtag tapenable $_TARGETNAME
poll off
jtag configure $_CHIPNAME.chp -event setup "
jtag tapenable $_TARGETNAME
poll off
if { [info exists HAS_ETB] } {
} else {
# Set default (no ETB).
if { [info exists HAS_ETB] } {
} else {
# Set default (no ETB).
- # Show a warning, because this should have been configured explicitely.
+ # Show a warning, because this should have been configured explicitly.
set HAS_ETB 0
# TODO: warning?
}
set HAS_ETB 0
# TODO: warning?
}
-# Wired to seperate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
+# Wired to separate STDO pin on the lpc3131, externally muxed to TDO on ea3131 module
# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
if { [info exists SJCTAPID] } {
set _SJCTAPID $SJCTAPID
# JTAGSEL pin must be 0 to activate, which reassigns arm tdo to a pass through.
if { [info exists SJCTAPID] } {
set _SJCTAPID $SJCTAPID
} else {
if {![using_hla]} {
# Tempest and Firestorm default to using NVIC VECTRESET
} else {
if {![using_hla]} {
# Tempest and Firestorm default to using NVIC VECTRESET
- # peripherals will need reseting manually, see proc reset_peripherals
+ # peripherals will need resetting manually, see proc reset_peripherals
cortex_m reset_config vectreset
}
# reset peripherals, based on code in
cortex_m reset_config vectreset
}
# reset peripherals, based on code in
- # Intialize MSP, PSP, and PC from vector table at flash 0x01000800
+ # Initialize MSP, PSP, and PC from vector table at flash 0x01000800
mem2array boot 32 0x01000800 2
reg msp $boot(0)
mem2array boot 32 0x01000800 2
reg msp $boot(0)
-# set default, can be overriden later
+# set default, can be overridden later
adapter speed 1000
proc get_partition { name } {
adapter speed 1000
proc get_partition { name } {
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