target/atsamv: make APCSW cacheable 78/4678/2
authorChristopher Head <chead@zaber.com>
Wed, 19 Sep 2018 23:20:26 +0000 (16:20 -0700)
committerTomas Vanek <vanekt@fbl.cz>
Thu, 27 Sep 2018 15:13:06 +0000 (16:13 +0100)
Change-Id: Ic00d3192642c682f370a6f7f8b70ae29744eb746
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4678
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
tcl/target/atsamv.cfg

index d1f8454..1d026aa 100644 (file)
@@ -50,3 +50,10 @@ if {![using_hla]} {
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME atsamv 0x00400000 0 0 0 $_TARGETNAME
 
+# Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
+# HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
+# makes the data access cacheable. This allows reading and writing data in the
+# CPU cache from the debugger, which is far more useful than going straight to
+# RAM when operating on typical variables, and is generally no worse when
+# operating on special memory locations.
+$_CHIPNAME.dap apcsw 0x08000000 0x08000000