michal smulski <michal.smulski@ooma.com> reset now works

git-svn-id: svn://svn.berlios.de/openocd/trunk@2778 b42882b7-edfa-0310-969c-e2dbd0fdcd60

diff --git a/tcl/board/telo.cfg b/tcl/board/telo.cfg
index a0643f74ae6965a8cd1b4eee111151a59b9afc2b..29066f960668e49fa9e9a3f4fa161ec84a2ec68b 100644 (file)
--- a/tcl/board/telo.cfg
+++ b/tcl/board/telo.cfg
@@ -1,33 +1,34 @@
-source [find target/c100.cfg]
+source [find c100.cfg]

 # basic register defintion for C100
 # basic register defintion for C100

-source [find target/c100regs.tcl]
+source [find c100regs.tcl]

 # board-config info
 # board-config info

-source [find target/c100config.tcl]
+source [find c100config.tcl]

 # C100 helper functions
 # C100 helper functions

-source [find target/c100helper.tcl]
+source [find c100helper.tcl]

 
 
 # Telo board & C100 support trst and srst
 
 
 # Telo board & C100 support trst and srst

-# however openocd does not support
-# 1. setting srst reset pulse width
-# 2. setting delay between srst pulse and JTAG access
-# This really makes the srst useless for now.
+# Note that libftd2xx.so tries to assert srst
+# which break this script
+# use libftdi.so library instead with this script
+# make the reset asserted to 
+# allow RC circuit to discharge for: [ms]
+jtag_nsrst_assert_width 100
+jtag_ntrst_assert_width 100
+# don't talk to JTAG after reset for: [ms]
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100

 reset_config trst_and_srst separate
 
 
 
 reset_config trst_and_srst separate
 
 
 

+

 # issue telnet: reset init
 # issue gdb: monitor reset init
 $_TARGETNAME configure -event reset-init {
        jtag_khz 100
 # issue telnet: reset init
 # issue gdb: monitor reset init
 $_TARGETNAME configure -event reset-init {
        jtag_khz 100

-       # setup GPIO used as control signals for C100
-       setupGPIO
-       # This will allow acces to lower 8MB or NOR
-       lowGPIO5
-       # setup NOR size,timing,etc.
-       setupNOR
-       # setup internals + PLL + DDR2
-       initC100
+       # this will setup Telo board
+       setupTelo

        #turn up the JTAG speed
        jtag_khz 3000
        puts "JTAG speek now 3MHz"
        #turn up the JTAG speed
        jtag_khz 3000
        puts "JTAG speek now 3MHz"


@@ -38,10 +39,15 @@ $_TARGETNAME configure -event reset-deassert-post {
        # Force target into ARM state.
 #      soft_reset_halt # not implemented on ARM11
        puts "Detected SRSRT asserted on C100.CPU"
        # Force target into ARM state.
 #      soft_reset_halt # not implemented on ARM11
        puts "Detected SRSRT asserted on C100.CPU"

+       
+}

 
 

+$_TARGETNAME configure -event reset-assert-post {
+  puts "Assering reset"
+  #sleep 10

 }
 
 }
 

-proc power_restore {} { puts "Sensed power restore. No action." }
+proc power_restore {} { puts "Sensed power restore. No action." } 

 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
 
 
 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
 
 

diff --git a/tcl/target/c100config.tcl b/tcl/target/c100config.tcl
index b25dfd790afc971743845c80927453c36595fd6b..752865e3068243e0b557743a69a7e28ba33d0a9b 100644 (file)
--- a/tcl/target/c100config.tcl
+++ b/tcl/target/c100config.tcl
@@ -3,7 +3,7 @@
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {

-    return [dict get [configC100] $label ]
+    return [dict get [configC100] $label ]     

 }
 
 # show the value for the param. with label
 }
 
 # show the value for the param. with label


@@ -15,7 +15,7 @@ proc showconfig {label} {
 # when there are more then one board config
 # use soft links to c100board-config.tcl
 # so that only the right board-config gets
 # when there are more then one board config
 # use soft links to c100board-config.tcl
 # so that only the right board-config gets

-# included (just like include/configs/board-configs.h
+# included (just like include/configs/board-configs.h 

 # in u-boot.
 proc configC100 {} {
     # xtal freq. 24MHz
 # in u-boot.
 proc configC100 {} {
     # xtal freq. 24MHz


@@ -28,7 +28,7 @@ proc configC100 {} {
     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
     dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
 
     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
     dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
 

-    # Arm Clk 450MHz, must be a multiple of 25 MHz
+    # Arm Clk 450MHz, must be a multiple of 25 MHz 

     dict set configC100 CFG_ARM_CLOCK      450000000
     dict set configC100 w_arm 0
     dict set configC100 x_arm 1
     dict set configC100 CFG_ARM_CLOCK      450000000
     dict set configC100 w_arm 0
     dict set configC100 x_arm 1


@@ -38,20 +38,34 @@ proc configC100 {} {
 
 }
 
 
 }
 

+# This should be called for reset init event handler
+proc setupTelo {} {
+
+    # setup GPIO used as control signals for C100
+    setupGPIO
+    # This will allow acces to lower 8MB or NOR
+    lowGPIO5 
+    # setup NOR size,timing,etc.
+    setupNOR
+    # setup internals + PLL + DDR2
+    initC100
+}
+
+

 proc setupNOR {} {
     puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
 proc setupNOR {} {
     puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()

-    set EX_CSEN_REG        [regs EX_CSEN_REG ]
-    set EX_CS0_SEG_REG     [regs EX_CS0_SEG_REG ]
-    set EX_CS0_CFG_REG     [regs EX_CS0_CFG_REG ]
-    set EX_CS0_TMG1_REG            [regs EX_CS0_TMG1_REG ]
-    set EX_CS0_TMG2_REG            [regs EX_CS0_TMG2_REG ]
-    set EX_CS0_TMG3_REG            [regs EX_CS0_TMG3_REG ]
+    set EX_CSEN_REG        [regs EX_CSEN_REG ] 
+    set EX_CS0_SEG_REG     [regs EX_CS0_SEG_REG ]      
+    set EX_CS0_CFG_REG     [regs EX_CS0_CFG_REG ]      
+    set EX_CS0_TMG1_REG            [regs EX_CS0_TMG1_REG ]     
+    set EX_CS0_TMG2_REG            [regs EX_CS0_TMG2_REG ]     
+    set EX_CS0_TMG3_REG            [regs EX_CS0_TMG3_REG ]     

     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]

-    set EX_MFSM_REG        [regs EX_MFSM_REG ]
-    set EX_CSFSM_REG       [regs EX_CSFSM_REG ]
-    set EX_WRFSM_REG       [regs EX_WRFSM_REG ]
-    set EX_RDFSM_REG       [regs EX_RDFSM_REG ]
+    set EX_MFSM_REG        [regs EX_MFSM_REG ] 
+    set EX_CSFSM_REG       [regs EX_CSFSM_REG ]        
+    set EX_WRFSM_REG       [regs EX_WRFSM_REG ]        
+    set EX_RDFSM_REG       [regs EX_RDFSM_REG ]        

 
     # enable Expansion Bus Clock + CS0 (NOR)
     mww $EX_CSEN_REG 0x3
 
     # enable Expansion Bus Clock + CS0 (NOR)
     mww $EX_CSEN_REG 0x3


@@ -62,7 +76,7 @@ proc setupNOR {} {
     # set timings to NOR
     mww $EX_CS0_TMG1_REG 0x03034006
     mww $EX_CS0_TMG2_REG 0x04040002
     # set timings to NOR
     mww $EX_CS0_TMG1_REG 0x03034006
     mww $EX_CS0_TMG2_REG 0x04040002

-    #mww $EX_CS0_TMG3_REG
+    #mww $EX_CS0_TMG3_REG 

     # set EBUS clock 165/5=33MHz
     mww $EX_CLOCK_DIV_REG 0x5
     # everthing else is OK with default
     # set EBUS clock 165/5=33MHz
     mww $EX_CLOCK_DIV_REG 0x5
     # everthing else is OK with default


@@ -72,7 +86,7 @@ proc bootNOR {} {
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
     set BLOCK_RESET_REG               [regs BLOCK_RESET_REG]
     set DDR_RST                       [regs DDR_RST]
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
     set BLOCK_RESET_REG               [regs BLOCK_RESET_REG]
     set DDR_RST                       [regs DDR_RST]

-
+ 

     # put DDR controller in reset (so that it comes reset in u-boot)
     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
     # setup CS0 controller for NOR
     # put DDR controller in reset (so that it comes reset in u-boot)
     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
     # setup CS0 controller for NOR


@@ -93,8 +107,8 @@ proc setupGPIO {} {
     #GPIO17 reset for DECT module.
     #GPIO29 CS_n for NAND
 
     #GPIO17 reset for DECT module.
     #GPIO29 CS_n for NAND
 

-    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]
-    set GPIO_OE_REG                [regs GPIO_OE_REG]
+    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]      
+    set GPIO_OE_REG                [regs GPIO_OE_REG]  

 
     # set GPIO29=GPIO17=1, GPIO5=0
     mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
 
     # set GPIO29=GPIO17=1, GPIO5=0
     mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]


@@ -104,14 +118,14 @@ proc setupGPIO {} {
 
 proc highGPIO5 {} {
     puts "GPIO5 high"
 
 proc highGPIO5 {} {
     puts "GPIO5 high"

-    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]
+    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]      

     # set GPIO5=1
     mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
 }
 
 proc lowGPIO5 {} {
     puts "GPIO5 low"
     # set GPIO5=1
     mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
 }
 
 proc lowGPIO5 {} {
     puts "GPIO5 low"

-    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]
+    set GPIO_OUTPUT_REG                    [regs GPIO_OUTPUT_REG]      

     # set GPIO5=0
     mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
 }
     # set GPIO5=0
     mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
 }


@@ -119,31 +133,32 @@ proc lowGPIO5 {} {
 proc boardID {id} {
     # so far built:
     # 4'b1111
 proc boardID {id} {
     # so far built:
     # 4'b1111

-    dict set boardID 15 name "EVT1"
+    dict set boardID 15 name "EVT1"            

     dict set boardID 15 ddr2size 128M
     # dict set boardID 15 nandsize 1G
     # dict set boardID 15 norsize 16M
     # 4'b0000
     dict set boardID 15 ddr2size 128M
     # dict set boardID 15 nandsize 1G
     # dict set boardID 15 norsize 16M
     # 4'b0000

-    dict set boardID 0 name "EVT2"
+    dict set boardID 0 name "EVT2"             

     dict set boardID 0 ddr2size 128M
     # 4'b0001
     dict set boardID 0 ddr2size 128M
     # 4'b0001

-    dict set boardID 1 name "EVT3"
+    dict set boardID 1 name "EVT3"             

     dict set boardID 1 ddr2size 256M
     # 4'b1110
     dict set boardID 14 name "EVT3_old"
     dict set boardID 14 ddr2size 128M
     # 4'b0010
     dict set boardID 1 ddr2size 256M
     # 4'b1110
     dict set boardID 14 name "EVT3_old"
     dict set boardID 14 ddr2size 128M
     # 4'b0010

-    dict set boardID 2 name "EVT4"
+    dict set boardID 2 name "EVT4"             

     dict set boardID 2 ddr2size 256M
 
     return $boardID
 }
 
     dict set boardID 2 ddr2size 256M
 
     return $boardID
 }
 

+

 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()

-# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors 

 proc ooma_board_detect {} {
     set GPIO_BOOTSTRAP_REG     [regs GPIO_BOOTSTRAP_REG]
 proc ooma_board_detect {} {
     set GPIO_BOOTSTRAP_REG     [regs GPIO_BOOTSTRAP_REG]

-
+    

     # read the current value of the BOOTSRAP pins
     set tmp [mrw $GPIO_BOOTSTRAP_REG]
     puts [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
     # read the current value of the BOOTSRAP pins
     set tmp [mrw $GPIO_BOOTSTRAP_REG]
     puts [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]


@@ -152,12 +167,77 @@ proc ooma_board_detect {} {
 
     # display board ID
     puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
 
     # display board ID
     puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]

+    # show it on serial console
+    putsUART0 [format "This is %s (0x%x)\n" [dict get [boardID $gpbt] $gpbt name] $gpbt]

     # return the ddr2 size, used to configure DDR2 on a given board.
     return [dict get [boardID $gpbt] $gpbt ddr2size]
 }
 
 proc configureDDR2regs_256M {} {
     # return the ddr2 size, used to configure DDR2 on a given board.
     return [dict get [boardID $gpbt] $gpbt ddr2size]
 }
 
 proc configureDDR2regs_256M {} {

-    puts "ConfigureDDR2regs_256M TBD"
+    
+    set DENALI_CTL_00_DATA    [regs DENALI_CTL_00_DATA]
+    set DENALI_CTL_01_DATA    [regs DENALI_CTL_01_DATA]
+    set DENALI_CTL_02_DATA    [regs DENALI_CTL_02_DATA]
+    set DENALI_CTL_03_DATA    [regs DENALI_CTL_03_DATA]
+    set DENALI_CTL_04_DATA    [regs DENALI_CTL_04_DATA]
+    set DENALI_CTL_05_DATA    [regs DENALI_CTL_05_DATA]
+    set DENALI_CTL_06_DATA    [regs DENALI_CTL_06_DATA]
+    set DENALI_CTL_07_DATA    [regs DENALI_CTL_07_DATA]
+    set DENALI_CTL_08_DATA    [regs DENALI_CTL_08_DATA]
+    set DENALI_CTL_09_DATA    [regs DENALI_CTL_09_DATA]
+    set DENALI_CTL_10_DATA    [regs DENALI_CTL_10_DATA]
+    set DENALI_CTL_11_DATA    [regs DENALI_CTL_11_DATA]
+    set DENALI_CTL_12_DATA    [regs DENALI_CTL_12_DATA]
+    set DENALI_CTL_13_DATA    [regs DENALI_CTL_13_DATA]
+    set DENALI_CTL_14_DATA    [regs DENALI_CTL_14_DATA]
+    set DENALI_CTL_15_DATA    [regs DENALI_CTL_15_DATA]
+    set DENALI_CTL_16_DATA    [regs DENALI_CTL_16_DATA]
+    set DENALI_CTL_17_DATA    [regs DENALI_CTL_17_DATA]
+    set DENALI_CTL_18_DATA    [regs DENALI_CTL_18_DATA]
+    set DENALI_CTL_19_DATA    [regs DENALI_CTL_19_DATA]
+    set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
+
+    set DENALI_CTL_02_VAL 0x0100000000010100
+    set DENALI_CTL_11_VAL 0x433a32164a560a00
+
+    mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
+    # 01_DATA mod [40]=1, enable BA2
+    mw64bit $DENALI_CTL_01_DATA  0x0100010100000001
+    mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
+    mw64bit $DENALI_CTL_03_DATA  0x0102020202020201
+    mw64bit $DENALI_CTL_04_DATA  0x0000010100000001
+    mw64bit $DENALI_CTL_05_DATA  0x0203010300010101
+    mw64bit $DENALI_CTL_06_DATA  0x060a020200020202
+    mw64bit $DENALI_CTL_07_DATA  0x0000000300000206 
+    mw64bit $DENALI_CTL_08_DATA  0x6400003f3f0a0209
+    mw64bit $DENALI_CTL_09_DATA  0x1a000000001a1a1a
+    mw64bit $DENALI_CTL_10_DATA  0x0120202020191a18
+    # 11_DATA mod [39-32]=16,more refresh
+    mw64bit $DENALI_CTL_11_DATA  $DENALI_CTL_11_VAL
+    mw64bit $DENALI_CTL_12_DATA  0x0000000000000800
+    mw64bit $DENALI_CTL_13_DATA  0x0010002000100040
+    mw64bit $DENALI_CTL_14_DATA  0x0010004000100040
+    mw64bit $DENALI_CTL_15_DATA  0x04f8000000000000
+    mw64bit $DENALI_CTL_16_DATA  0x000000002cca0000
+    mw64bit $DENALI_CTL_17_DATA  0x0000000000000000
+    mw64bit $DENALI_CTL_18_DATA  0x0302000000000000
+    mw64bit $DENALI_CTL_19_DATA  0x00001300c8030600
+    mw64bit $DENALI_CTL_20_DATA  0x0000000081fe00c8 
+    
+    set wr_dqs_shift 0x40
+    # start DDRC
+    mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
+    # wait int_status[2] (DRAM init complete)
+    puts -nonewline "Waiting for DDR2 controller to init..."
+    set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+    while { [expr $tmp & 0x040000] == 0 } { 
+       sleep 1
+       set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+    }
+    puts "done."
+
+    # do ddr2 training sequence
+    # TBD (for now, if you need it, run trainDDR command)

 }
 
 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
 }
 
 # converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()


@@ -187,9 +267,9 @@ proc configureDDR2regs_128M {} {
     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 
 
     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 
 

-    set DENALI_CTL_02_VAL 0x0100010000010100
+    set DENALI_CTL_02_VAL 0x0100010000010100 

     set DENALI_CTL_11_VAL 0x433A42124A650A37
     set DENALI_CTL_11_VAL 0x433A42124A650A37

-    # set some default values
+    # set some default values     

     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL


@@ -218,11 +298,12 @@ proc configureDDR2regs_128M {} {
     # wait int_status[2] (DRAM init complete)
     puts -nonewline "Waiting for DDR2 controller to init..."
     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
     # wait int_status[2] (DRAM init complete)
     puts -nonewline "Waiting for DDR2 controller to init..."
     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]

-    while { [expr $tmp & 0x040000] == 0 } {
+    while { [expr $tmp & 0x040000] == 0 } { 

        sleep 1
        set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
     }
        sleep 1
        set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
     }

-   mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
+    # This is not necessary
+    #mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL  & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]

     puts "done."
 
     # do ddr2 training sequence
     puts "done."
 
     # do ddr2 training sequence


@@ -237,18 +318,18 @@ proc setupUART0 {} {
     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]

-    set UART0_LCR                  [regs UART0_LCR]
-    set LCR_DLAB                   [regs LCR_DLAB]
-    set UART0_DLL                  [regs UART0_DLL]
-    set UART0_DLH                  [regs UART0_DLH]
-    set UART0_IIR                  [regs UART0_IIR]
-    set UART0_IER                  [regs UART0_IER]
-    set LCR_ONE_STOP               [regs LCR_ONE_STOP]
-    set LCR_CHAR_LEN_8             [regs LCR_CHAR_LEN_8]
+    set UART0_LCR                  [regs UART0_LCR]    
+    set LCR_DLAB                   [regs LCR_DLAB]     
+    set UART0_DLL                  [regs UART0_DLL]            
+    set UART0_DLH                  [regs UART0_DLH]    
+    set UART0_IIR                  [regs UART0_IIR]    
+    set UART0_IER                  [regs UART0_IER]    
+    set LCR_ONE_STOP               [regs LCR_ONE_STOP]         
+    set LCR_CHAR_LEN_8             [regs LCR_CHAR_LEN_8]               

     set FCR_XMITRES                [regs FCR_XMITRES]
     set FCR_XMITRES                [regs FCR_XMITRES]

-    set FCR_RCVRRES                [regs FCR_RCVRRES]
-    set FCR_FIFOEN                 [regs FCR_FIFOEN]
-    set IER_UUE                            [regs IER_UUE]
+    set FCR_RCVRRES                [regs FCR_RCVRRES]  
+    set FCR_FIFOEN                 [regs FCR_FIFOEN]   
+    set IER_UUE                            [regs IER_UUE]              

 
     # unlock writing to IOCTRL register
     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
 
     # unlock writing to IOCTRL register
     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL


@@ -274,7 +355,7 @@ proc setupUART0 {} {
 
 proc putcUART0 {char} {
 
 
 proc putcUART0 {char} {
 

-    set UART0_LSR          [regs UART0_LSR]
+    set UART0_LSR          [regs UART0_LSR]    

     set UART0_THR          [regs UART0_THR]
     set LSR_TEMT           [regs LSR_TEMT]
 
     set UART0_THR          [regs UART0_THR]
     set LSR_TEMT           [regs LSR_TEMT]
 


@@ -308,17 +389,24 @@ proc trainDDR2 {} {
     resume
 }
 
     resume
 }
 

-proc flashUBOOT {} {
+proc flashUBOOT {file} {

     # this will update uboot on NOR partition
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
     # this will update uboot on NOR partition
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]

-
+    

     # setup CS0 controller for NOR
     setupNOR
     # make sure we are accessing the lower part of NOR
     lowGPIO5
     flash probe 0
     puts "Erasing sectors 0-3 for uboot"
     # setup CS0 controller for NOR
     setupNOR
     # make sure we are accessing the lower part of NOR
     lowGPIO5
     flash probe 0
     puts "Erasing sectors 0-3 for uboot"

+    putsUART0 "Erasing sectors 0-3 for uboot\n"

     flash erase_sector 0 0 3
     flash erase_sector 0 0 3

-    puts "Programming u-boot, takes about 4-5 min for 256kb"
-    flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
+    puts "Programming u-boot"
+    putsUART0 "Programming u-boot..."
+    memwrite burst enable
+    flash write_image $file $EXP_CS0_BASEADDR
+    memwrite burst disable
+    putsUART0 "done.\n"
+    putsUART0 "Rebooting, please wait!\n"
+    reboot

 }
\ No newline at end of file
 }
\ No newline at end of file

diff --git a/tcl/target/telo.cfg b/tcl/target/telo.cfg
index 836b225273b19e0c6c005a5526a0e0dde07cfb8a..29066f960668e49fa9e9a3f4fa161ec84a2ec68b 100644 (file)
--- a/tcl/target/telo.cfg
+++ b/tcl/target/telo.cfg
@@ -1,9 +1,60 @@
 source [find c100.cfg]
 source [find c100.cfg]

+# basic register defintion for C100
+source [find c100regs.tcl]
+# board-config info
+source [find c100config.tcl]
+# C100 helper functions
+source [find c100helper.tcl]
+
+
+# Telo board & C100 support trst and srst
+# Note that libftd2xx.so tries to assert srst
+# which break this script
+# use libftdi.so library instead with this script
+# make the reset asserted to 
+# allow RC circuit to discharge for: [ms]
+jtag_nsrst_assert_width 100
+jtag_ntrst_assert_width 100
+# don't talk to JTAG after reset for: [ms]
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+reset_config trst_and_srst separate
+
+
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+       jtag_khz 100
+       # this will setup Telo board
+       setupTelo
+       #turn up the JTAG speed
+       jtag_khz 3000
+       puts "JTAG speek now 3MHz"
+       puts "type helpC100 to get help on C100"
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+       # Force target into ARM state.
+#      soft_reset_halt # not implemented on ARM11
+       puts "Detected SRSRT asserted on C100.CPU"
+       
+}
+
+$_TARGETNAME configure -event reset-assert-post {
+  puts "Assering reset"
+  #sleep 10
+}
+
+proc power_restore {} { puts "Sensed power restore. No action." } 
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+

 
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus
 
 # boots from NOR on CS0:  8 MBytes CFI flash, 16-bit bus

-# it's really 16MB but the upper 8mb is controller via gpio?
+# it's really 16MB but the upper 8mb is controller via gpio
+# openocd does not support 'complex reads/writes' to NOR

 flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
 
 flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
 

-#
-gdb_memory_map enable
-
+# writing data to memory does not work without this
+memwrite burst disable
\ No newline at end of file