make PXA255 targets enumerate sort-of-OK

Startup now mostly works, except that the initial target state
is "unknown" ... previously, it refused to even start.

Getting that far required fixing the ircapture value (which
can never have been correct!) and the default JTAG clock rate,
then providing custom reset script.

The "reset" command is still iffy.  DCSR updates, and loading
the debug handler, report numerous DR/IR capture failures.
But once that's done, "poll" reports that the CPU is halted
(which it shouldn't be, this was "reset run"!), due to the
rather curious reason "target-not-halted".

Summary:  you still can't debug these parts, but it's closer.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

diff --git a/NEWS b/NEWS
index 7fe542dbe31d6d3597dbc2d7f75c224096b1f507..81fce82181091f9ce3f7a3b03df82cd3b1d3f713 100644 (file)
--- a/NEWS
+++ b/NEWS
@@ -39,6 +39,7 @@ Board, Target, and Interface Configuration Scripts:
     Samsung s3c2450
        Mini2440 board
     Numeric TAP and Target identifiers now trigger warnings
+    PXA255 partially enumerates
 
 Documentation:
     Capture more debugging and setup advice

diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 1608d66c88f2c96b2d33bad8467014ac33ef5f57..7137621a43c87de0ed2daf7ac756286e65d1d26f 100644 (file)
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -19,8 +19,37 @@ if { [info exists CPUTAPID ] } {
    set _CPUTAPID 0x69264013
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e -irmask 0x1f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME
-debug_level 3
+target create $_TARGETNAME xscale -endian $_ENDIAN \
+       -chain-position $_CHIPNAME.cpu
+
+# PXA255 comes out of reset using 3.6864 MHz oscillator.
+# Until the PLL kicks in, keep the JTAG clock slow enough
+# that we get no errors.
+jtag_khz 300
+$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+
+# reset processing that works with PXA
+proc init_reset {mode} {
+       # assert both resets; equivalent to power-on reset
+       jtag_reset 1 1
+
+       # drop TRST after at least 32 cycles
+       sleep 1
+       jtag_reset 0 1
+
+       # minimum 32 TCK cycles to wake up the controller
+       runtest 50
+
+       # now the TAP will be responsive; validate scanchain
+       jtag arp_init
+
+       # ... and take it out of reset
+       jtag_reset 0 0
+}
+
+proc jtag_init {} {
+       init_reset startup
+}