tcl: remove trailing whitespace

The script checkpatch available in new Linux kernel offers an
experimental feature for automatically fix the code in place.
While still experimental, the feature works quite well for simple
fixes, like spacing.

This patch has been created automatically with the script under
review for inclusion in OpenOCD, using the command:
	find tcl/ -type f -exec ./tools/scripts/checkpatch.pl \
	-q --types TRAILING_WHITESPACE --fix-inplace -f {} \;

The patch only changes amount and position of whitespace, thus
the following commands show empty diff
	git diff -w
	git log -w -p
	git log -w --stat

Change-Id: Ie7e3a236f4db9c70019e3b3c7e851edbd3a9dd84
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5616
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
Tested-by: jenkins

diff --git a/tcl/board/at91cap7a-stk-sdram.cfg b/tcl/board/at91cap7a-stk-sdram.cfg
index df91a6b0b0672d43ec80588068830fe03d408d33..8395ba33bcf02f2fba7e54e15df4299008f9edf8 100644 (file)
--- a/tcl/board/at91cap7a-stk-sdram.cfg
+++ b/tcl/board/at91cap7a-stk-sdram.cfg
@@ -43,13 +43,13 @@ proc wait_state {expression} {
                        return
                }
        }
                        return
                }
        }

-       return -code 1 "Timed out"      
+       return -code 1 "Timed out"

 }
 
 # Use a global variable here to be able to tinker interactively with
 # post reset jtag frequency.
 global post_reset_khz
 }
 
 # Use a global variable here to be able to tinker interactively with
 # post reset jtag frequency.
 global post_reset_khz

-# Danger!!!! Even 16MHz kinda works with this target, but 
+# Danger!!!! Even 16MHz kinda works with this target, but

 # it needs to be as low as 2000kHz to be stable.
 set post_reset_khz 2000
 
 # it needs to be as low as 2000kHz to be stable.
 set post_reset_khz 2000
 


@@ -61,25 +61,25 @@ $_TARGETNAME configure -event reset-init {
        mww 0xfffffd08 0xa5000001
        # Enable main oscillator
        mww 0xFFFFFc20  0x00000f01
        mww 0xfffffd08 0xa5000001
        # Enable main oscillator
        mww 0xFFFFFc20  0x00000f01

-       wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}  
+       wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}

 
        # Set PLLA to 96MHz
        mww 0xFFFFFc28 0x20072801
 
        # Set PLLA to 96MHz
        mww 0xFFFFFc28 0x20072801

-       wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}  
+       wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}

 
        # Select prescaler
        mww 0xFFFFFC30 0x00000004
 
        # Select prescaler
        mww 0xFFFFFC30 0x00000004

-       wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+       wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}

 
        # Select master clock to 48MHz
        mww 0xFFFFFC30 0x00000006
 
        # Select master clock to 48MHz
        mww 0xFFFFFC30 0x00000006

-       wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+       wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}

 
        echo "Master clock ok."
 
        echo "Master clock ok."

-       
+

        # Now that we're up and running, crank up speed!
        global post_reset_khz ; adapter speed $post_reset_khz
        # Now that we're up and running, crank up speed!
        global post_reset_khz ; adapter speed $post_reset_khz

-       
+

        echo "Configuring the SDRAM controller..."
 
        # Configure EBI Chip select for SDRAM
        echo "Configuring the SDRAM controller..."
 
        # Configure EBI Chip select for SDRAM


@@ -95,7 +95,7 @@ $_TARGETNAME configure -event reset-init {
 
        # Configure SDRAMC CR
        mww 0xFFFFEA08 0xA63392F9
 
        # Configure SDRAMC CR
        mww 0xFFFFEA08 0xA63392F9

- 
+

        # NOP command
        mww 0xFFFFEA00 0x1
        mww 0x20000000 0
        # NOP command
        mww 0xFFFFEA00 0x1
        mww 0x20000000 0


@@ -151,7 +151,7 @@ $_TARGETNAME configure -event reset-init {
 
        #remap internal memory at address 0x0
        mww 0xffffef00 0x3
 
        #remap internal memory at address 0x0
        mww 0xffffef00 0x3

-       
+

        echo "SDRAM configuration ok."
 }
 
        echo "SDRAM configuration ok."
 }
 

diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg
index 9e0413a1963d4f22ca2827c1959dd2acbf1a3fcd..03296c50e314287b868ed6c2515d82945d843bf7 100644 (file)
--- a/tcl/board/at91sam9g20-ek.cfg
+++ b/tcl/board/at91sam9g20-ek.cfg
@@ -139,13 +139,13 @@ proc at91sam9g20_reset_init { } {
        # (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
        # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
        # is a little tedious to do here.  If you have questions about how to do this, Atmel has
        # (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
        # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
        # is a little tedious to do here.  If you have questions about how to do this, Atmel has

-       # a decent application note #6255B that covers this process. 
+       # a decent application note #6255B that covers this process.

 
        mww 0xffffec30 0x00020002       ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
        mww 0xffffec34 0x04040404       ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
        mww 0xffffec38 0x00070006       ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
 
        mww 0xffffec30 0x00020002       ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
        mww 0xffffec34 0x04040404       ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
        mww 0xffffec38 0x00070006       ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle

-       mww 0xffffec3C 0x00020003       ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
-   
+       mww 0xffffec3C 0x00020003       ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+

        mww 0xffffe800 0x00000001       ;# ECC_CR : reset the ECC parity registers
        mww 0xffffe804 0x00000002       ;# ECC_MR : page size is 2112 words (word is 8 bits)
 
        mww 0xffffe800 0x00000001       ;# ECC_CR : reset the ECC parity registers
        mww 0xffffe804 0x00000002       ;# ECC_MR : page size is 2112 words (word is 8 bits)
 

diff --git a/tcl/board/hilscher_nxdb500sys.cfg b/tcl/board/hilscher_nxdb500sys.cfg
index d71c4453b541668751afa4c0fea07bb80d91fa76..20fa3ea0334d6aca6fe5f6a110f33e296fdd7bf1 100644 (file)
--- a/tcl/board/hilscher_nxdb500sys.cfg
+++ b/tcl/board/hilscher_nxdb500sys.cfg
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
   arm7_9 dcc_downloads enable
 
   sdram_fix

-  
+

   puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C13261
   puts "Configuring SDRAM controller for paired K4S561632C (64MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C13261

diff --git a/tcl/board/hilscher_nxeb500hmi.cfg b/tcl/board/hilscher_nxeb500hmi.cfg
index aa3d58701ce839f9931ea4a3ac8f4a0dac0f069e..a51fa03bcf513a33f9385d043332c5d25ed84c6a 100644 (file)
--- a/tcl/board/hilscher_nxeb500hmi.cfg
+++ b/tcl/board/hilscher_nxeb500hmi.cfg
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads disable
 
   sdram_fix
   arm7_9 dcc_downloads disable
 
   sdram_fix

-  
+

   puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
   puts "Configuring SDRAM controller for MT48LC8M32 (32MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251

diff --git a/tcl/board/hilscher_nxsb100.cfg b/tcl/board/hilscher_nxsb100.cfg
index 807e29200c4967f7cdee6cf589edf1ad75c7122a..c332beec0fdd30e273f75e717ecaa4391b49cfb6 100644 (file)
--- a/tcl/board/hilscher_nxsb100.cfg
+++ b/tcl/board/hilscher_nxsb100.cfg
@@ -17,7 +17,7 @@ $_TARGETNAME configure -event reset-init {
   arm7_9 dcc_downloads enable
 
   sdram_fix
   arm7_9 dcc_downloads enable
 
   sdram_fix

-  
+

   puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251
   puts "Configuring SDRAM controller for MT48LC2M32 (8MB) "
   mww 0x00100140 0
   mww 0x00100144 0x03C23251

diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index 502d4077430955983a244c08f224c83fe5d0a613..2dce157dbc72fb91db28cc2a2bfdf43bc5100bf5 100644 (file)
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -28,36 +28,36 @@ proc imx31pdk_init { } {
 
        mww 0x53FC0000 0x040
        mww 0x53F80000 0x074B0B7D
 
        mww 0x53FC0000 0x040
        mww 0x53F80000 0x074B0B7D

-       
+

        # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
        #mww 0x53F80004 0xFF871D50
        #mww 0x53F80010 0x00271C1B
        # 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
        #mww 0x53F80004 0xFF871D50
        #mww 0x53F80010 0x00271C1B

-       
+

        # Start 16 bit NorFlash Initialization on CS0
        mww 0xb8002000 0x0000CC03
        mww 0xb8002004 0xa0330D01
        mww 0xb8002008 0x00220800
        # Start 16 bit NorFlash Initialization on CS0
        mww 0xb8002000 0x0000CC03
        mww 0xb8002004 0xa0330D01
        mww 0xb8002008 0x00220800

-       
+

        # Configure CPLD on CS4
        mww 0xb8002040 0x0000DCF6
        mww 0xb8002044 0x444A4541
        mww 0xb8002048 0x44443302
        # Configure CPLD on CS4
        mww 0xb8002040 0x0000DCF6
        mww 0xb8002044 0x444A4541
        mww 0xb8002048 0x44443302

-       
+

        # SDCLK
        mww 0x43FAC26C 0
        # SDCLK
        mww 0x43FAC26C 0

-       
+

        # CAS
        mww 0x43FAC270 0
        # CAS
        mww 0x43FAC270 0

-       
+

        # RAS
        mww 0x43FAC274 0
        # RAS
        mww 0x43FAC274 0

-       
+

        # CS2 (CSD0)
        mww 0x43FAC27C 0x1000
        # CS2 (CSD0)
        mww 0x43FAC27C 0x1000

-       
+

        # DQM3
        mww 0x43FAC284 0
        # DQM3
        mww 0x43FAC284 0

-       
+

        # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
        mww 0x43FAC288 0
        mww 0x43FAC28C 0
        # DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
        mww 0x43FAC288 0
        mww 0x43FAC28C 0


@@ -81,7 +81,7 @@ proc imx31pdk_init { } {
        mww 0x43FAC2D4 0
        mww 0x43FAC2D8 0
        mww 0x43FAC2DC 0
        mww 0x43FAC2D4 0
        mww 0x43FAC2D8 0
        mww 0x43FAC2DC 0

-       
+

        # Initialization script for 32 bit DDR on MX31 ADS
        mww 0xB8001010 0x00000004
        mww 0xB8001004 0x006ac73a
        # Initialization script for 32 bit DDR on MX31 ADS
        mww 0xB8001010 0x00000004
        mww 0xB8001004 0x006ac73a

diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index b81c0b01cc2a3a715e0ea7af0e8e56eed1cd71ea..2a7efaba7ef82a73951c47f9a051c51e361f36bf 100644 (file)
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -8,9 +8,9 @@ $_TARGETNAME configure -event reset-init { imx35pdk_init }
 jtag_rclk 10
 
 proc imx35pdk_init { } {
 jtag_rclk 10
 
 proc imx35pdk_init { } {

-       
+

        imx3x_reset
        imx3x_reset

-       
+

        mww 0x43f00040 0x00000000
        mww 0x43f00044 0x00000000
        mww 0x43f00048 0x00000000
        mww 0x43f00040 0x00000000
        mww 0x43f00044 0x00000000
        mww 0x43f00048 0x00000000


@@ -25,11 +25,11 @@ proc imx35pdk_init { } {
        mww 0x53f00050 0x00000000
        mww 0x53f00000 0x77777777
        mww 0x53f00004 0x77777777
        mww 0x53f00050 0x00000000
        mww 0x53f00000 0x77777777
        mww 0x53f00004 0x77777777

-       
+

        # clock setup
        mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
        mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.
        # clock setup
        mww 0x53F80004 0x00821000 ;# first need to set IPU_HND_BYP
        mww 0x53F80004 0x00821000 ;#arm clock is 399Mhz and ahb clock is 133Mhz.

-       
+

        #=================================================
        # WEIM config
        #=================================================
        #=================================================
        # WEIM config
        #=================================================


@@ -45,14 +45,14 @@ proc imx35pdk_init { } {
        mww 0xB8002054 0x444a4541
        # CS5A
        mww 0xB8002058 0x44443302
        mww 0xB8002054 0x444a4541
        # CS5A
        mww 0xB8002058 0x44443302

-       
+

        # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
        mww 0x43FAC368 0x00000006
        mww 0x43FAC36C 0x00000006
        mww 0x43FAC370 0x00000006
        mww 0x43FAC374 0x00000006
        mww 0x43FAC378 0x00000006
        # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
        mww 0x43FAC368 0x00000006
        mww 0x43FAC36C 0x00000006
        mww 0x43FAC370 0x00000006
        mww 0x43FAC374 0x00000006
        mww 0x43FAC378 0x00000006

-       mww 0x43FAC37C 0x00000006       
+       mww 0x43FAC37C 0x00000006

        mww 0x43FAC380 0x00000006
        mww 0x43FAC384 0x00000006
        mww 0x43FAC388 0x00000006
        mww 0x43FAC380 0x00000006
        mww 0x43FAC384 0x00000006
        mww 0x43FAC388 0x00000006


@@ -76,7 +76,7 @@ proc imx35pdk_init { } {
        mww 0x43FAC3D0 0x00000006
        mww 0x43FAC3D4 0x00000006
        mww 0x43FAC3D8 0x00000006
        mww 0x43FAC3D0 0x00000006
        mww 0x43FAC3D4 0x00000006
        mww 0x43FAC3D8 0x00000006

-       
+

        # DDR data bus SD 0 through 31
        mww 0x43FAC3DC 0x00000082
        mww 0x43FAC3E0 0x00000082
        # DDR data bus SD 0 through 31
        mww 0x43FAC3DC 0x00000082
        mww 0x43FAC3E0 0x00000082


@@ -110,13 +110,13 @@ proc imx35pdk_init { } {
        mww 0x43FAC450 0x00000082
        mww 0x43FAC454 0x00000082
        mww 0x43FAC458 0x00000082
        mww 0x43FAC450 0x00000082
        mww 0x43FAC454 0x00000082
        mww 0x43FAC458 0x00000082

-       
+

        # DQM setup
        mww 0x43FAC45c 0x00000082
        mww 0x43FAC460 0x00000082
        mww 0x43FAC464 0x00000082
        mww 0x43FAC468 0x00000082
        # DQM setup
        mww 0x43FAC45c 0x00000082
        mww 0x43FAC460 0x00000082
        mww 0x43FAC464 0x00000082
        mww 0x43FAC468 0x00000082

-       
+

        mww 0x43FAC46c 0x00000006
        mww 0x43FAC470 0x00000006
        mww 0x43FAC474 0x00000006
        mww 0x43FAC46c 0x00000006
        mww 0x43FAC470 0x00000006
        mww 0x43FAC474 0x00000006


@@ -130,30 +130,30 @@ proc imx35pdk_init { } {
        mww 0x43FAC494 0x00000006
        mww 0x43FAC498 0x00000006
        mww 0x43FAC49c 0x00000006
        mww 0x43FAC494 0x00000006
        mww 0x43FAC498 0x00000006
        mww 0x43FAC49c 0x00000006

-       mww 0x43FAC4A0 0x00000006       
+       mww 0x43FAC4A0 0x00000006

        mww 0x43FAC4A4 0x00000006       ;# RAS
        mww 0x43FAC4A8 0x00000006       ;# CAS
        mww 0x43FAC4Ac 0x00000006       ;# SDWE
        mww 0x43FAC4B0 0x00000006       ;# SDCKE0
        mww 0x43FAC4B4 0x00000006  ;# SDCKE1
        mww 0x43FAC4B8 0x00000002  ;# SDCLK
        mww 0x43FAC4A4 0x00000006       ;# RAS
        mww 0x43FAC4A8 0x00000006       ;# CAS
        mww 0x43FAC4Ac 0x00000006       ;# SDWE
        mww 0x43FAC4B0 0x00000006       ;# SDCKE0
        mww 0x43FAC4B4 0x00000006  ;# SDCKE1
        mww 0x43FAC4B8 0x00000002  ;# SDCLK

-       
+

        # SDQS0 through SDQS3
        mww 0x43FAC4Bc 0x00000082
        mww 0x43FAC4C0 0x00000082
        mww 0x43FAC4C4 0x00000082
        mww 0x43FAC4C8 0x00000082
        # SDQS0 through SDQS3
        mww 0x43FAC4Bc 0x00000082
        mww 0x43FAC4C0 0x00000082
        mww 0x43FAC4C4 0x00000082
        mww 0x43FAC4C8 0x00000082

-       
-       
+
+

        # *==================================================
        #  Initialization script for 32 bit DDR2 on RINGO 3DS
        # *==================================================
        # *==================================================
        #  Initialization script for 32 bit DDR2 on RINGO 3DS
        # *==================================================

-       
+

        #--------------------------------------------
        # Init CCM
        #--------------------------------------------
        mww 0x53F80028 0x7D000028
        #--------------------------------------------
        # Init CCM
        #--------------------------------------------
        mww 0x53F80028 0x7D000028

-       
+

        #--------------------------------------------
        # Init IOMUX for JTAG
        #--------------------------------------------
        #--------------------------------------------
        # Init IOMUX for JTAG
        #--------------------------------------------


@@ -164,24 +164,24 @@ proc imx35pdk_init { } {
        mww 0x43FAC5FC 0x000000F3
        mww 0x43FAC600 0x000000F3
        mww 0x43FAC604 0x000000F3
        mww 0x43FAC5FC 0x000000F3
        mww 0x43FAC600 0x000000F3
        mww 0x43FAC604 0x000000F3

-       
-       
+
+

        # ESD_MISC : enable DDR2
        mww 0xB8001010 0x00000304
        # ESD_MISC : enable DDR2
        mww 0xB8001010 0x00000304

-       
+

        #--------------------------------------------
        # Init 32-bit DDR2 memory on CSD0
        # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
        #--------------------------------------------
        #--------------------------------------------
        # Init 32-bit DDR2 memory on CSD0
        # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
        #--------------------------------------------

-       
+

        # ESD_ESDCFG0 : set timing parameters
        # ESD_ESDCFG0 : set timing parameters

-       mww 0xB8001004 0x007ffC2f       
-       
+       mww 0xB8001004 0x007ffC2f
+

        # ESD_ESDCTL0 : select Prechare-All mode
        mww 0xB8001000 0x92220000
        # DDR2 : Prechare-All
        mww 0x80000400 0x12345678
        # ESD_ESDCTL0 : select Prechare-All mode
        mww 0xB8001000 0x92220000
        # DDR2 : Prechare-All
        mww 0x80000400 0x12345678

-       
+

        # ESD_ESDCTL0 : select Load-Mode-Register mode
        mww 0xB8001000 0xB2220000
        # DDR2 : Load reg EMR2
        # ESD_ESDCTL0 : select Load-Mode-Register mode
        mww 0xB8001000 0xB2220000
        # DDR2 : Load reg EMR2


@@ -192,18 +192,18 @@ proc imx35pdk_init { } {
        mwb 0x82000400 0xda
        # DDR2 : Load reg MR -- reset DLL
        mwb 0x80000333 0xda
        mwb 0x82000400 0xda
        # DDR2 : Load reg MR -- reset DLL
        mwb 0x80000333 0xda

-       
+

        # ESD_ESDCTL0 : select Prechare-All mode
        mww 0xB8001000 0x92220000
        # DDR2 : Prechare-All
        mwb 0x80000400 0x12345678
        # ESD_ESDCTL0 : select Prechare-All mode
        mww 0xB8001000 0x92220000
        # DDR2 : Prechare-All
        mwb 0x80000400 0x12345678

-       
+

        # ESD_ESDCTL0 : select Manual-Refresh mode
        mww 0xB8001000 0xA2220000
        # DDR2 : Manual-Refresh 2 times
        mww 0x80000000 0x87654321
        mww 0x80000000 0x87654321
        # ESD_ESDCTL0 : select Manual-Refresh mode
        mww 0xB8001000 0xA2220000
        # DDR2 : Manual-Refresh 2 times
        mww 0x80000000 0x87654321
        mww 0x80000000 0x87654321

-       
+

        # ESD_ESDCTL0 : select Load-Mode-Register mode
        mww 0xB8001000 0xB2220000
        # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
        # ESD_ESDCTL0 : select Load-Mode-Register mode
        mww 0xB8001000 0xB2220000
        # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset


@@ -212,19 +212,19 @@ proc imx35pdk_init { } {
        mwb 0x82000780 0xda
        # DDR2 : Load reg EMR1 -- OCD exit
        mwb 0x82000400 0xda     ;# ODT disabled
        mwb 0x82000780 0xda
        # DDR2 : Load reg EMR1 -- OCD exit
        mwb 0x82000400 0xda     ;# ODT disabled

-       
+

        # ESD_ESDCTL0 : select normal-operation mode
        # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
        # disable PWT & PRCT
        # disable Auto-Refresh
        mww 0xB8001000 0x82220080
        # ESD_ESDCTL0 : select normal-operation mode
        # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
        # disable PWT & PRCT
        # disable Auto-Refresh
        mww 0xB8001000 0x82220080

-       
+

        ## ESD_ESDCTL0 : enable Auto-Refresh
        mww 0xB8001000 0x82228080
        ## ESD_ESDCTL1 : enable Auto-Refresh
        mww 0xB8001008 0x00002000
        ## ESD_ESDCTL0 : enable Auto-Refresh
        mww 0xB8001000 0x82228080
        ## ESD_ESDCTL1 : enable Auto-Refresh
        mww 0xB8001008 0x00002000

-       
-       
+
+

        #***********************************************
        # Adjust the ESDCDLY5 register
        #***********************************************
        #***********************************************
        # Adjust the ESDCDLY5 register
        #***********************************************


@@ -233,20 +233,20 @@ proc imx35pdk_init { } {
        mww 0xB8001024 0x00F48000       ;# this is the default value
        mww 0xB8001028 0x00F48000       ;# this is the default value
        mww 0xB800102c 0x00F48000       ;# this is the default value
        mww 0xB8001024 0x00F48000       ;# this is the default value
        mww 0xB8001028 0x00F48000       ;# this is the default value
        mww 0xB800102c 0x00F48000       ;# this is the default value

-       
-       
+
+

        #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
        mww 0xB8001010 0x00000384
        # wait a while
        sleep 1000
        # now clear the force measurement bit
        mww 0xB8001010 0x00000304
        #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
        mww 0xB8001010 0x00000384
        # wait a while
        sleep 1000
        # now clear the force measurement bit
        mww 0xB8001010 0x00000304

-       
+

        # dummy write to DDR memory to set DQS low
        mww 0x80000000 0x00000000
        # dummy write to DDR memory to set DQS low
        mww 0x80000000 0x00000000

-       
+

        mww 0x30000100 0x0
        mww 0x30000104 0x31024
        mww 0x30000100 0x0
        mww 0x30000104 0x31024

-       
-       
+
+

 }
 }

diff --git a/tcl/board/mcb1700.cfg b/tcl/board/mcb1700.cfg
index 4954dab0a1e3f9d90d7b4276b31e7086eac329d9..01080a0b16b560c9815aed45efc02cfee475fe65 100644 (file)
--- a/tcl/board/mcb1700.cfg
+++ b/tcl/board/mcb1700.cfg
@@ -1,5 +1,5 @@
 # Keil MCB1700 PCB with 1768
 # Keil MCB1700 PCB with 1768

-# 
+#

 # Reset init script sets it to 100MHz
 set CCLK 100000
 
 # Reset init script sets it to 100MHz
 set CCLK 100000
 


@@ -53,7 +53,7 @@ $_TARGETNAME configure -event reset-init {
 
        # Dividing CPU clock by 8 should be pretty conservative
        #
 
        # Dividing CPU clock by 8 should be pretty conservative
        #

-       # 
+       #

        global MCB1700_CCLK
        adapter speed [expr $MCB1700_CCLK / 8]
 
        global MCB1700_CCLK
        adapter speed [expr $MCB1700_CCLK / 8]
 

diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index ad2f850a116dbf4d7d250dc2a1b8b673c9fdd81f..72dce87b1c2d8ecdb57d66a6bfa704b1070940d1 100644 (file)
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -23,15 +23,15 @@ $_TARGETNAME configure -event reset-start {
        # RCLK is not supported.
        jtag_rclk 5
        halt
        # RCLK is not supported.
        jtag_rclk 5
        halt

-       
-       # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may 
+
+       # RSTC_MR : enable user reset, reset length is 64 slow clock cycles.  MMU may

        # be enabled... use physical address.
        mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {
        mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
        # be enabled... use physical address.
        mww phys 0xfffffd08 0xa5000501
 }
 
 $_TARGETNAME configure -event reset-init {
        mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog

-       
+

        ##
        # Clock configuration for 99.328 MHz main clock.
        ##
        ##
        # Clock configuration for 99.328 MHz main clock.
        ##


@@ -45,23 +45,23 @@ $_TARGETNAME configure -event reset-init {
        mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
        sleep 10                  ;# wait 10 ms
        mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)
        mww 0xfffffc30 0x00000101 ;# PMC_MCKR : no scale on proc clock, master is proc / 2
        sleep 10                  ;# wait 10 ms
        mww 0xfffffc30 0x00000102 ;# PMC_MCKR : switch to PLLA (99.328 MHz)

-       
+

        # Increase JTAG speed to 6 MHz if RCLK is not supported.
        jtag_rclk 6000
        # Increase JTAG speed to 6 MHz if RCLK is not supported.
        jtag_rclk 6000

-       
+

        arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.
        arm7_9 dcc_downloads enable ;# Enable faster DCC downloads.

-       
+

        ##
        # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
        ##
     echo "Configuring SDRAM"
        mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
        mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31
        ##
        # SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
        ##
     echo "Configuring SDRAM"
        mww 0xfffff870 0xffff0000 ;# PIOC_ASR : select peripheral function for D15..D31
        mww 0xfffff804 0xffff0000 ;# PIOC_PDR : disable PIO function for D15..D31

-       
+

        mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory
        mww 0xffffef1c 0x00010002 ;# EBI_CSA : assign EBI CS1 to SDRAM, VDDIOMSEL set for +3V3 memory

-       
+

        mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips
        mww 0xffffea08 0x85237259 ;# SDRAMC_CR : configure SDRAM for Samsung chips

-       
+

        mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
        mww 0x20000000 0
        mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command
        mww 0xffffea00 0x1        ;# SDRAMC_MR : issue NOP command
        mww 0x20000000 0
        mww 0xffffea00 0x2        ;# SDRAMC_MR : issue an 'All Banks Precharge' command


@@ -86,7 +86,7 @@ $_TARGETNAME configure -event reset-init {
        mww 0x20000000 0
        mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
        mww 0x20000000 0
        mww 0x20000000 0
        mww 0xffffea00 0x0        ;# SDRAMC_MR : normal mode
        mww 0x20000000 0

-       
+

        mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
 
     ##
        mww 0xffffea04 0x2b6      ;# SDRAMC_TR : set refresh timer count to 7 us
 
     ##


@@ -99,37 +99,37 @@ $_TARGETNAME configure -event reset-init {
     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
     mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
     mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
     mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13

-    
+

     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
     mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before

-    
+

     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
     mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
     mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
     mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle

-    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
+    mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,

                                #             3 TDF cycles, no optimization
                                #             3 TDF cycles, no optimization

-    
+

     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
     mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
     mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)

-    
+

     nand probe at91sam9260.flash
     nand probe at91sam9260.flash

-    
+

     ##
     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
     ##
     echo "Setting up dataflash"
     ##
     # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
     ##
     echo "Setting up dataflash"

-    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI), 
+    mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),

                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
                                #            2(SPI0_SPCK), and 11(SPI0_NPCS1)
     mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
     mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
     mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock

-    
+

     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
     mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
     mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected

-    
-    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud, 
+
+    mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,

                                #             250ns delay before SPCK, 250ns b/n tx
                                #             250ns delay before SPCK, 250ns b/n tx

-    
+

     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 }
     mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
     mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
 }

diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
index 1c48f5df7072b137b098014ca079d3cd74882469..cee28cdd26552cd49b0d6d33cca91a621ad4e9bf 100644 (file)
--- a/tcl/board/phytec_lpc3250.cfg
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -23,12 +23,12 @@ $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {
 
 # Bare-bones initialization of core clocks and SDRAM
 proc phytec_lpc3250_init { } {

-        # Set clock dividers 
+        # Set clock dividers

         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0
         #   ARMCLK = 266.5 MHz
         #   HCLK   = 133.25 MHz
         #   PERIPHCLK = 13.325 MHz
         mww 0x400040BC 0

-        mww 0x40004050 0x140        
+        mww 0x40004050 0x140

         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 
         mww 0x40004040 0x4D
         mww 0x40004058 0x16250
 


@@ -37,7 +37,7 @@ proc phytec_lpc3250_init { } {
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy
         sleep 1 busy
         mww 0x40004044 0x106
         sleep 1 busy

-        mww 0x40004044 0x006        
+        mww 0x40004044 0x006

         sleep 1 busy
         mww 0x40004048 0x2
 
         sleep 1 busy
         mww 0x40004048 0x2
 


@@ -49,7 +49,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11
         mww 0x31080008 0
         mww 0x40004068 0x1C000
         mww 0x31080028 0x11

-        
+

         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0
         mww 0x31080400 0
         mww 0x31080440 0
         mww 0x31080460 0


@@ -66,7 +66,7 @@ proc phytec_lpc3250_init { } {
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0
         mww 0x31080054 1
         mww 0x31080058 1
         mww 0x3108005C 0

-        
+

         mww 0x31080100 0x5680
         mww 0x31080104 0x302
 
         mww 0x31080100 0x5680
         mww 0x31080104 0x302
 

diff --git a/tcl/board/rsc-w910.cfg b/tcl/board/rsc-w910.cfg
index cb1733b278d346754f1f6d6bf7f0e621f576497a..574de0c0761e5e8d10add8583fb127d7c2f99174 100644 (file)
--- a/tcl/board/rsc-w910.cfg
+++ b/tcl/board/rsc-w910.cfg
@@ -33,7 +33,7 @@ $_TARGETNAME configure -event reset-start {adapter speed 1000}
 $_TARGETNAME configure -event reset-init {
        # switch on PLL for 200MHz operation
        # running from 15MHz input clock
 $_TARGETNAME configure -event reset-init {
        # switch on PLL for 200MHz operation
        # running from 15MHz input clock

-       
+

        mww 0xB0000200 0x00000030 ;# CLKEN
        mww 0xB0000204 0x00000f3c ;# CLKSEL
        mww 0xB0000208 0x05007000 ;# CLKDIV
        mww 0xB0000200 0x00000030 ;# CLKEN
        mww 0xB0000204 0x00000f3c ;# CLKSEL
        mww 0xB0000208 0x05007000 ;# CLKDIV


@@ -41,17 +41,17 @@ $_TARGETNAME configure -event reset-init {
        mww 0xB0000210 0x00002b63 ;# PLLCON1
        mww 0xB000000C 0x08817fa6 ;# MFSEL
        sleep 10
        mww 0xB0000210 0x00002b63 ;# PLLCON1
        mww 0xB000000C 0x08817fa6 ;# MFSEL
        sleep 10

-       
+

        # we are now running @ 200MHz
        # enable all openocd speed tweaks
        # we are now running @ 200MHz
        # enable all openocd speed tweaks

-       
+

        arm7_9 dcc_downloads enable
        arm7_9 fast_memory_access enable
        adapter speed 15000
        arm7_9 dcc_downloads enable
        arm7_9 fast_memory_access enable
        adapter speed 15000

-       
+

        # map nor flash to 0x20000000
        # map sdram to 0x00000000
        # map nor flash to 0x20000000
        # map sdram to 0x00000000

-       
+

        mww 0xb0001000 0x000530c1 ;# EBICON
        mww 0xb0001004 0x40030084 ;# ROMCON
        mww 0xb0001008 0x000010ee ;# SDCONF0
        mww 0xb0001000 0x000530c1 ;# EBICON
        mww 0xb0001004 0x40030084 ;# ROMCON
        mww 0xb0001008 0x000010ee ;# SDCONF0

diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg
index 91807ce3094906861e6bb70d5d4b2ee4a573f1d2..f30253c1166ee231c0670376a58bce6019d14198 100644 (file)
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -17,11 +17,11 @@ flash bank $_FLASHNAME cfi 0x64000000 0x01000000 2 2 $_TARGETNAME
 proc stm32_enable_fsmc {} {
 
        echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"
 proc stm32_enable_fsmc {} {
 
        echo "Enabling FSMC Bank 1 (NOR/PSRAM Bank 2)"

-       
+

        # enable gpio (defg) clocks for fsmc
        # RCC_APB2ENR
        mww 0x40021018 0x000001E0
        # enable gpio (defg) clocks for fsmc
        # RCC_APB2ENR
        mww 0x40021018 0x000001E0

-       
+

        # enable fsmc clock
        # RCC_AHBENR
        mww 0x40021014 0x00000114
        # enable fsmc clock
        # RCC_AHBENR
        mww 0x40021014 0x00000114


@@ -31,29 +31,29 @@ proc stm32_enable_fsmc {} {
        mww 0x40011400 0x44BB44BB
        # GPIOD_CRH
        mww 0x40011404 0xBBBBBBBB
        mww 0x40011400 0x44BB44BB
        # GPIOD_CRH
        mww 0x40011404 0xBBBBBBBB

-       
+

        # GPIOE_CRL
        mww 0x40011800 0xBBBBB444
        # GPIOE_CRH
        mww 0x40011804 0xBBBBBBBB
        # GPIOE_CRL
        mww 0x40011800 0xBBBBB444
        # GPIOE_CRH
        mww 0x40011804 0xBBBBBBBB

-       
+

        # GPIOF_CRL
        mww 0x40011C00 0x44BBBBBB
        # GPIOF_CRH
        mww 0x40011C04 0xBBBB4444
        # GPIOF_CRL
        mww 0x40011C00 0x44BBBBBB
        # GPIOF_CRH
        mww 0x40011C04 0xBBBB4444

-       
+

        # GPIOG_CRL
        mww 0x40012000 0x44BBBBBB
        # GPIOG_CRH
        mww 0x40012004 0x444444B4
        # GPIOG_CRL
        mww 0x40012000 0x44BBBBBB
        # GPIOG_CRH
        mww 0x40012004 0x444444B4

-       
+

        # setup fsmc timings
        # FSMC_BCR1
        mww 0xA0000008 0x00001058
        # setup fsmc timings
        # FSMC_BCR1
        mww 0xA0000008 0x00001058

-       
+

        # FSMC_BTR1
        mww 0xA000000C 0x10000502
        # FSMC_BTR1
        mww 0xA000000C 0x10000502

-       
+

        # FSMC_BCR1 - enable fsmc
        mww 0xA0000008 0x00001059
 }
        # FSMC_BCR1 - enable fsmc
        mww 0xA0000008 0x00001059
 }

diff --git a/tcl/board/uptech_2410.cfg b/tcl/board/uptech_2410.cfg
index 680cfd7d60419ba1eb8896b2c3c146081f755cd0..227cf42f6b355fa6664ad93e55a6395d655525e5 100644 (file)
--- a/tcl/board/uptech_2410.cfg
+++ b/tcl/board/uptech_2410.cfg
@@ -11,28 +11,28 @@ proc init_pll_sdram { } {
        #echo "---------- Initializing PLL and SDRAM ---------"
        #watchdog timer disable
        mww phys 0x53000000 0x00000000
        #echo "---------- Initializing PLL and SDRAM ---------"
        #watchdog timer disable
        mww phys 0x53000000 0x00000000

-       
+

        #disable all interrupts
        mww phys 0x4a000008 0xffffffff
        #disable all interrupts
        mww phys 0x4a000008 0xffffffff

-       
+

        #disable all sub-interrupts
        mww phys 0x4a00001c 0x000007ff
        #disable all sub-interrupts
        mww phys 0x4a00001c 0x000007ff

-       
+

        #clear all source pending bits
        mww phys 0x4a000000 0xffffffff
        #clear all source pending bits
        mww phys 0x4a000000 0xffffffff

-       
+

        #clear all sub-source pending bits
        mww phys 0x4a000018 0x000007ff
        #clear all sub-source pending bits
        mww phys 0x4a000018 0x000007ff

-       
+

        #clear interrupt pending bit
        mww phys 0x4a000010 0xffffffff
        #clear interrupt pending bit
        mww phys 0x4a000010 0xffffffff

-       
+

        #PLL locktime counter
        mww phys 0x4c000000 0x00ffffff
        #PLL locktime counter
        mww phys 0x4c000000 0x00ffffff

-       
+

        #Fin=12MHz Fout=202.8MHz
        #mww phys 0x4c000004 0x000a1031
        #Fin=12MHz Fout=202.8MHz
        #mww phys 0x4c000004 0x000a1031

-       
+

        #FCLK:HCLK:PCLK = 1:2:4
        mww phys 0x4c000014 0x00000003
 
        #FCLK:HCLK:PCLK = 1:2:4
        mww phys 0x4c000014 0x00000003
 

diff --git a/tcl/target/dsp56321.cfg b/tcl/target/dsp56321.cfg
index 0ac0ce87c83bf0a16971ef65921510185cbe6f1d..78ecb3bd2473ff23924e75b14eb268ed63f0fc51 100644 (file)
--- a/tcl/target/dsp56321.cfg
+++ b/tcl/target/dsp56321.cfg
@@ -1,13 +1,13 @@
 # Script for freescale DSP56321
 #
 
 # Script for freescale DSP56321
 #
 

-if { [info exists CHIPNAME] } {        
+if { [info exists CHIPNAME] } {

    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp56321
 }
 
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp56321
 }
 

-if { [info exists ENDIAN] } {  
+if { [info exists ENDIAN] } {

    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian

diff --git a/tcl/target/dsp568013.cfg b/tcl/target/dsp568013.cfg
index 40fa3c2b0ce88e52e9ecee7de171b3ae1d78de8b..67d44192eea366d421e18f7292415a28baa3b1e0 100644 (file)
--- a/tcl/target/dsp568013.cfg
+++ b/tcl/target/dsp568013.cfg
@@ -1,12 +1,12 @@
 # Script for freescale DSP568013
 
 # Script for freescale DSP568013
 

-if { [info exists CHIPNAME] } {        
+if { [info exists CHIPNAME] } {

    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp568013
 }
 
    set _CHIPNAME $CHIPNAME
 } else {
    set _CHIPNAME dsp568013
 }
 

-if { [info exists ENDIAN] } {  
+if { [info exists ENDIAN] } {

    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian
    set _ENDIAN $ENDIAN
 } else {
   # this defaults to a big endian

diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg
index 376320e832b3a430f0b7cfb96798d34dd67afbd4..544cff9d6a088e5a53f6768149543ca8efea33eb 100644 (file)
--- a/tcl/target/fm3.cfg
+++ b/tcl/target/fm3.cfg
@@ -36,10 +36,10 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
 

-# MB9BF506 has 64kB of SRAM on its main system bus 
+# MB9BF506 has 64kB of SRAM on its main system bus

 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
 
 $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0
 

-# MB9BF506 has 512kB internal FLASH 
+# MB9BF506 has 512kB internal FLASH

 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME
 
 set _FLASHNAME $_CHIPNAME.flash
 flash bank $_FLASHNAME fm3 0 0 0 0 $_TARGETNAME

diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
index 9eea53eef2194305a03540b177136beba5c4f76f..ccfddb6f7ca7f656d2fe7e73623ec09f6850fde6 100644 (file)
--- a/tcl/target/imx.cfg
+++ b/tcl/target/imx.cfg
@@ -6,7 +6,7 @@ set TARGETNAME $_TARGETNAME
 # rewrite commands of the form below to arm11 mcr...
 #      Data.Set c15:0x042f %long 0x40000015
 proc setc15 {regs value} {
 # rewrite commands of the form below to arm11 mcr...
 #      Data.Set c15:0x042f %long 0x40000015
 proc setc15 {regs value} {

-       global TARGETNAME 
+       global TARGETNAME

 
        echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
 
        echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 

diff --git a/tcl/target/ixp42x.cfg b/tcl/target/ixp42x.cfg
index 3f86e357b9557eb80fddc6cb8546c1a365020766..624fe29da8987cddd4e8980b9c5dee035d9bfa5a 100644 (file)
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -66,8 +66,8 @@ set IXP42x_SDRAM_256MB_32Mx16_2BANK   0x0015
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx
 
 # helper function to init SDRAM on IXP42x.
 # SDRAM_CFG: one of IXP42X_SDRAM_xxx

-# REFRESH: refresh counter reload value (integer) 
-# CASLAT: 2 or 3 
+# REFRESH: refresh counter reload value (integer)
+# CASLAT: 2 or 3

 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {
 proc ixp42x_init_sdram { SDRAM_CFG REFRESH CASLAT } {
 
     switch $CASLAT {

diff --git a/tcl/target/lpc2103.cfg b/tcl/target/lpc2103.cfg
index f55777f56508e9d9d610543b85f3cb3e4434d254..131b9ef89e211800c864fc8f203f5bbc5a806a0d 100644 (file)
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2103 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2103 12000 1500
 }
        # setup_lpc2103 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2103 12000 1500
 }

diff --git a/tcl/target/lpc2124.cfg b/tcl/target/lpc2124.cfg
index 02517381af8e9302a1082f88c1a0f51867ba42f0..ddbde22a5a5a1bd7f30851d7dadaf2d7b2ccdd53 100644 (file)
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2124 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2124 12000 1500
 }
        # setup_lpc2124 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2124 12000 1500
 }

diff --git a/tcl/target/lpc2129.cfg b/tcl/target/lpc2129.cfg
index 2c33cde310f5f6913e8f6b73e30006dc9f8c6a38..a1c3fe7bbce0bb0180225103f37a05154b19f440 100644 (file)
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2129 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2129 12000 1500
 }
        # setup_lpc2129 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2129 12000 1500
 }

diff --git a/tcl/target/lpc2148.cfg b/tcl/target/lpc2148.cfg
index f3a2011a81e1c91f593c7d4652dc838680562748..503a68264970da4c90d8878a3532c81174711fe3 100644 (file)
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2148 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2148 12000 1500
 }
        # setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2148 12000 1500
 }

diff --git a/tcl/target/lpc2294.cfg b/tcl/target/lpc2294.cfg
index 83d595deb57f8bb87e85a681e86781720a47740a..1320cda3ee2ef9e536627f06ec5f7ba42144afc7 100644 (file)
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -9,7 +9,7 @@ source [find target/lpc2xxx.cfg]
 proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
        # 256kB flash and 16kB SRAM
        # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>
 proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
        # 256kB flash and 16kB SRAM
        # setup_lpc2xxx <chip_name> <cputapid> <flash_size> <flash_variant> <workarea_size> <core_freq_khz> <adapter_freq_khz>

-       
+

        # !! TAPID unknown !!
        setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
 }
        # !! TAPID unknown !!
        setup_lpc2xxx lpc2294 0xffffffff 0x40000 lpc2000_v1 0x4000 $core_freq_khz $adapter_freq_khz
 }


@@ -17,7 +17,7 @@ proc setup_lpc2294 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 12MHz crystal
        echo "Warning - assuming default core clock 12MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2294 12000 1500
 }
        # setup_lpc2294 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2294 12000 1500
 }

diff --git a/tcl/target/lpc2378.cfg b/tcl/target/lpc2378.cfg
index 0b66b82557452d39eda19d0357556275924cf42f..235456a074408d33ad04fb69bd28021fd539137f 100644 (file)
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2378 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2378 4000 500
 }
        # setup_lpc2378 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2378 4000 500
 }

diff --git a/tcl/target/lpc2460.cfg b/tcl/target/lpc2460.cfg
index 69fdc4aafcb43f57230f46063aabccc178f3f4b6..c229f6dd6eb31066cd29b64de0c61dffed645d08 100644 (file)
--- a/tcl/target/lpc2460.cfg
+++ b/tcl/target/lpc2460.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2460 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2460 4000 500
 }
        # setup_lpc2460 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2460 4000 500
 }

diff --git a/tcl/target/lpc2478.cfg b/tcl/target/lpc2478.cfg
index 48e5bdf3f0af74e244062bc5dcb4bafcc0c575f3..36b5c46936fd32811f2d5c4b958c8ed7d0c51d3c 100644 (file)
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -15,7 +15,7 @@ proc setup_lpc2478 {core_freq_khz adapter_freq_khz} {
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."
 proc init_targets {} {
        # default to core clocked with 4MHz internal oscillator
        echo "Warning - assuming default core clock 4MHz! Flashing may fail if actual core clock is different."

-       
+

        # setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2478 4000 500
 }
        # setup_lpc2478 <core_freq_khz> <adapter_freq_khz>
        setup_lpc2478 4000 500
 }

diff --git a/tcl/target/lpc2xxx.cfg b/tcl/target/lpc2xxx.cfg
index 4c3394c95104d0ee6bf153e859764b3dfbc3c69c..f947c1b0532d7798203dc2413b69b6cc4798b678 100644 (file)
--- a/tcl/target/lpc2xxx.cfg
+++ b/tcl/target/lpc2xxx.cfg
@@ -40,5 +40,5 @@ proc setup_lpc2xxx {chip_name cputapids flash_size flash_variant workarea_size c
 proc init_targets {} {
        # FIX!!! read out CPUTAPID here and choose right setup. In addition to the
        # CPUTAPID some querying of the target would be required.
 proc init_targets {} {
        # FIX!!! read out CPUTAPID here and choose right setup. In addition to the
        # CPUTAPID some querying of the target would be required.

-       return -error "This is a generic LPC2xxx configuration file, use a specific target file." 
+       return -error "This is a generic LPC2xxx configuration file, use a specific target file."

 }
 }

diff --git a/tcl/target/lpc3131.cfg b/tcl/target/lpc3131.cfg
index d6f2cdbda9b5d9ee60431dc370dc6e01cc702056..89bbf0265fda0a4a45e53165b3c951f08297a8df 100644 (file)
--- a/tcl/target/lpc3131.cfg
+++ b/tcl/target/lpc3131.cfg
@@ -56,7 +56,7 @@ adapter srst delay 1000
 jtag_ntrst_delay 0
 
 set _TARGETNAME $_CHIPNAME.cpu
 jtag_ntrst_delay 0
 
 set _TARGETNAME $_CHIPNAME.cpu

-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME 
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME

 
 $_TARGETNAME invoke-event halted
 
 
 $_TARGETNAME invoke-event halted
 

diff --git a/tcl/target/u8500.cfg b/tcl/target/u8500.cfg
index baef9c81f21c9104113d9565a524a3afe4e61211..36e0db71d20e08166f789fb3b37f7697e95f4a38 100644 (file)
--- a/tcl/target/u8500.cfg
+++ b/tcl/target/u8500.cfg
@@ -1,6 +1,6 @@
 #  Copyright (C) ST-Ericsson SA 2011
 #  Author : michel.jaouen@stericsson.com
 #  Copyright (C) ST-Ericsson SA 2011
 #  Author : michel.jaouen@stericsson.com

-#  U8500 target 
+#  U8500 target

 
 proc mmu_off {} {
        set cp [arm mrc 15 0 1 0 0]
 
 proc mmu_off {} {
        set cp [arm mrc 15 0 1 0 0]


@@ -31,7 +31,7 @@ proc ocd_gdb_restart {target_id} {
 proc smp_reg {} {
        global _TARGETNAME_1
     global _TARGETNAME_2
 proc smp_reg {} {
        global _TARGETNAME_1
     global _TARGETNAME_2

-    targets $_TARGETNAME_1 
+    targets $_TARGETNAME_1

        echo "$_TARGETNAME_1"
        set pc1 [reg pc]
        set stck1 [reg sp_svc]
        echo "$_TARGETNAME_1"
        set pc1 [reg pc]
        set stck1 [reg sp_svc]


@@ -68,7 +68,7 @@ proc pwrsts { } {
                8 {
                        echo "A9 100% DVFS"
                  }
                8 {
                        echo "A9 100% DVFS"
                  }

-               c { 
+               c {

                        echo "A9 50% DVFS"
                }
        }
                        echo "A9 50% DVFS"
                }
        }


@@ -144,7 +144,7 @@ tcl_port 5555
 telnet_port 4444
 gdb_port 3333
 
 telnet_port 4444
 gdb_port 3333
 

-if { [info exists CHIPNAME] } {        
+if { [info exists CHIPNAME] } {

 global _CHIPNAME
     set _CHIPNAME $CHIPNAME
 } else {
 global _CHIPNAME
     set _CHIPNAME $CHIPNAME
 } else {


@@ -194,12 +194,12 @@ set _TARGETNAME_1 $TARGETNAME_1
 if { [info exists DAP_DBG1] } {
        set _DAP_DBG1 $DAP_DBG1
 } else {
 if { [info exists DAP_DBG1] } {
        set _DAP_DBG1 $DAP_DBG1
 } else {

-       set _DAP_DBG1 0x801A8000 
+       set _DAP_DBG1 0x801A8000

 }
 if { [info exists DAP_DBG2] } {
        set _DAP_DBG2 $DAP_DBG2
 } else {
 }
 if { [info exists DAP_DBG2] } {
        set _DAP_DBG2 $DAP_DBG2
 } else {

-       set _DAP_DBG2 0x801AA000 
+       set _DAP_DBG2 0x801AA000

 }
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 }
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu


@@ -226,7 +226,7 @@ global _SMP
 set _SMP $SMP
 }
 global SMP
 set _SMP $SMP
 }
 global SMP

-if { $_SMP == 1} { 
+if { $_SMP == 1} {

 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 
 target smp $_CHIPNAME.cpu2 $_CHIPNAME.cpu1
 }
 


@@ -264,7 +264,7 @@ proc att { } {
        } else {
                echo "target secured"
        }
        } else {
                echo "target secured"
        }

-       
+

 }
 
 
 }
 
 


@@ -310,10 +310,10 @@ if {![info exists MAXSPEED]} {
 global _MAXSPEED
 set _MAXSPEED 15000
 } else {
 global _MAXSPEED
 set _MAXSPEED 15000
 } else {

-global _MAXSPEED 
+global _MAXSPEED

 set _MAXSPEED $MAXSPEED
 }
 set _MAXSPEED $MAXSPEED
 }

-global _MAXSPEED 
+global _MAXSPEED

 adapter speed $_MAXSPEED
 
 
 adapter speed $_MAXSPEED