Using the ICEPick reset seems to allow the processor to be halted sooner
and the halt on gdb connection makes the connect process more robust.
Change-Id: I0586f6e6becc60a729030509ef58907a19d545ec
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/23
Tested-by: Øyvind Harboe <oyvindharboe@gmail.com>
Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
-# Copyright (C) 2010 by Karl Kurbjun
-# Copyright (C) 2009-2011 by Øyvind Harboe
+# Copyright (C) 2010-2011 by Karl Kurbjun
+# Copyright (C) 2009-2011 by Øyvind Harboe
# Copyright (C) 2009 by David Brownell
# Copyright (C) 2009 by Magnus Lundin
#
# Copyright (C) 2009 by David Brownell
# Copyright (C) 2009 by Magnus Lundin
#
# Primary TAP: ICEpick - it is closest to TDI so last in the chain
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
# Primary TAP: ICEpick - it is closest to TDI so last in the chain
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"
######
# End of Chain Description
######
######
# End of Chain Description
######
######
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
######
# Set the JTAG clock down to 10 kHz to be sure that it will work with the
-# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
+# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up
# *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
# *after* PLL and clock tree setup.
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }
-# Reset needs to be performed in in software.
-# The AM/DM37x TRM (sprugn4b) describes the software reset in detail.
-# PRM_RSTCTRL is described in table 3-425 on page 618. We assert RST_GS
-# (bit 1 (in 31:0) ) to do a warm reset.
-
-# Create a vaiable for the register address
-set PRM_RSTCTRL 0x48307250
+# Describe the reset assert process for openocd - this is asserted with the
+# ICEPick
+$_TARGETNAME configure -event "reset-assert" {
-# Describe the reset assert process: A value of 2 must be written
-# (assert bit 1) to the physical address of PRM_RSTCTRL.
-$_TARGETNAME configure -event \
- reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 2"
+ # assert warm system reset through ICEPick
+ icepick_c_wreset $_CHIPNAME.jrc
+}
# After the reset is asserted we need to re-initialize debugging and speed up
# the JTAG clock.
# After the reset is asserted we need to re-initialize debugging and speed up
# the JTAG clock.
-$_TARGETNAME configure -event \
- reset-assert-post "amdm37x_dbginit $_TARGETNAME; adapter_khz 1000"
+$_TARGETNAME configure -event reset-assert-post {
+
+ global _TARGETNAME
+ amdm37x_dbginit $_TARGETNAME
+ adapter_khz 1000
+}
+
+$_TARGETNAME configure -event gdb-attach {
+
+ global _TARGETNAME
+ amdm37x_dbginit $_TARGETNAME
+
+ echo "Halting target"
+ halt
+}
######
# End Target Reset Event Setup:
######
# End Target Reset Event Setup:
proc amdm37x_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
proc amdm37x_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
-
- # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
+
+ # Enable DBGEN signal. This signal is described in the ARM v7 TRM, but
# access to the signal appears to be implementation specific. TI does not
# describe this register much except a quick line that states DBGEM (sic) is
# at this address and this bit.
# access to the signal appears to be implementation specific. TI does not
# describe this register much except a quick line that states DBGEM (sic) is
# at this address and this bit.
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)