instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2632
b42882b7-edfa-0310-969c-
e2dbd0fdcd60
swjdp_common_t *swjdp = &armv7a->swjdp_info;
LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
+ do
+ {
+ retvalue = mem_ap_read_atomic_u32(swjdp,
+ OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+ }
+ while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+
mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+
do
{
retvalue = mem_ap_read_atomic_u32(swjdp,
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