Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before...
authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Wed, 26 Aug 2009 19:16:08 +0000 (19:16 +0000)
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Wed, 26 Aug 2009 19:16:08 +0000 (19:16 +0000)
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/cortex_a8.c

index 84ace67..dcf246f 100644 (file)
@@ -161,7 +161,15 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
        swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
        LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
+       do
+       {
+               retvalue = mem_ap_read_atomic_u32(swjdp,
+                               OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+       }
+       while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+
        mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+
        do
        {
                retvalue = mem_ap_read_atomic_u32(swjdp,