+/****************************************************************************\r
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.\r
+*\r
+* Redistribution and use in source and binary forms, with or without \r
+* modification, are permitted provided that the following conditions \r
+* are met:\r
+* \r
+* 1. Redistributions of source code must retain the above copyright \r
+* notice, this list of conditions and the following disclaimer.\r
+* 2. Redistributions in binary form must reproduce the above copyright\r
+* notice, this list of conditions and the following disclaimer in the \r
+* documentation and/or other materials provided with the distribution.\r
+* 3. Neither the name of the author nor the names of its contributors may \r
+* be used to endorse or promote products derived from this software \r
+* without specific prior written permission.\r
+*\r
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS \r
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL \r
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, \r
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, \r
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS \r
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED \r
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, \r
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF \r
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF \r
+* SUCH DAMAGE.\r
+*\r
+****************************************************************************\r
+*\r
+* History:\r
+*\r
+* 04.03.06 mifi First Version\r
+* This version based on an example from Ethernut and\r
+* "ARM Cross Development with Eclipse" from James P. Lynch\r
+*\r
+* 26.01.08 mifi Change the code of the init section. Here I have used\r
+* some of the source from the Anglia startup.s\r
+* Author: Spencer Oliver (www.anglia-designs.com)\r
+****************************************************************************/\r
+\r
+/*\r
+ * Some defines for the program status registers\r
+ */\r
+ ARM_MODE_USER = 0x10 /* Normal User Mode */ \r
+ ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */\r
+ ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */\r
+ ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */\r
+ ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */\r
+ ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */\r
+ ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */\r
+ ARM_MODE_MASK = 0x1F\r
+ \r
+ I_BIT = 0x80 /* disable IRQ when I bit is set */\r
+ F_BIT = 0x40 /* disable IRQ when I bit is set */\r
+ \r
+/*\r
+ * Register Base Address\r
+ */\r
+ PRCCU_BASE = 0xA0000000\r
+ RCCU_CFR = 0x08\r
+ RCCU_PLL1CR = 0x18\r
+ PCU_MDIVR = 0x40\r
+ PCU_PDIVR = 0x44\r
+ PCU_BOOTCR = 0x50\r
+ \r
+ \r
+ .section .vectors,"ax"\r
+ .code 32\r
+ \r
+/****************************************************************************/\r
+/* Vector table and reset entry */\r
+/****************************************************************************/\r
+_vectors:\r
+ ldr pc, ResetAddr /* Reset */\r
+ ldr pc, UndefAddr /* Undefined instruction */\r
+ ldr pc, SWIAddr /* Software interrupt */\r
+ ldr pc, PAbortAddr /* Prefetch abort */\r
+ ldr pc, DAbortAddr /* Data abort */\r
+ ldr pc, ReservedAddr /* Reserved */\r
+ ldr pc, IRQAddr /* IRQ interrupt */\r
+ ldr pc, FIQAddr /* FIQ interrupt */\r
+\r
+\r
+ResetAddr: .word ResetHandler\r
+UndefAddr: .word UndefHandler\r
+SWIAddr: .word SWIHandler\r
+PAbortAddr: .word PAbortHandler\r
+DAbortAddr: .word DAbortHandler\r
+ReservedAddr: .word 0\r
+IRQAddr: .word IRQHandler\r
+FIQAddr: .word FIQHandler\r
+\r
+ .ltorg\r
+\r
+\r
+ .section .init, "ax"\r
+ .code 32\r
+ \r
+ .global ResetHandler\r
+ .global ExitFunction\r
+ .extern main\r
+/****************************************************************************/\r
+/* Reset handler */\r
+/****************************************************************************/\r
+ResetHandler:\r
+/*\r
+ * Wait for the oscillator is stable\r
+ */ \r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ nop\r
+ \r
+/*\r
+ * Setup STR71X, for more information about the register\r
+ * take a look in the STR71x Microcontroller Reference Manual.\r
+ *\r
+ * Reference is made to: Rev. 6 March 2005\r
+ * \r
+ * 1. Map internal RAM to address 0\r
+ * In this case, we are running always in the RAM\r
+ * this make no sence. But if we are in flash, we\r
+ * can copy the interrupt vectors into the ram and\r
+ * switch to RAM mode.\r
+ *\r
+ * 2. Setup the PLL, the eval board HITEX STR7 is equipped\r
+ * with an external 16MHz oscillator. We want:\r
+ *\r
+ * RCLK: 32MHz = (CLK2 * 16) / 4\r
+ * MCLK: 32Mhz\r
+ * PCLK1: 32MHz\r
+ * PCLK2: 32MHz\r
+ *\r
+ */ \r
+ \r
+ /* \r
+ * 1. Map RAM to the boot memory 0x00000000\r
+ */\r
+ ldr r0, =PRCCU_BASE\r
+ ldr r1, =0x01C2 \r
+ str r1, [r0, #PCU_BOOTCR] \r
+ \r
+ \r
+ /*\r
+ * 2. Setup PLL start\r
+ */\r
+ \r
+ /* Set the prescaling factor for APB and APB1 group */\r
+ ldr r0, =PRCCU_BASE\r
+ ldr r1, =0x0000 /* no prescaling PCLKx = RCLK */ \r
+ str r1, [r0, #PCU_PDIVR] \r
+\r
+ /* Set the prescaling factor for the Main System Clock MCLK */\r
+ ldr r0, =PRCCU_BASE\r
+ ldr r1, =0x0000 /* no prescaling MCLK = RCLK\r
+ str r1, [r0, #PCU_MDIVR] \r
+ \r
+ /* Configure the PLL1 ( * 16 , / 4 ) */\r
+ ldr r0, =PRCCU_BASE\r
+ ldr r1, =0x0073 \r
+ str r1, [r0, #RCCU_PLL1CR] \r
+\r
+ /* Check if the PLL is locked */\r
+pll_lock_loop:\r
+ ldr r1, [r0, #RCCU_CFR]\r
+ tst r1, #0x0002\r
+ beq pll_lock_loop\r
+ \r
+ /* Select PLL1_Output as RCLK clock */\r
+ ldr r0, =PRCCU_BASE\r
+ ldr r1, =0x8009 \r
+ str r1, [r0, #RCCU_CFR] \r
+ \r
+ /*\r
+ * Setup PLL end\r
+ */\r
+ \r
+ \r
+ /*\r
+ * Setup a stack for each mode\r
+ */ \r
+ msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */ \r
+ ldr sp, =__stack_und_end__\r
+ \r
+ msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */\r
+ ldr sp, =__stack_abt_end__\r
+ \r
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */ \r
+ ldr sp, =__stack_fiq_end__\r
+ \r
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */ \r
+ ldr sp, =__stack_irq_end__\r
+ \r
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */\r
+ ldr sp, =__stack_svc_end__\r
+\r
+ \r
+ /*\r
+ * Now init all the sections\r
+ */\r
+\r
+\r
+ /* \r
+ * Relocate .data section (Copy from ROM to RAM) \r
+ */\r
+ ldr r1, =_etext\r
+ ldr r2, =__data_start\r
+ ldr r3, =_edata\r
+LoopRel:\r
+ cmp r2, r3\r
+ ldrlo r0, [r1], #4\r
+ strlo r0, [r2], #4\r
+ blo LoopRel\r
+\r
+\r
+ /* \r
+ * Clear .bss section (Zero init) \r
+ */\r
+ mov r0, #0\r
+ ldr r1, =__bss_start__\r
+ ldr r2, =__bss_end__\r
+LoopZI:\r
+ cmp r1, r2\r
+ strlo r0, [r1], #4\r
+ blo LoopZI\r
+\r
+ \r
+ /* \r
+ * Call C++ constructors \r
+ */\r
+ ldr r0, =__ctors_start__\r
+ ldr r1, =__ctors_end__\r
+ctor_loop:\r
+ cmp r0, r1\r
+ beq ctor_end\r
+ ldr r2, [r0], #4\r
+ stmfd sp!, {r0-r1}\r
+ mov lr, pc\r
+ mov pc, r2\r
+ ldmfd sp!, {r0-r1}\r
+ b ctor_loop\r
+ctor_end:\r
+ \r
+ \r
+ /*\r
+ * Jump to main\r
+ */\r
+ mrs r0, cpsr\r
+ bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */\r
+ msr cpsr, r0\r
+ \r
+ mov r0, #0 /* No arguments */\r
+ mov r1, #0 /* No arguments */\r
+ ldr r2, =main\r
+ mov lr, pc\r
+ bx r2 /* And jump... */\r
+ \r
+ExitFunction:\r
+ nop\r
+ nop\r
+ nop\r
+ b ExitFunction \r
+ \r
+\r
+/****************************************************************************/\r
+/* Default interrupt handler */\r
+/****************************************************************************/\r
+\r
+UndefHandler:\r
+ b UndefHandler\r
+ \r
+SWIHandler:\r
+ b SWIHandler\r
+\r
+PAbortHandler:\r
+ b PAbortHandler\r
+\r
+DAbortHandler:\r
+ b DAbortHandler\r
+ \r
+IRQHandler:\r
+ b IRQHandler\r
+ \r
+FIQHandler:\r
+ b FIQHandler\r
+ \r
+ .weak ExitFunction\r
+ .weak UndefHandler, PAbortHandler, DAbortHandler\r
+ .weak IRQHandler, FIQHandler\r
+\r
+ .ltorg\r
+/*** EOF ***/ \r
+ \r
+\r
\ No newline at end of file