- provide more directory structure for boards/targets?
- factor configurations into layers (encapsulation and re-use)
+- Fix handling of variables between multiple command line "-c" and "-f"
+ parameters. Currently variables assigned through one such parameter
+ command/script are unset before the next one is invoked.
+
- Isolate all TCL command support:
- Pure C CLI implementations using --disable-builtin-tcl.
- Allow developers to build new dongles using OpenOCD's JTAG core.
AC_PREREQ(2.60)
-AC_INIT([openocd], [0.3.0-in-development],
+AC_INIT([openocd], [0.3.0-dev],
[OpenOCD Mailing List <openocd-development@lists.berlios.de>])
AC_CONFIG_SRCDIR([src/openocd.c])
@subsection releaseversiontags Version Tags
After these required numeric components, the version string may contain
-one or more <i>version tags</i>, such as '-rc1' or '-in-development'.
+one or more <i>version tags</i>, such as '-rc1' or '-dev'.
-The trunk and all branches should have the tag '-in-development' in
+The trunk and all branches should have the tag '-dev' in
their version number. This tag helps developers identify reports
created from the Subversion repository, and it can be detected and
manipulated by the release script. Specifically, this tag will be
- This material should be produced during the development cycle.
- Add a new item for each @c NEWS-worthy contribution, when committed.
-# bump library version if our API changed (not yet required)
- -# Remove -in-development tag from package version:
+ -# Remove -dev tag from package version in configure.in:
- For major/minor releases, remove version tag from trunk, @a or
- For bug-fix releases, remove version tag from release branch.
-# Branch or tag the required tree in the Subversion repository:
* GDB and OpenOCD:: Using GDB and OpenOCD
* Tcl Scripting API:: Tcl Scripting API
* Upgrading:: Deprecated/Removed Commands
-* Target Library:: Target Library
* FAQ:: Frequently Asked Questions
* Tcl Crash Course:: Tcl Crash Course
* License:: GNU Free Documentation License
One might re-flash the board with a specific firmware version.
Another might set up a particular debugging or run-time environment.
+@quotation Important
+At this writing (October 2009) the command line method has
+problems with how it treats variables.
+For example, after @option{-c "set VAR value"}, or doing the
+same in a script, the variable @var{VAR} will have no value
+that can be tested in a later script.
+@end quotation
+
Here we will focus on the simpler solution: one user config
file, including basic configuration plus any TCL procedures
to simplify your work.
needs to get a new board working smoothly.
It provides guidelines for creating those files.
-You should find the following directories under @t{$(INSTALLDIR)/scripts}:
+You should find the following directories under @t{$(INSTALLDIR)/scripts},
+with files including the ones listed here.
+Use them as-is where you can; or as models for new files.
@itemize @bullet
@item @file{interface} ...
think JTAG Dongle. Files that configure JTAG adapters go here.
+@example
+$ ls interface
+arm-jtag-ew.cfg hitex_str9-comstick.cfg oocdlink.cfg
+arm-usb-ocd.cfg icebear.cfg openocd-usb.cfg
+at91rm9200.cfg jlink.cfg parport.cfg
+axm0432.cfg jtagkey2.cfg parport_dlc5.cfg
+calao-usb-a9260-c01.cfg jtagkey.cfg rlink.cfg
+calao-usb-a9260-c02.cfg jtagkey-tiny.cfg sheevaplug.cfg
+calao-usb-a9260.cfg luminary.cfg signalyzer.cfg
+chameleon.cfg luminary-icdi.cfg stm32-stick.cfg
+cortino.cfg luminary-lm3s811.cfg turtelizer2.cfg
+dummy.cfg olimex-arm-usb-ocd.cfg usbprog.cfg
+flyswatter.cfg olimex-jtag-tiny.cfg vsllink.cfg
+$
+@end example
@item @file{board} ...
think Circuit Board, PWA, PCB, they go by many names. Board files
-contain initialization items that are specific to a board. For
+contain initialization items that are specific to a board.
+They reuse target configuration files, since the same
+microprocessor chips are used on many boards,
+but support for external parts varies widely. For
example, the SDRAM initialization sequence for the board, or the type
of external flash and what address it uses. Any initialization
sequence to enable that external flash or SDRAM should be found in the
board file. Boards may also contain multiple targets: two CPUs; or
-a CPU and an FPGA or CPLD.
+a CPU and an FPGA.
+@example
+$ ls board
+arm_evaluator7t.cfg keil_mcb1700.cfg
+at91rm9200-dk.cfg keil_mcb2140.cfg
+at91sam9g20-ek.cfg linksys_nslu2.cfg
+atmel_at91sam7s-ek.cfg logicpd_imx27.cfg
+atmel_at91sam9260-ek.cfg mini2440.cfg
+atmel_sam3u_ek.cfg olimex_LPC2378STK.cfg
+crossbow_tech_imote2.cfg olimex_lpc_h2148.cfg
+csb337.cfg olimex_sam7_ex256.cfg
+csb732.cfg olimex_sam9_l9260.cfg
+digi_connectcore_wi-9c.cfg olimex_stm32_h103.cfg
+dm355evm.cfg omap2420_h4.cfg
+dm365evm.cfg osk5912.cfg
+dm6446evm.cfg pic-p32mx.cfg
+eir.cfg propox_mmnet1001.cfg
+ek-lm3s1968.cfg pxa255_sst.cfg
+ek-lm3s3748.cfg sheevaplug.cfg
+ek-lm3s811.cfg stm3210e_eval.cfg
+ek-lm3s9b9x.cfg stm32f10x_128k_eval.cfg
+hammer.cfg str910-eval.cfg
+hitex_lpc2929.cfg telo.cfg
+hitex_stm32-performancestick.cfg ti_beagleboard.cfg
+hitex_str9-comstick.cfg topas910.cfg
+iar_str912_sk.cfg topasa900.cfg
+imx27ads.cfg unknown_at91sam9260.cfg
+imx27lnst.cfg x300t.cfg
+imx31pdk.cfg zy1000.cfg
+$
+@end example
@item @file{target} ...
think chip. The ``target'' directory represents the JTAG TAPs
on a chip
are ARM chips and FPGA or CPLD chips.
When a chip has multiple TAPs (maybe it has both ARM and DSP cores),
the target config file defines all of them.
+@example
+$ ls target
+aduc702x.cfg imx27.cfg pxa255.cfg
+ar71xx.cfg imx31.cfg pxa270.cfg
+at91eb40a.cfg imx35.cfg readme.txt
+at91r40008.cfg is5114.cfg sam7se512.cfg
+at91rm9200.cfg ixp42x.cfg sam7x256.cfg
+at91sam3u1c.cfg lm3s1968.cfg samsung_s3c2410.cfg
+at91sam3u1e.cfg lm3s3748.cfg samsung_s3c2440.cfg
+at91sam3u2c.cfg lm3s6965.cfg samsung_s3c2450.cfg
+at91sam3u2e.cfg lm3s811.cfg samsung_s3c4510.cfg
+at91sam3u4c.cfg lm3s9b9x.cfg samsung_s3c6410.cfg
+at91sam3u4e.cfg lpc1768.cfg sharp_lh79532.cfg
+at91sam3uXX.cfg lpc2103.cfg smdk6410.cfg
+at91sam7sx.cfg lpc2124.cfg smp8634.cfg
+at91sam9260.cfg lpc2129.cfg stm32.cfg
+c100.cfg lpc2148.cfg str710.cfg
+c100config.tcl lpc2294.cfg str730.cfg
+c100helper.tcl lpc2378.cfg str750.cfg
+c100regs.tcl lpc2478.cfg str912.cfg
+cs351x.cfg lpc2900.cfg telo.cfg
+davinci.cfg mega128.cfg ti_dm355.cfg
+dragonite.cfg netx500.cfg ti_dm365.cfg
+epc9301.cfg omap2420.cfg ti_dm6446.cfg
+feroceon.cfg omap3530.cfg tmpa900.cfg
+icepick.cfg omap5912.cfg tmpa910.cfg
+imx21.cfg pic32mx.cfg xba_revA3.cfg
+$
+@end example
+@item @emph{more} ... browse for other library files which may be useful.
+For example, there are various generic and CPU-specific utilities.
@end itemize
The @file{openocd.cfg} user config
@end deffn
@deffn {Command} reset_config mode_flag ...
-This command tells OpenOCD the reset configuration
+This command displays or modifies the reset configuration
of your combination of JTAG board and target in target
configuration scripts.
with a board that only wires up SRST.)
The @var{mode_flag} options can be specified in any order, but only one
-of each type -- @var{signals}, @var{combination}, @var{trst_type},
+of each type -- @var{signals}, @var{combination},
+@var{gates},
+@var{trst_type},
and @var{srst_type} -- may be specified at a time.
If you don't provide a new value for a given type, its previous
value (perhaps the default) is unchanged.
TRST just to declare that if the JTAG adapter should want to drive SRST,
it must explicitly be driven high (@option{srst_push_pull}).
+@itemize
+@item
@var{signals} can specify which of the reset signals are connected.
For example, If the JTAG interface provides SRST, but the board doesn't
connect that signal properly, then OpenOCD can't use it.
@option{srst_only} and @option{trst_and_srst}.
@quotation Tip
-If your board provides SRST or TRST through the JTAG connector,
+If your board provides SRST and/or TRST through the JTAG connector,
you must declare that or else those signals will not be used.
@end quotation
+@item
The @var{combination} is an optional value specifying broken reset
signal implementations.
The default behaviour if no option given is @option{separate},
@option{combined} implies both @option{srst_pulls_trst} and
@option{trst_pulls_srst}.
-@option{srst_gates_jtag} indicates that asserting SRST gates the
+@item
+The @var{gates} tokens control flags that describe some cases where
+JTAG may be unvailable during reset.
+@option{srst_gates_jtag} (default)
+indicates that asserting SRST gates the
JTAG clock. This means that no communication can happen on JTAG
while SRST is asserted.
+Its converse is @option{srst_nogate}, indicating that JTAG commands
+can safely be issued while SRST is active.
+@end itemize
The optional @var{trst_type} and @var{srst_type} parameters allow the
driver mode of each reset line to be specified. These values only affect
JTAG interfaces with support for different driver modes, like the Amontec
-JTAGkey and JTAGAccelerator. Also, they are necessarily ignored if the
+JTAGkey and JTAG Accelerator. Also, they are necessarily ignored if the
relevant signal (TRST or SRST) is not connected.
+@itemize
+@item
Possible @var{trst_type} driver modes for the test reset signal (TRST)
-are @option{trst_push_pull} (default) and @option{trst_open_drain}.
+are the default @option{trst_push_pull}, and @option{trst_open_drain}.
Most boards connect this signal to a pulldown, so the JTAG TAPs
never leave reset unless they are hooked up to a JTAG adapter.
+@item
Possible @var{srst_type} driver modes for the system reset signal (SRST)
are the default @option{srst_open_drain}, and @option{srst_push_pull}.
Most boards connect this signal to a pullup, and allow the
signal to be pulled low by various events including system
powerup and pressing a reset button.
+@end itemize
@end deffn
@}
@end example
-@node Target Library
-@chapter Target Library
-@cindex Target Library
-
-OpenOCD comes with a target configuration script library. These scripts can be
-used as-is or serve as a starting point.
-
-The target library is published together with the OpenOCD executable and
-the path to the target library is in the OpenOCD script search path.
-Similarly there are example scripts for configuring the JTAG interface.
-
-The command line below uses the example parport configuration script
-that ship with OpenOCD, then configures the str710.cfg target and
-finally issues the init and reset commands. The communication speed
-is set to 10kHz for reset and 8MHz for post reset.
-
-@example
-openocd -f interface/parport.cfg -f target/str710.cfg \
- -c "init" -c "reset"
-@end example
-
-To list the target scripts available:
-
-@example
-$ ls /usr/local/lib/openocd/target
-
-arm7_fast.cfg lm3s6965.cfg pxa255.cfg stm32.cfg xba_revA3.cfg
-at91eb40a.cfg lpc2148.cfg pxa255_sst.cfg str710.cfg zy1000.cfg
-at91r40008.cfg lpc2294.cfg sam7s256.cfg str912.cfg
-at91sam9260.cfg nslu2.cfg sam7x256.cfg wi-9c.cfg
-@end example
-
@include fdl.texi
@node OpenOCD Concept Index
-#!/bin/bash
+#!/bin/sh
#
+# This scripts adds local version information from the version
+# control systems git, mercurial (hg) and subversion (svn).
+#
+# Copied from Linux 2.6.32 scripts/setlocalversion and modified
+# slightly to work better for OpenOCD.
+#
+
+usage() {
+ echo "Usage: $0 [srctree]" >&2
+ exit 1
+}
+
+cd "${1:-.}" || usage
+
+# Check for git and a git repo.
+if head=`git rev-parse --verify --short HEAD 2>/dev/null`; then
+
+ # If we are at a tagged commit (like "v2.6.30-rc6"), we ignore it,
+ # because this version is defined in the top level Makefile.
+ if [ -z "`git describe --exact-match 2>/dev/null`" ]; then
+
+ # If we are past a tagged commit (like "v2.6.30-rc5-302-g72357d5"),
+ # we pretty print it.
+ if atag="`git describe 2>/dev/null`"; then
+ echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}'
+
+ # If we don't have a tag at all we print -g{commitish}.
+ else
+ printf '%s%s' -g $head
+ fi
+ fi
+
+ # Is this git on svn?
+ if git config --get svn-remote.svn.url >/dev/null; then
+ printf -- '-svn%s' "`git svn find-rev $head`"
+ fi
+
+ # Update index only on r/w media
+ [ -w . ] && git update-index --refresh --unmerged > /dev/null
+
+ # Check for uncommitted changes
+ if git diff-index --name-only HEAD | grep -v "^scripts/package" \
+ | read dummy; then
+ printf '%s' -dirty
+ fi
+
+ # All done with git
+ exit
+fi
+
+# Check for mercurial and a mercurial repo.
+if hgid=`hg id 2>/dev/null`; then
+ tag=`printf '%s' "$hgid" | cut -d' ' -f2`
+
+ # Do we have an untagged version?
+ if [ -z "$tag" -o "$tag" = tip ]; then
+ id=`printf '%s' "$hgid" | sed 's/[+ ].*//'`
+ printf '%s%s' -hg "$id"
+ fi
+
+ # Are there uncommitted changes?
+ # These are represented by + after the changeset id.
+ case "$hgid" in
+ *+|*+\ *) printf '%s' -dirty ;;
+ esac
+
+ # All done with mercurial
+ exit
+fi
-REV=unknown
+# Check for svn and a svn repo.
+if rev=`svn info 2>/dev/null | grep '^Last Changed Rev'`; then
+ rev=`echo $rev | awk '{print $NF}'`
+ printf -- '-svn%s' "$rev"
-which svnversion > /dev/null 2>&1 && REV=`svnversion -n "$1"`
+ # All done with svn
+ exit
+fi
-echo -n $REV
+# There's no reecognized repository; we must be a snapshot.
+printf -- '-snapshot'
libopenocd_la_CPPFLAGS = -DPKGBLDDATE=\"`date +%F-%R`\"
+# banner output includes RELSTR appended to $VERSION from the configure script
+# guess-rev.sh returns either a repository version ID or "-snapshot"
if RELEASE
-libopenocd_la_CPPFLAGS += -DRELSTR=\"Release\" -DPKGBLDREV=\"\"
+libopenocd_la_CPPFLAGS += -DRELSTR=\"\"
else
-libopenocd_la_CPPFLAGS += -DRELSTR=\"svn:\" -DPKGBLDREV=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
+libopenocd_la_CPPFLAGS += -DRELSTR=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
endif
# add default CPPFLAGS
static void zylinjtag_reboot(cyg_addrword_t data)
{
serialLog = true;
- diag_printf("Rebooting in 100 ticks..\n");
- cyg_thread_delay(100);
+ diag_printf("Rebooting in 500 ticks..\n");
+ cyg_thread_delay(500);
diag_printf("Unmounting /config..\n");
umount("/config");
diag_printf("Rebooting..\n");
break;
}
- /* Validate the two LSBs, which must be 01 per JTAG spec.
- * REVISIT we might be able to verify some MSBs too, using
- * ircapture/irmask attributes.
- */
- val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
- if ((val & 0x3) != 1) {
- LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
- jtag_tap_name(tap),
- (tap->ir_length + 7) / tap->ir_length,
- val);
-
- retval = ERROR_JTAG_INIT_FAILED;
- goto done;
+ if (tap->hasidcode)
+ {
+ /* Validate the two LSBs, which must be 01 per JTAG spec.
+ * REVISIT we might be able to verify some MSBs too, using
+ * ircapture/irmask attributes.
+ */
+ val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
+ if ((val & 0x3) != 1) {
+ LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
+ jtag_tap_name(tap),
+ (tap->ir_length + 7) / tap->ir_length,
+ val);
+
+ retval = ERROR_JTAG_INIT_FAILED;
+ goto done;
+ }
}
LOG_DEBUG("%s: IR capture 0x%0*x", jtag_tap_name(tap),
(tap->ir_length + 7) / tap->ir_length, val);
RESET_TRST_PULLS_SRST = 0x8,
RESET_TRST_OPEN_DRAIN = 0x10,
RESET_SRST_PUSH_PULL = 0x20,
- RESET_SRST_GATES_JTAG = 0x40,
+ RESET_SRST_NO_GATING = 0x40,
};
enum reset_types jtag_get_reset_config(void);
COMMAND_CONFIG, "(DEPRECATED) jtag_device <ir_length> <ir_expected> <ir_mask>");
register_command(cmd_ctx, NULL, "reset_config", handle_reset_config_command,
COMMAND_ANY,
- "[none/trst_only/srst_only/trst_and_srst] [srst_pulls_trst/trst_pulls_srst] [combined/separate] [trst_push_pull/trst_open_drain] [srst_push_pull/srst_open_drain]");
+ "reset_config "
+ "[none|trst_only|srst_only|trst_and_srst] "
+ "[srst_pulls_trst|trst_pulls_srst|combined|separate] "
+ "[srst_gates_jtag|srst_nogate] "
+ "[trst_push_pull|trst_open_drain] "
+ "[srst_push_pull|srst_open_drain]");
register_command(cmd_ctx, NULL, "jtag_nsrst_delay", handle_jtag_nsrst_delay_command,
COMMAND_ANY, "jtag_nsrst_delay <ms> - delay after deasserting srst in ms");
register_command(cmd_ctx, NULL, "jtag_ntrst_delay", handle_jtag_ntrst_delay_command,
int new_cfg = 0;
int mask = 0;
- if (argc < 1)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
/* Original versions cared about the order of these tokens:
* reset_config signals [combination [trst_type [srst_type]]]
* They also clobbered the previous configuration even on error.
int tmp = 0;
int m;
- m = RESET_SRST_GATES_JTAG;
- tmp = 0;
+ /* gating */
+ m = RESET_SRST_NO_GATING;
if (strcmp(*args, "srst_gates_jtag") == 0)
- {
- tmp = RESET_SRST_GATES_JTAG;
- goto next;
+ /* default: don't use JTAG while SRST asserted */;
+ else if (strcmp(*args, "srst_nogate") == 0)
+ tmp = RESET_SRST_NO_GATING;
+ else
+ m = 0;
+ if (mask & m) {
+ LOG_ERROR("extra reset_config %s spec (%s)",
+ "gating", *args);
+ return ERROR_INVALID_ARGUMENTS;
}
+ if (m)
+ goto next;
/* signals */
m = RESET_HAS_TRST | RESET_HAS_SRST;
}
/* clear previous values of those bits, save new values */
- enum reset_types old_cfg = jtag_get_reset_config();
- old_cfg &= ~mask;
- new_cfg |= old_cfg;
- jtag_set_reset_config(new_cfg);
+ if (mask) {
+ int old_cfg = jtag_get_reset_config();
+
+ old_cfg &= ~mask;
+ new_cfg |= old_cfg;
+ jtag_set_reset_config(new_cfg);
+ } else
+ new_cfg = jtag_get_reset_config();
+
+
+ /*
+ * Display the (now-)current reset mode
+ */
+ char *modes[5];
+
+ /* minimal JTAG has neither SRST nor TRST (so that's the default) */
+ switch (new_cfg & (RESET_HAS_TRST | RESET_HAS_SRST)) {
+ case RESET_HAS_SRST:
+ modes[0] = "srst_only";
+ break;
+ case RESET_HAS_TRST:
+ modes[0] = "trst_only";
+ break;
+ case RESET_TRST_AND_SRST:
+ modes[0] = "trst_and_srst";
+ break;
+ default:
+ modes[0] = "none";
+ break;
+ }
+
+ /* normally SRST and TRST are decoupled; but bugs happen ... */
+ switch (new_cfg & (RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST)) {
+ case RESET_SRST_PULLS_TRST:
+ modes[1] = "srst_pulls_trst";
+ break;
+ case RESET_TRST_PULLS_SRST:
+ modes[1] = "trst_pulls_srst";
+ break;
+ case RESET_SRST_PULLS_TRST | RESET_TRST_PULLS_SRST:
+ modes[1] = "combined";
+ break;
+ default:
+ modes[1] = "separate";
+ break;
+ }
+
+ /* TRST-less connectors include Altera, Xilinx, and minimal JTAG */
+ if (new_cfg & RESET_HAS_TRST) {
+ if (new_cfg & RESET_TRST_OPEN_DRAIN)
+ modes[3] = " trst_open_drain";
+ else
+ modes[3] = " trst_push_pull";
+ } else
+ modes[3] = "";
+
+ /* SRST-less connectors include TI-14, Xilinx, and minimal JTAG */
+ if (new_cfg & RESET_HAS_SRST) {
+ if (new_cfg & RESET_SRST_NO_GATING)
+ modes[2] = " srst_nogate";
+ else
+ modes[2] = " srst_gates_jtag";
+
+ if (new_cfg & RESET_SRST_PUSH_PULL)
+ modes[4] = " srst_push_pull";
+ else
+ modes[4] = " srst_open_drain";
+ } else {
+ modes[2] = "";
+ modes[4] = "";
+ }
+
+ command_print(cmd_ctx, "%s %s%s%s%s",
+ modes[0], modes[1],
+ modes[2], modes[3], modes[4]);
return ERROR_OK;
}
#include <cyg/hal/hal_diag.h>
-#define ZYLIN_VERSION "1.54"
+#define ZYLIN_VERSION "1.55"
#define ZYLIN_DATE __DATE__
#define ZYLIN_TIME __TIME__
#define ZYLIN_OPENOCD "$Revision$"
#define OPENOCD_VERSION \
- "Open On-Chip Debugger " VERSION " (" PKGBLDDATE ") " RELSTR PKGBLDREV
+ "Open On-Chip Debugger " VERSION RELSTR " (" PKGBLDDATE ")"
static void print_version(void)
{
uint32_t dscr;
+ int i = 0;
while (1)
{
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
+
+
+ long long then = 0;
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
}
arm11_on_enter_debug_state(arm11);
CHECK_RETVAL(jtag_execute_queue());
+ int i = 0;
while (1)
{
uint32_t dscr;
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
+
+
+ long long then = 0;
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
}
if (!debug_execution)
CHECK_RETVAL(jtag_execute_queue());
- /** \todo TODO: add a timeout */
-
/* wait for halt */
-
+ int i = 0;
while (1)
{
uint32_t dscr;
if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
break;
+
+ long long then = 0;
+ if (i == 1000)
+ {
+ then = timeval_ms();
+ }
+ if (i >= 1000)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+ return ERROR_FAIL;
+ }
+ }
+ i++;
}
/* clear breakpoint */
if (address + size * count != r0)
{
- LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
+ LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
+ address + size * count, r0);
if (arm11_config_memwrite_burst)
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
0xFFFFFFFF, /* value */
};
-const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
-const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
-
arm11_common_t * arm11_find_target(const char * arg)
{
jtag_tap_t * tap;
{
if (argc != (read ? 6 : 7))
{
- LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
- return -1;
+ LOG_ERROR("Invalid number of arguments.");
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
arm11_common_t * arm11 = arm11_find_target(args[0]);
if (!arm11)
{
- LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
- read ? arm11_mrc_syntax : arm11_mcr_syntax);
-
- return -1;
+ LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
if (arm11->target->state != TARGET_HALTED)
if (values[i] > arm11_coproc_instruction_limits[i])
{
- LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+ LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
(long)(i + 2),
- arm11_coproc_instruction_limits[i],
- read ? arm11_mrc_syntax : arm11_mcr_syntax);
- return -1;
+ arm11_coproc_instruction_limits[i]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
}
register_command(cmd_ctx, top_cmd, "mcr",
arm11_handle_mcr, COMMAND_ANY,
- "Write Coprocessor register");
+ "Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, top_cmd, "mrc",
arm11_handle_mrc, COMMAND_ANY,
- "Read Coprocessor register");
+ "Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
register_command(cmd_ctx, top_cmd, "no_increment",
arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
"Don't increment address on multi-read/-write"
return ERROR_FAIL;
}
- /* at this point trst has been asserted/deasserted once. We want to
- * program embedded ice while SRST is asserted, but some CPUs gate
- * the JTAG clock while SRST is asserted
+ /* At this point trst has been asserted/deasserted once. We would
+ * like to program EmbeddedICE while SRST is asserted, instead of
+ * depending on SRST to leave that module alone. However, many CPUs
+ * gate the JTAG clock while SRST is asserted; or JTAG may need
+ * clock stability guarantees (adaptive clocking might help).
+ *
+ * So we assume JTAG access during SRST is off the menu unless it's
+ * been specifically enabled.
*/
bool srst_asserted = false;
- if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+
+ if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+ && (jtag_reset_config & RESET_SRST_NO_GATING))
{
jtag_add_reset(0, 1);
srst_asserted = true;
# The IMX31PDK eval board has a single IMX31 chip
source [find target/imx31.cfg]
-$_TARGETNAME configure -event gdb-attach { reset init }
$_TARGETNAME configure -event reset-init { imx31pdk_init }
proc imx31pdk_init { } {
# This setup puts RAM at 0x80000000
- # reset the board correctly
- reset run
- reset halt
-
# ========================================
# Init CCM
# ========================================
--- /dev/null
+# The IMX35PDK eval board has a single IMX35 chip
+source [find target/imx35.cfg]
+$_TARGETNAME configure -event reset-init { imx35pdk_init }
+
+memwrite burst disable
+#arm11 no_increment enable
+
+
+global TARGETNAME
+set TARGETNAME $_TARGETNAME
+
+# rewrite commands of the form below to arm11 mcr...
+# Data.Set c15:0x042f %long 0x40000015
+proc setc15 {regs value} {
+ global TARGETNAME
+
+ echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+
+ arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
+}
+
+proc imx35pdk_init { } {
+
+
+ echo "Target Setup: initialize DRAM controller and peripherals"
+
+# Data.Set c15:0x01 %long 0x00050078
+ setc15 0x01 0x00050078
+
+ echo "configuring CP15 for enabling the peripheral bus"
+# Data.Set c15:0x042f %long 0x40000015
+ setc15 0x042f 0x40000015
+
+ mww 0x43f00040 0x00000000
+ mww 0x43f00044 0x00000000
+ mww 0x43f00048 0x00000000
+ mww 0x43f0004C 0x00000000
+ mww 0x43f00050 0x00000000
+ mww 0x43f00000 0x77777777
+ mww 0x43f00004 0x77777777
+ mww 0x53f00040 0x00000000
+ mww 0x53f00044 0x00000000
+ mww 0x53f00048 0x00000000
+ mww 0x53f0004C 0x00000000
+ mww 0x53f00050 0x00000000
+ mww 0x53f00000 0x77777777
+ mww 0x53f00004 0x77777777
+
+ # clock setup
+ mww 0x53F80004 0x00821000 # first need to set IPU_HND_BYP
+ mww 0x53F80004 0x00821000 #arm clock is 399Mhz and ahb clock is 133Mhz.
+
+ #=================================================
+ # WEIM config
+ #=================================================
+ # CS0U
+ mww 0xB8002000 0x0000CC03
+ # CS0L
+ mww 0xB8002004 0xA0330D01
+ # CS0A
+ mww 0xB8002008 0x00220800
+ # CS5U
+ mww 0xB8002050 0x0000dcf6
+ # CS5L
+ mww 0xB8002054 0x444a4541
+ # CS5A
+ mww 0xB8002058 0x44443302
+
+ # IO SW PAD Control registers - setting of 0x0002 is high drive, mDDR
+ mww 0x43FAC368 0x00000006
+ mww 0x43FAC36C 0x00000006
+ mww 0x43FAC370 0x00000006
+ mww 0x43FAC374 0x00000006
+ mww 0x43FAC378 0x00000006
+ mww 0x43FAC37C 0x00000006
+ mww 0x43FAC380 0x00000006
+ mww 0x43FAC384 0x00000006
+ mww 0x43FAC388 0x00000006
+ mww 0x43FAC38C 0x00000006
+ mww 0x43FAC390 0x00000006
+ mww 0x43FAC394 0x00000006
+ mww 0x43FAC398 0x00000006
+ mww 0x43FAC39C 0x00000006
+ mww 0x43FAC3A0 0x00000006
+ mww 0x43FAC3A4 0x00000006
+ mww 0x43FAC3A8 0x00000006
+ mww 0x43FAC3AC 0x00000006
+ mww 0x43FAC3B0 0x00000006
+ mww 0x43FAC3B4 0x00000006
+ mww 0x43FAC3B8 0x00000006
+ mww 0x43FAC3BC 0x00000006
+ mww 0x43FAC3C0 0x00000006
+ mww 0x43FAC3C4 0x00000006
+ mww 0x43FAC3C8 0x00000006
+ mww 0x43FAC3CC 0x00000006
+ mww 0x43FAC3D0 0x00000006
+ mww 0x43FAC3D4 0x00000006
+ mww 0x43FAC3D8 0x00000006
+
+ # DDR data bus SD 0 through 31
+ mww 0x43FAC3DC 0x00000082
+ mww 0x43FAC3E0 0x00000082
+ mww 0x43FAC3E4 0x00000082
+ mww 0x43FAC3E8 0x00000082
+ mww 0x43FAC3EC 0x00000082
+ mww 0x43FAC3F0 0x00000082
+ mww 0x43FAC3F4 0x00000082
+ mww 0x43FAC3F8 0x00000082
+ mww 0x43FAC3FC 0x00000082
+ mww 0x43FAC400 0x00000082
+ mww 0x43FAC404 0x00000082
+ mww 0x43FAC408 0x00000082
+ mww 0x43FAC40C 0x00000082
+ mww 0x43FAC410 0x00000082
+ mww 0x43FAC414 0x00000082
+ mww 0x43FAC418 0x00000082
+ mww 0x43FAC41c 0x00000082
+ mww 0x43FAC420 0x00000082
+ mww 0x43FAC424 0x00000082
+ mww 0x43FAC428 0x00000082
+ mww 0x43FAC42c 0x00000082
+ mww 0x43FAC430 0x00000082
+ mww 0x43FAC434 0x00000082
+ mww 0x43FAC438 0x00000082
+ mww 0x43FAC43c 0x00000082
+ mww 0x43FAC440 0x00000082
+ mww 0x43FAC444 0x00000082
+ mww 0x43FAC448 0x00000082
+ mww 0x43FAC44c 0x00000082
+ mww 0x43FAC450 0x00000082
+ mww 0x43FAC454 0x00000082
+ mww 0x43FAC458 0x00000082
+
+ # DQM setup
+ mww 0x43FAC45c 0x00000082
+ mww 0x43FAC460 0x00000082
+ mww 0x43FAC464 0x00000082
+ mww 0x43FAC468 0x00000082
+
+ mww 0x43FAC46c 0x00000006
+ mww 0x43FAC470 0x00000006
+ mww 0x43FAC474 0x00000006
+ mww 0x43FAC478 0x00000006
+ mww 0x43FAC47c 0x00000006
+ mww 0x43FAC480 0x00000006 # CSD0
+ mww 0x43FAC484 0x00000006 # CSD1
+ mww 0x43FAC488 0x00000006
+ mww 0x43FAC48c 0x00000006
+ mww 0x43FAC490 0x00000006
+ mww 0x43FAC494 0x00000006
+ mww 0x43FAC498 0x00000006
+ mww 0x43FAC49c 0x00000006
+ mww 0x43FAC4A0 0x00000006
+ mww 0x43FAC4A4 0x00000006 # RAS
+ mww 0x43FAC4A8 0x00000006 # CAS
+ mww 0x43FAC4Ac 0x00000006 # SDWE
+ mww 0x43FAC4B0 0x00000006 # SDCKE0
+ mww 0x43FAC4B4 0x00000006 # SDCKE1
+ mww 0x43FAC4B8 0x00000002 # SDCLK
+
+ # SDQS0 through SDQS3
+ mww 0x43FAC4Bc 0x00000082
+ mww 0x43FAC4C0 0x00000082
+ mww 0x43FAC4C4 0x00000082
+ mww 0x43FAC4C8 0x00000082
+
+
+ # *==================================================
+ # Initialization script for 32 bit DDR2 on RINGO 3DS
+ # *==================================================
+
+ #--------------------------------------------
+ # Init CCM
+ #--------------------------------------------
+ mww 0x53F80028 0x7D000028
+
+ #--------------------------------------------
+ # Init IOMUX for JTAG
+ #--------------------------------------------
+ mww 0x43FAC5EC 0x000000C3
+ mww 0x43FAC5F0 0x000000C3
+ mww 0x43FAC5F4 0x000000F3
+ mww 0x43FAC5F8 0x000000F3
+ mww 0x43FAC5FC 0x000000F3
+ mww 0x43FAC600 0x000000F3
+ mww 0x43FAC604 0x000000F3
+
+
+ # ESD_MISC : enable DDR2
+ mww 0xB8001010 0x00000304
+
+ #--------------------------------------------
+ # Init 32-bit DDR2 memeory on CSD0
+ # COL=10-bit, ROW=13-bit, BA[1:0]=Addr[26:25]
+ #--------------------------------------------
+
+ # ESD_ESDCFG0 : set timing paramters
+ mww 0xB8001004 0x007ffC2f
+
+ # ESD_ESDCTL0 : select Prechare-All mode
+ mww 0xB8001000 0x92220000
+ # DDR2 : Prechare-All
+ mww 0x80000400 0x12345678
+
+ # ESD_ESDCTL0 : select Load-Mode-Register mode
+ mww 0xB8001000 0xB2220000
+ # DDR2 : Load reg EMR2
+ mwb 0x84000000 0xda
+ # DDR2 : Load reg EMR3
+ mwb 0x86000000 0xda
+ # DDR2 : Load reg EMR1 -- enable DLL
+ mwb 0x82000400 0xda
+ # DDR2 : Load reg MR -- reset DLL
+ mwb 0x80000333 0xda
+
+ # ESD_ESDCTL0 : select Prechare-All mode
+ mww 0xB8001000 0x92220000
+ # DDR2 : Prechare-All
+ mwb 0x80000400 0x12345678
+
+ # ESD_ESDCTL0 : select Manual-Refresh mode
+ mww 0xB8001000 0xA2220000
+ # DDR2 : Manual-Refresh 2 times
+ mww 0x80000000 0x87654321
+ mww 0x80000000 0x87654321
+
+ # ESD_ESDCTL0 : select Load-Mode-Register mode
+ mww 0xB8001000 0xB2220000
+ # DDR2 : Load reg MR -- CL=3, BL=8, end DLL reset
+ mwb 0x80000233 0xda
+ # DDR2 : Load reg EMR1 -- OCD default
+ mwb 0x82000780 0xda
+ # DDR2 : Load reg EMR1 -- OCD exit
+ mwb 0x82000400 0xda # ODT disabled
+
+ # ESD_ESDCTL0 : select normal-operation mode
+ # DSIZ=32-bit, BL=8, COL=10-bit, ROW=13-bit
+ # disable PWT & PRCT
+ # disable Auto-Refresh
+ mww 0xB8001000 0x82220080
+
+ ## ESD_ESDCTL0 : enable Auto-Refresh
+ mww 0xB8001000 0x82228080
+ ## ESD_ESDCTL1 : enable Auto-Refresh
+ mww 0xB8001008 0x00002000
+
+
+ #***********************************************
+ # Adjust the ESDCDLY5 register
+ #***********************************************
+ # Vary DQS_ABS_OFFSET5 for writes
+ mww 0xB8001020 0x00F48000 # this is the default value
+ mww 0xB8001024 0x00F48000 # this is the default value
+ mww 0xB8001028 0x00F48000 # this is the default value
+ mww 0xB800102c 0x00F48000 # this is the default value
+
+
+ #Then you can make force measure with the dedicated bit (Bit 7 at ESDMISC)
+ mww 0xB8001010 0x00000384
+ # wait a while
+ sleep 1000
+ # now clear the force measurement bit
+ mww 0xB8001010 0x00000304
+
+ # dummy write to DDR memory to set DQS low
+ mww 0x80000000 0x00000000
+
+ mww 0x30000100 0x0
+ mww 0x30000104 0x31024
+
+
+}
PACKAGE_VERSION="$(package_info_load_version)"
[ "${RELEASE_VERSION}" ] || \
- RELEASE_VERSION=${PACKAGE_VERSION/-in-development/}
+ RELEASE_VERSION=${PACKAGE_VERSION/-dev/}
[ "${PACKAGE_NAME}" -a "${PACKAGE_VERSION}" ] || \
die "package information is missing from configure script"
package_info_load
svn_setup_load
- [ "${PACKAGE_VERSION/in-development/}" = "${PACKAGE_VERSION}" ] || \
+ [ "${PACKAGE_VERSION/dev/}" = "${PACKAGE_VERSION}" ] || \
die "'${PACKAGE_NAME}-${PACKAGE_VERSION}' cannot be released"
[ "${PACKAGE_VERSION%.0}" = "${PACKAGE_VERSION}" ] || \
do_release_step_prep() {
- do_version tag remove in-development
+ do_version tag remove dev
# reset RELEASE_VERSION now to allow release version to be detected
export RELEASE_VERSION=
}
local TYPE="$1"
echo "Bump ${TYPE} version and add tag:"
do_version_bump ${TYPE}
- do_version_tag_add in-development
+ do_version_tag_add dev
}
do_release_step_branch() {
do_svn_switch "${PACKAGE_BRANCH}"
Code Review / openocd.git / commitdiff