tcl/board: add configuration for Novena's integrated FPGA 32/3532/3
authorSean Cross <xobs@kosagi.com>
Tue, 28 Jun 2016 09:12:34 +0000 (12:12 +0300)
committerAndreas Fritiofson <andreas.fritiofson@gmail.com>
Mon, 17 Oct 2016 08:14:17 +0000 (09:14 +0100)
Change-Id: Iecd57c0ef59cfde98de36464a73436f57b0835e2
Signed-off-by: Sean Cross <xobs@kosagi.com>
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3532
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
tcl/board/novena-internal-fpga.cfg [new file with mode: 0644]

diff --git a/tcl/board/novena-internal-fpga.cfg b/tcl/board/novena-internal-fpga.cfg
new file mode 100644 (file)
index 0000000..87495e3
--- /dev/null
@@ -0,0 +1,25 @@
+#
+# Novena open hardware and F/OSS-friendly computing platform
+#
+# Design documentation:
+# http://www.kosagi.com/w/index.php?title=Novena_PVT_Design_Source
+#
+# +-------------+--------------+------+-------+---------+
+# | Pad name    | Schematic    | GPIO | sysfs | JTAG    |
+# +-------------+--------------+------+-------+---------+
+# | DISP0_DAT13 | FPGA_RESET_N | 5-07 |  135  | RESET_N |
+# | DISP0_DAT14 | FPGA_TCK     | 5-08 |  136  | TCK     |
+# | DISP0_DAT15 | FPGA_TDI     | 5-09 |  137  | TDI     |
+# | DISP0_DAT16 | FPGA_TDO     | 5-10 |  138  | TDO     |
+# | DISP0_DAT17 | FPGA_TMS     | 5-11 |  139  | TMS     |
+# +-------------+--------------+------+-------+---------+
+
+interface sysfsgpio
+
+transport select jtag
+
+# TCK TMS TDI TDO
+sysfsgpio_jtag_nums 136 139 137 138
+
+source [find cpld/xilinx-xc6s.cfg]
+