target/armv7a_cache: add gdb keep-alive and fix a missing dpm finish 27/4627/2
authorAntonio Borneo <borneo.antonio@gmail.com>
Tue, 24 Jul 2018 08:17:57 +0000 (10:17 +0200)
committerMatthias Welwarsky <matthias@welwarsky.de>
Wed, 8 Aug 2018 09:36:28 +0000 (10:36 +0100)
Depending on range size, the loop on cache operations can take quite
some time, causing gdb to timeout.

Add keep-alive to prevent gdb to timeout.
Add also a missing dpm->finish() to balance dpm->prepare().

Change-Id: Ia87934b1ec19a0332bb50e3010b582381e5f3685
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4627
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
src/target/armv7a_cache.c

index 3e5f8d6..7435aab 100644 (file)
@@ -70,6 +70,7 @@ static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cach
 
        LOG_DEBUG("cl %" PRId32, cl);
        do {
+               keep_alive();
                c_way = size->way;
                do {
                        uint32_t value = (c_index << size->index_shift)
@@ -89,6 +90,7 @@ static int armv7a_l1_d_cache_flush_level(struct arm_dpm *dpm, struct armv7a_cach
        } while (c_index >= 0);
 
  done:
+       keep_alive();
        return retval;
 }
 
@@ -164,7 +166,7 @@ int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
        struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
        uint32_t linelen = armv7a_cache->dminline;
        uint32_t va_line, va_end;
-       int retval;
+       int retval, i = 0;
 
        retval = armv7a_l1_d_cache_sanity_check(target);
        if (retval != ERROR_OK)
@@ -198,6 +200,8 @@ int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
        }
 
        while (va_line < va_end) {
+               if ((i++ & 0x3f) == 0)
+                       keep_alive();
                /* DCIMVAC - Invalidate data cache line by VA to PoC. */
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV4_5_MCR(15, 0, 0, 7, 6, 1), va_line);
@@ -206,11 +210,13 @@ int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
                va_line += linelen;
        }
 
+       keep_alive();
        dpm->finish(dpm);
        return retval;
 
 done:
        LOG_ERROR("d-cache invalidate failed");
+       keep_alive();
        dpm->finish(dpm);
 
        return retval;
@@ -224,7 +230,7 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
        struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
        uint32_t linelen = armv7a_cache->dminline;
        uint32_t va_line, va_end;
-       int retval;
+       int retval, i = 0;
 
        retval = armv7a_l1_d_cache_sanity_check(target);
        if (retval != ERROR_OK)
@@ -238,6 +244,8 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
        va_end = virt + size;
 
        while (va_line < va_end) {
+               if ((i++ & 0x3f) == 0)
+                       keep_alive();
                /* DCCMVAC - Data Cache Clean by MVA to PoC */
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV4_5_MCR(15, 0, 0, 7, 10, 1), va_line);
@@ -246,11 +254,13 @@ int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
                va_line += linelen;
        }
 
+       keep_alive();
        dpm->finish(dpm);
        return retval;
 
 done:
        LOG_ERROR("d-cache invalidate failed");
+       keep_alive();
        dpm->finish(dpm);
 
        return retval;
@@ -264,7 +274,7 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
        struct armv7a_cache_common *armv7a_cache = &armv7a->armv7a_mmu.armv7a_cache;
        uint32_t linelen = armv7a_cache->dminline;
        uint32_t va_line, va_end;
-       int retval;
+       int retval, i = 0;
 
        retval = armv7a_l1_d_cache_sanity_check(target);
        if (retval != ERROR_OK)
@@ -278,6 +288,8 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
        va_end = virt + size;
 
        while (va_line < va_end) {
+               if ((i++ & 0x3f) == 0)
+                       keep_alive();
                /* DCCIMVAC */
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV4_5_MCR(15, 0, 0, 7, 14, 1), va_line);
@@ -286,11 +298,13 @@ int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
                va_line += linelen;
        }
 
+       keep_alive();
        dpm->finish(dpm);
        return retval;
 
 done:
        LOG_ERROR("d-cache invalidate failed");
+       keep_alive();
        dpm->finish(dpm);
 
        return retval;
@@ -342,7 +356,7 @@ int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
                                &armv7a->armv7a_mmu.armv7a_cache;
        uint32_t linelen = armv7a_cache->iminline;
        uint32_t va_line, va_end;
-       int retval;
+       int retval, i = 0;
 
        retval = armv7a_l1_i_cache_sanity_check(target);
        if (retval != ERROR_OK)
@@ -356,6 +370,8 @@ int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
        va_end = virt + size;
 
        while (va_line < va_end) {
+               if ((i++ & 0x3f) == 0)
+                       keep_alive();
                /* ICIMVAU - Invalidate instruction cache by VA to PoU. */
                retval = dpm->instr_write_data_r0(dpm,
                                ARMV4_5_MCR(15, 0, 0, 7, 5, 1), va_line);
@@ -368,10 +384,13 @@ int armv7a_l1_i_cache_inval_virt(struct target *target, uint32_t virt,
                        goto done;
                va_line += linelen;
        }
+       keep_alive();
+       dpm->finish(dpm);
        return retval;
 
 done:
        LOG_ERROR("i-cache invalidate failed");
+       keep_alive();
        dpm->finish(dpm);
 
        return retval;