build: cleanup src/target directory
authorSpencer Oliver <spen@spen-soft.co.uk>
Sun, 5 Feb 2012 12:03:04 +0000 (12:03 +0000)
committerSpencer Oliver <spen@spen-soft.co.uk>
Mon, 6 Feb 2012 11:00:36 +0000 (11:00 +0000)
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
107 files changed:
src/target/adi_v5_jtag.c
src/target/adi_v5_swd.c
src/target/algorithm.c
src/target/algorithm.h
src/target/arm.h
src/target/arm11.c
src/target/arm11.h
src/target/arm11_dbgtap.c
src/target/arm11_dbgtap.h
src/target/arm720t.c
src/target/arm720t.h
src/target/arm7_9_common.c
src/target/arm7_9_common.h
src/target/arm7tdmi.c
src/target/arm7tdmi.h
src/target/arm920t.c
src/target/arm920t.h
src/target/arm926ejs.c
src/target/arm926ejs.h
src/target/arm946e.c
src/target/arm946e.h
src/target/arm966e.c
src/target/arm966e.h
src/target/arm9tdmi.c
src/target/arm9tdmi.h
src/target/arm_adi_v5.c
src/target/arm_adi_v5.h
src/target/arm_disassembler.c
src/target/arm_disassembler.h
src/target/arm_dpm.c
src/target/arm_dpm.h
src/target/arm_jtag.c
src/target/arm_jtag.h
src/target/arm_opcodes.h
src/target/arm_semihosting.c
src/target/arm_simulator.c
src/target/arm_simulator.h
src/target/armv4_5.c
src/target/armv4_5.h
src/target/armv4_5_cache.c
src/target/armv4_5_cache.h
src/target/armv4_5_mmu.c
src/target/armv4_5_mmu.h
src/target/armv7a.c
src/target/armv7a.h
src/target/armv7m.c
src/target/armv7m.h
src/target/avr32_ap7k.c
src/target/avr32_ap7k.h
src/target/avr32_jtag.c
src/target/avr32_jtag.h
src/target/avr32_mem.c
src/target/avr32_mem.h
src/target/avr32_regs.c
src/target/avr32_regs.h
src/target/avrt.c
src/target/avrt.h
src/target/breakpoints.c
src/target/breakpoints.h
src/target/cortex_a.c
src/target/cortex_a.h
src/target/cortex_m.c
src/target/cortex_m.h
src/target/dsp563xx.c
src/target/dsp563xx.h
src/target/dsp563xx_once.c
src/target/dsp563xx_once.h
src/target/dsp5680xx.c
src/target/dsp5680xx.h
src/target/embeddedice.c
src/target/embeddedice.h
src/target/etb.c
src/target/etb.h
src/target/etm.c
src/target/etm.h
src/target/etm_dummy.c
src/target/etm_dummy.h
src/target/fa526.c
src/target/feroceon.c
src/target/image.c
src/target/image.h
src/target/mips32.c
src/target/mips32.h
src/target/mips32_dmaacc.c
src/target/mips32_dmaacc.h
src/target/mips32_pracc.c
src/target/mips32_pracc.h
src/target/mips_ejtag.c
src/target/mips_ejtag.h
src/target/mips_m4k.c
src/target/mips_m4k.h
src/target/oocd_trace.c
src/target/oocd_trace.h
src/target/register.c
src/target/register.h
src/target/smp.c
src/target/smp.h
src/target/stm32_stlink.c
src/target/target.c
src/target/target.h
src/target/target_request.c
src/target/target_request.h
src/target/target_type.h
src/target/trace.c
src/target/trace.h
src/target/xscale.c
src/target/xscale.h

index 75461c3..b6473b0 100644 (file)
@@ -40,7 +40,6 @@
 #include "arm_adi_v5.h"
 #include <helper/time_support.h>
 
-
 /* JTAG instructions/registers for JTAG-DP and SWJ-DP */
 #define JTAG_DP_ABORT          0x8
 #define JTAG_DP_DPACC          0xA
@@ -223,22 +222,19 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                        DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
        if (retval != ERROR_OK)
                return retval;
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
 
        dap->ack = dap->ack & 0x7;
 
        /* common code path avoids calling timeval_ms() */
-       if (dap->ack != JTAG_ACK_OK_FAULT)
-       {
+       if (dap->ack != JTAG_ACK_OK_FAULT) {
                long long then = timeval_ms();
 
-               while (dap->ack != JTAG_ACK_OK_FAULT)
-               {
-                       if (dap->ack == JTAG_ACK_WAIT)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
+               while (dap->ack != JTAG_ACK_OK_FAULT) {
+                       if (dap->ack == JTAG_ACK_WAIT) {
+                               if ((timeval_ms()-then) > 1000) {
                                        /* NOTE:  this would be a good spot
                                         * to use JTAG_DP_ABORT.
                                         */
@@ -247,9 +243,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                                                "in JTAG-DP transaction");
                                        return ERROR_JTAG_DEVICE_ERROR;
                                }
-                       }
-                       else
-                       {
+                       } else {
                                LOG_WARNING("Invalid ACK %#x "
                                                "in JTAG-DP transaction",
                                                dap->ack);
@@ -260,7 +254,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                                        DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
                        if (retval != ERROR_OK)
                                return retval;
-                       if ((retval = dap_run(dap)) != ERROR_OK)
+                       retval = dap_run(dap);
+                       if (retval != ERROR_OK)
                                return retval;
                        dap->ack = dap->ack & 0x7;
                }
@@ -269,18 +264,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
        /* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
 
        /* Check for STICKYERR and STICKYORUN */
-       if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
-       {
+       if (ctrlstat & (SSTICKYORUN | SSTICKYERR)) {
                LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
                /* Check power to debug regions */
-               if ((ctrlstat & 0xf0000000) != 0xf0000000)
-               {
+               if ((ctrlstat & 0xf0000000) != 0xf0000000) {
                        retval = ahbap_debugport_init(dap);
                        if (retval != ERROR_OK)
                                return retval;
-               }
-               else
-               {
+               } else {
                        uint32_t mem_ap_csw, mem_ap_tar;
 
                        /* Maybe print information about last intended
@@ -314,7 +305,8 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                                        DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
                        if (retval != ERROR_OK)
                                return retval;
-                       if ((retval = dap_run(dap)) != ERROR_OK)
+                       retval = dap_run(dap);
+                       if (retval != ERROR_OK)
                                return retval;
 
                        LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
@@ -329,13 +321,15 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                        if (retval != ERROR_OK)
                                return retval;
 
-                       if ((retval = dap_run(dap)) != ERROR_OK)
+                       retval = dap_run(dap);
+                       if (retval != ERROR_OK)
                                return retval;
                        LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
                                        PRIx32, mem_ap_csw, mem_ap_tar);
 
                }
-               if ((retval = dap_run(dap)) != ERROR_OK)
+               retval = dap_run(dap);
+               if (retval != ERROR_OK)
                        return retval;
                return ERROR_JTAG_DEVICE_ERROR;
        }
index 5a3570d..6af7748 100644 (file)
 
 #include <jtag/swd.h>
 
-
-
 static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
                uint32_t *data)
 {
-       // REVISIT status return vs ack ...
+       /* REVISIT status return vs ack ... */
        return swd->read_reg(swd_cmd(true,  false, reg), data);
 }
 
@@ -71,14 +69,14 @@ static int swd_queue_idcode_read(struct adiv5_dap *dap,
        if (status < 0)
                return status;
        *ack = status;
-       // ??
+       /* ?? */
        return ERROR_OK;
 }
 
 static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
                uint32_t data)
 {
-       // REVISIT status return vs ack ...
+       /* REVISIT status return vs ack ... */
        return swd->write_reg(swd_cmd(false,  false, reg), data);
 }
 
@@ -86,16 +84,16 @@ static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
 static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
                uint32_t *data)
 {
-       // REVISIT  APSEL ...
-       // REVISIT status return ...
+       /* REVISIT  APSEL ... */
+       /* REVISIT status return ... */
        return swd->read_reg(swd_cmd(true,  true, reg), data);
 }
 
 static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
                uint32_t data)
 {
-       // REVISIT  APSEL ...
-       // REVISIT status return ...
+       /* REVISIT  APSEL ... */
+       /* REVISIT status return ... */
        return swd->write_reg(swd_cmd(false,  true, reg), data);
 }
 
@@ -194,15 +192,14 @@ COMMAND_HANDLER(handle_swd_wcr)
        int retval;
        struct target *target = get_current_target(CMD_CTX);
        struct arm *arm = target_to_arm(target);
-struct adiv5_dap *dap = arm->dap;
+       struct adiv5_dap *dap = arm->dap;
        uint32_t wcr;
        unsigned trn, scale = 0;
 
-
        switch (CMD_ARGC) {
        /* no-args: just dump state */
        case 0:
-               //retval = swd_queue_dp_read(dap, DP_WCR, &wcr);
+               /*retval = swd_queue_dp_read(dap, DP_WCR, &wcr); */
                retval = dap_queue_dp_read(dap, DP_WCR, &wcr);
                if (retval == ERROR_OK)
                        dap->ops->run(dap);
@@ -315,11 +312,10 @@ static int swd_init(struct command_context *ctx)
 {
        struct target *target = get_current_target(ctx);
        struct arm *arm = target_to_arm(target);
-struct adiv5_dap *dap = arm->dap;
+       struct adiv5_dap *dap = arm->dap;
        uint32_t idcode;
        int status;
 
-
        /* FIXME validate transport config ... is the
         * configured DAP present (check IDCODE)?
         * Is *only* one DAP configured?
index 57383ae..0714144 100644 (file)
@@ -17,6 +17,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -24,7 +25,6 @@
 #include "algorithm.h"
 #include <helper/binarybuffer.h>
 
-
 void init_mem_param(struct mem_param *param, uint32_t address, uint32_t size, enum param_direction direction)
 {
        param->address = address;
index af1fd91..ecd1177 100644 (file)
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef ALGORITHM_H
 #define ALGORITHM_H
 
-enum param_direction
-{
+enum param_direction {
        PARAM_IN,
        PARAM_OUT,
        PARAM_IN_OUT
 };
 
-struct mem_param
-{
+struct mem_param {
        uint32_t address;
        uint32_t size;
        uint8_t *value;
        enum param_direction direction;
 };
 
-struct reg_param
-{
+struct reg_param {
        const char *reg_name;
        uint32_t size;
        uint8_t *value;
index 86cf447..ab7d85c 100644 (file)
@@ -23,6 +23,7 @@
  * Free Software Foundation, Inc.,
  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  */
+
 #ifndef ARM_H
 #define ARM_H
 
index da084b1..bb7b9c6 100644 (file)
@@ -38,7 +38,6 @@
 #include "register.h"
 #include "arm_opcodes.h"
 
-
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
@@ -56,8 +55,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 {
        CHECK_RETVAL(arm11_read_DSCR(arm11));
 
-       if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
-       {
+       if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
                LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
                LOG_DEBUG("Bringing target into debug mode");
 
@@ -68,8 +66,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 
                arm11->simulate_reset_on_next_halt = true;
 
-               if (arm11->dscr & DSCR_CORE_HALTED)
-               {
+               if (arm11->dscr & DSCR_CORE_HALTED) {
                        /** \todo TODO: this needs further scrutiny because
                          * arm11_debug_entry() never gets called.  (WHY NOT?)
                          * As a result we don't read the actual register states from
@@ -78,9 +75,7 @@ static int arm11_check_init(struct arm11_common *arm11)
 
                        arm11->arm.target->state = TARGET_HALTED;
                        arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
-               }
-               else
-               {
+               } else {
                        arm11->arm.target->state = TARGET_RUNNING;
                        arm11->arm.target->debug_reason = DBG_REASON_NOTHALTED;
                }
@@ -110,20 +105,20 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
        /* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
        arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
-       if (arm11->is_wdtr_saved)
-       {
+       if (arm11->is_wdtr_saved) {
                arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 
                arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-               struct scan_field       chain5_fields[3];
+               struct scan_field chain5_fields[3];
 
                arm11_setup_field(arm11, 32, NULL,
-                               &arm11->saved_wdtr, chain5_fields + 0);
-               arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 1);
-               arm11_setup_field(arm11,  1, NULL, NULL,                chain5_fields + 2);
+                       &arm11->saved_wdtr, chain5_fields + 0);
+               arm11_setup_field(arm11,  1, NULL, NULL, chain5_fields + 1);
+               arm11_setup_field(arm11,  1, NULL, NULL, chain5_fields + 2);
 
-               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                               chain5_fields), chain5_fields, TAP_DRPAUSE);
 
        }
 
@@ -143,10 +138,9 @@ static int arm11_debug_entry(struct arm11_common *arm11)
        /** \todo TODO: Test drain write buffer. */
 
 #if 0
-       while (1)
-       {
+       while (1) {
                /* MRC p14,0,R0,c5,c10,0 */
-               //      arm11_run_instr_no_data1(arm11, /*0xee150e1a*/0xe320f000);
+               /*      arm11_run_instr_no_data1(arm11, / *0xee150e1a* /0xe320f000); */
 
                /* mcr     15, 0, r0, cr7, cr10, {4} */
                arm11_run_instr_no_data1(arm11, 0xee070f9a);
@@ -155,8 +149,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
                LOG_DEBUG("DRAIN, DSCR %08x", dscr);
 
-               if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
-               {
+               if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT) {
                        arm11_run_instr_no_data1(arm11, 0xe320f000);
 
                        dscr = arm11_read_DSCR(arm11);
@@ -183,8 +176,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
        /* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
        arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
-       if (arm11->is_rdtr_saved)
-       {
+       if (arm11->is_rdtr_saved) {
                /* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
                retval = arm11_run_instr_data_from_core_via_r0(arm11,
                                0xEE100E15, &arm11->saved_rdtr);
@@ -196,8 +188,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
         * be MMU and cache state to care about ...
         */
 
-       if (arm11->simulate_reset_on_next_halt)
-       {
+       if (arm11->simulate_reset_on_next_halt) {
                arm11->simulate_reset_on_next_halt = false;
 
                LOG_DEBUG("Reset c1 Control Register");
@@ -255,8 +246,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
        {
                CHECK_RETVAL(arm11_read_DSCR(arm11));
 
-               if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
-               {
+               if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL)) {
                        /*
                        The wDTR/rDTR two registers that are used to send/receive data to/from
                        the core in tandem with corresponding instruction codes that are
@@ -265,14 +255,13 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
                        read out by the other side.
                        */
                        LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
-                                       (unsigned) arm11->dscr);
+                               (unsigned) arm11->dscr);
                        return ERROR_FAIL;
                }
        }
 
        /* maybe restore original wDTR */
-       if (arm11->is_wdtr_saved)
-       {
+       if (arm11->is_wdtr_saved) {
                retval = arm11_run_instr_data_prepare(arm11);
                if (retval != ERROR_OK)
                        return retval;
@@ -301,23 +290,23 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
        CHECK_RETVAL(arm11_write_DSCR(arm11, arm11->dscr));
 
        /* maybe restore rDTR */
-       if (arm11->is_rdtr_saved)
-       {
+       if (arm11->is_rdtr_saved) {
                arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 
                arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-               struct scan_field       chain5_fields[3];
+               struct scan_field chain5_fields[3];
 
-               uint8_t                 Ready           = 0;    /* ignored */
-               uint8_t                 Valid           = 0;    /* ignored */
+               uint8_t Ready           = 0;                    /* ignored */
+               uint8_t Valid           = 0;                    /* ignored */
 
                arm11_setup_field(arm11, 32, &arm11->saved_rdtr,
-                               NULL, chain5_fields + 0);
-               arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
-               arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
+                       NULL, chain5_fields + 0);
+               arm11_setup_field(arm11,  1, &Ready,    NULL, chain5_fields + 1);
+               arm11_setup_field(arm11,  1, &Valid,    NULL, chain5_fields + 2);
 
-               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                               chain5_fields), chain5_fields, TAP_DRPAUSE);
        }
 
        /* now processor is ready to RESTART */
@@ -333,10 +322,8 @@ static int arm11_poll(struct target *target)
 
        CHECK_RETVAL(arm11_check_init(arm11));
 
-       if (arm11->dscr & DSCR_CORE_HALTED)
-       {
-               if (target->state != TARGET_HALTED)
-               {
+       if (arm11->dscr & DSCR_CORE_HALTED) {
+               if (target->state != TARGET_HALTED) {
                        enum target_state old_state = target->state;
 
                        LOG_DEBUG("enter TARGET_HALTED");
@@ -346,17 +333,14 @@ static int arm11_poll(struct target *target)
 
                        target_call_event_callbacks(target,
                                (old_state == TARGET_DEBUG_RUNNING)
-                                       ? TARGET_EVENT_DEBUG_HALTED
-                                       : TARGET_EVENT_HALTED);
+                               ? TARGET_EVENT_DEBUG_HALTED
+                               : TARGET_EVENT_HALTED);
                }
-       }
-       else
-       {
-               if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
-               {
+       } else {
+               if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) {
                        LOG_DEBUG("enter TARGET_RUNNING");
-                       target->state                   = TARGET_RUNNING;
-                       target->debug_reason    = DBG_REASON_NOTHALTED;
+                       target->state                   = TARGET_RUNNING;
+                       target->debug_reason    = DBG_REASON_NOTHALTED;
                }
        }
 
@@ -374,14 +358,14 @@ static int arm11_arch_state(struct target *target)
 
        if (target->debug_reason == DBG_REASON_WATCHPOINT)
                LOG_USER("Watchpoint triggered at PC %#08x",
-                               (unsigned) arm11->dpm.wp_pc);
+                       (unsigned) arm11->dpm.wp_pc);
 
        return retval;
 }
 
 /* target request support */
 static int arm11_target_request_data(struct target *target,
-               uint32_t size, uint8_t *buffer)
+       uint32_t size, uint8_t *buffer)
 {
        LOG_WARNING("Not implemented: %s", __func__);
 
@@ -397,12 +381,9 @@ static int arm11_halt(struct target *target)
                target_state_name(target));
 
        if (target->state == TARGET_UNKNOWN)
-       {
                arm11->simulate_reset_on_next_halt = true;
-       }
 
-       if (target->state == TARGET_HALTED)
-       {
+       if (target->state == TARGET_HALTED) {
                LOG_DEBUG("target was already halted");
                return ERROR_OK;
        }
@@ -413,8 +394,7 @@ static int arm11_halt(struct target *target)
 
        int i = 0;
 
-       while (1)
-       {
+       while (1) {
                CHECK_RETVAL(arm11_read_DSCR(arm11));
 
                if (arm11->dscr & DSCR_CORE_HALTED)
@@ -423,13 +403,9 @@ static int arm11_halt(struct target *target)
 
                long long then = 0;
                if (i == 1000)
-               {
                        then = timeval_ms();
-               }
-               if (i >= 1000)
-               {
-                       if ((timeval_ms()-then) > 1000)
-                       {
+               if (i >= 1000) {
+                       if ((timeval_ms()-then) > 1000) {
                                LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
                                return ERROR_FAIL;
                        }
@@ -437,19 +413,19 @@ static int arm11_halt(struct target *target)
                i++;
        }
 
-       enum target_state old_state     = target->state;
+       enum target_state old_state     = target->state;
 
        CHECK_RETVAL(arm11_debug_entry(arm11));
 
        CHECK_RETVAL(
                target_call_event_callbacks(target,
-                       old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
+                       old_state ==
+                       TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
 
        return ERROR_OK;
 }
 
-static uint32_t
-arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
+static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 {
        void *value = arm11->arm.pc->value;
 
@@ -462,10 +438,10 @@ arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
 }
 
 static int arm11_resume(struct target *target, int current,
-               uint32_t address, int handle_breakpoints, int debug_execution)
+       uint32_t address, int handle_breakpoints, int debug_execution)
 {
-       //        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d",
-       //      current, address, handle_breakpoints, debug_execution);
+       /*        LOG_DEBUG("current %d  address %08x  handle_breakpoints %d  debug_execution %d", */
+       /*      current, address, handle_breakpoints, debug_execution); */
 
        struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -473,8 +449,7 @@ static int arm11_resume(struct target *target, int current,
                target_state_name(target));
 
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_ERROR("Target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -493,10 +468,8 @@ static int arm11_resume(struct target *target, int current,
        if (handle_breakpoints) {
                struct breakpoint *bp;
 
-               for (bp = target->breakpoints; bp; bp = bp->next)
-               {
-                       if (bp->address == address)
-                       {
+               for (bp = target->breakpoints; bp; bp = bp->next) {
+                       if (bp->address == address) {
                                LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
                                arm11_step(target, 1, 0, 0);
                                break;
@@ -509,21 +482,22 @@ static int arm11_resume(struct target *target, int current,
                struct breakpoint *bp;
                unsigned brp_num = 0;
 
-               for (bp = target->breakpoints; bp; bp = bp->next)
-               {
-                       struct arm11_sc7_action brp[2];
+               for (bp = target->breakpoints; bp; bp = bp->next) {
+                       struct arm11_sc7_action brp[2];
 
-                       brp[0].write    = 1;
-                       brp[0].address  = ARM11_SC7_BVR0 + brp_num;
-                       brp[0].value    = bp->address;
-                       brp[1].write    = 1;
-                       brp[1].address  = ARM11_SC7_BCR0 + brp_num;
-                       brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+                       brp[0].write    = 1;
+                       brp[0].address  = ARM11_SC7_BVR0 + brp_num;
+                       brp[0].value    = bp->address;
+                       brp[1].write    = 1;
+                       brp[1].address  = ARM11_SC7_BCR0 + brp_num;
+                       brp[1].value    = 0x1 |
+                               (3 <<
+                                1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 
                        CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
 
                        LOG_DEBUG("Add BP %d at %08" PRIx32, brp_num,
-                                       bp->address);
+                               bp->address);
 
                        brp_num++;
                }
@@ -540,8 +514,7 @@ static int arm11_resume(struct target *target, int current,
        CHECK_RETVAL(jtag_execute_queue());
 
        int i = 0;
-       while (1)
-       {
+       while (1) {
                CHECK_RETVAL(arm11_read_DSCR(arm11));
 
                LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
@@ -552,13 +525,9 @@ static int arm11_resume(struct target *target, int current,
 
                long long then = 0;
                if (i == 1000)
-               {
                        then = timeval_ms();
-               }
-               if (i >= 1000)
-               {
-                       if ((timeval_ms()-then) > 1000)
-                       {
+               if (i >= 1000) {
+                       if ((timeval_ms()-then) > 1000) {
                                LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
                                return ERROR_FAIL;
                        }
@@ -577,13 +546,12 @@ static int arm11_resume(struct target *target, int current,
 }
 
 static int arm11_step(struct target *target, int current,
-               uint32_t address, int handle_breakpoints)
+       uint32_t address, int handle_breakpoints)
 {
        LOG_DEBUG("target->state: %s",
                target_state_name(target));
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target was not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -597,30 +565,25 @@ static int arm11_step(struct target *target, int current,
 
        /** \todo TODO: Thumb not supported here */
 
-       uint32_t        next_instruction;
+       uint32_t next_instruction;
 
        CHECK_RETVAL(arm11_read_memory_word(arm11, address, &next_instruction));
 
        /* skip over BKPT */
-       if ((next_instruction & 0xFFF00070) == 0xe1200070)
-       {
+       if ((next_instruction & 0xFFF00070) == 0xe1200070) {
                address = arm11_nextpc(arm11, 0, address + 4);
                LOG_DEBUG("Skipping BKPT %08" PRIx32, address);
        }
-       /* skip over Wait for interrupt / Standby */
-       /* mcr  15, 0, r?, cr7, cr0, {4} */
-       else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90)
-       {
+       /* skip over Wait for interrupt / Standby
+        * mcr  15, 0, r?, cr7, cr0, {4} */
+       else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
                address = arm11_nextpc(arm11, 0, address + 4);
                LOG_DEBUG("Skipping WFI %08" PRIx32, address);
        }
        /* ignore B to self */
        else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
-       {
                LOG_DEBUG("Not stepping jump to self");
-       }
-       else
-       {
+       else {
                /** \todo TODO: check if break-/watchpoints make any sense at all in combination
                * with this. */
 
@@ -630,15 +593,14 @@ static int arm11_step(struct target *target, int current,
 
                /* Set up breakpoint for stepping */
 
-               struct arm11_sc7_action brp[2];
+               struct arm11_sc7_action brp[2];
 
-               brp[0].write    = 1;
-               brp[0].address  = ARM11_SC7_BVR0;
-               brp[1].write    = 1;
-               brp[1].address  = ARM11_SC7_BCR0;
+               brp[0].write    = 1;
+               brp[0].address  = ARM11_SC7_BVR0;
+               brp[1].write    = 1;
+               brp[1].address  = ARM11_SC7_BCR0;
 
-               if (arm11->hardware_step)
-               {
+               if (arm11->hardware_step) {
                        /* Hardware single stepping ("instruction address
                         * mismatch") is used if enabled.  It's not quite
                         * exactly "run one instruction"; "branch to here"
@@ -651,12 +613,11 @@ static int arm11_step(struct target *target, int current,
                         * FIXME Thumb stepping likely needs to use 0x03
                         * or 0xc0 byte masks, not 0x0f.
                         */
-                        brp[0].value   = address;
-                        brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
-                                       | (0 << 14) | (0 << 16) | (0 << 20)
-                                       | (2 << 21);
-               } else
-               {
+                       brp[0].value   = address;
+                       brp[1].value   = 0x1 | (3 << 1) | (0x0F << 5)
+                               | (0 << 14) | (0 << 16) | (0 << 20)
+                               | (2 << 21);
+               } else {
                        /* Sets a breakpoint on the next PC, as calculated
                         * by instruction set simulation.
                         *
@@ -670,10 +631,10 @@ static int arm11_step(struct target *target, int current,
                        if (retval != ERROR_OK)
                                return retval;
 
-                       brp[0].value    = next_pc;
-                       brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
-                                       | (0 << 14) | (0 << 16) | (0 << 20)
-                                       | (0 << 21);
+                       brp[0].value    = next_pc;
+                       brp[1].value    = 0x1 | (3 << 1) | (0x0F << 5)
+                               | (0 << 14) | (0 << 16) | (0 << 20)
+                               | (0 << 21);
                }
 
                CHECK_RETVAL(arm11_sc7_run(arm11, brp, ARRAY_SIZE(brp)));
@@ -697,10 +658,9 @@ static int arm11_step(struct target *target, int current,
                /* wait for halt */
                int i = 0;
 
-               while (1)
-               {
+               while (1) {
                        const uint32_t mask = DSCR_CORE_RESTARTED
-                                       | DSCR_CORE_HALTED;
+                               | DSCR_CORE_HALTED;
 
                        CHECK_RETVAL(arm11_read_DSCR(arm11));
                        LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
@@ -710,14 +670,11 @@ static int arm11_step(struct target *target, int current,
 
                        long long then = 0;
                        if (i == 1000)
-                       {
                                then = timeval_ms();
-                       }
-                       if (i >= 1000)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
-                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                       if (i >= 1000) {
+                               if ((timeval_ms()-then) > 1000) {
+                                       LOG_WARNING(
+                                               "Timeout (1000ms) waiting for instructions to complete");
                                        return ERROR_FAIL;
                                }
                        }
@@ -751,9 +708,9 @@ static int arm11_assert_reset(struct target *target)
                CHECK_RETVAL(arm11_sc7_set_vcr(arm11, arm11->vcr | 1));
 
        /* Issue some kind of warm reset. */
-       if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+       if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
                target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
-       else if (jtag_get_reset_config() & RESET_HAS_SRST) {
+       else if (jtag_get_reset_config() & RESET_HAS_SRST) {
                /* REVISIT handle "pulls" cases, if there's
                 * hardware that needs them to work.
                 */
@@ -800,8 +757,9 @@ static int arm11_deassert_reset(struct target *target)
        if (target->reset_halt) {
                if (target->state != TARGET_HALTED) {
                        LOG_WARNING("%s: ran after reset and before halt ...",
-                                       target_name(target));
-                       if ((retval = target_halt(target)) != ERROR_OK)
+                               target_name(target));
+                       retval = target_halt(target);
+                       if (retval != ERROR_OK)
                                return retval;
                }
        }
@@ -829,19 +787,22 @@ static int arm11_soft_reset_halt(struct target *target)
  * read memory address for some peripheral.
  */
 static int arm11_read_memory_inner(struct target *target,
-               uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
-               bool arm11_config_memrw_no_increment)
+       uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
+       bool arm11_config_memrw_no_increment)
 {
-       /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
+       /** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment
+        *problems */
        int retval;
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target was not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
+       LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
+               address,
+               size,
+               count);
 
        struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -854,36 +815,33 @@ static int arm11_read_memory_inner(struct target *target,
        if (retval != ERROR_OK)
                return retval;
 
-       switch (size)
-       {
-       case 1:
-               arm11->arm.core_cache->reg_list[1].dirty = true;
+       switch (size) {
+               case 1:
+                       arm11->arm.core_cache->reg_list[1].dirty = true;
 
-               for (size_t i = 0; i < count; i++)
-               {
-                       /* ldrb    r1, [r0], #1 */
-                       /* ldrb    r1, [r0] */
-                       CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
-                                       !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
+                       for (size_t i = 0; i < count; i++) {
+                               /* ldrb    r1, [r0], #1 */
+                               /* ldrb    r1, [r0] */
+                               CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
+                                               !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000));
 
-                       uint32_t res;
-                       /* MCR p14,0,R1,c0,c5,0 */
-                       CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
+                               uint32_t res;
+                               /* MCR p14,0,R1,c0,c5,0 */
+                               CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1));
 
-                       *buffer++ = res;
-               }
+                               *buffer++ = res;
+                       }
 
-               break;
+                       break;
 
-       case 2:
+               case 2:
                {
                        arm11->arm.core_cache->reg_list[1].dirty = true;
 
-                       for (size_t i = 0; i < count; i++)
-                       {
+                       for (size_t i = 0; i < count; i++) {
                                /* ldrh    r1, [r0], #2 */
                                CHECK_RETVAL(arm11_run_instr_no_data1(arm11,
-                                       !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
+                                               !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0));
 
                                uint32_t res;
 
@@ -897,23 +855,27 @@ static int arm11_read_memory_inner(struct target *target,
                        break;
                }
 
-       case 4:
+               case 4:
                {
-               uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
-               /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
-               uint32_t *words = (uint32_t *)(void *)buffer;
-
-               /* LDC p14,c5,[R0],#4 */
-               /* LDC p14,c5,[R0] */
-               CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
-               break;
+                       uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+                       /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+                       uint32_t *words = (uint32_t *)(void *)buffer;
+
+                       /* LDC p14,c5,[R0],#4 */
+                       /* LDC p14,c5,[R0] */
+                       CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, instr, words, count));
+                       break;
                }
        }
 
        return arm11_run_instr_data_finish(arm11);
 }
 
-static int arm11_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int arm11_read_memory(struct target *target,
+       uint32_t address,
+       uint32_t size,
+       uint32_t count,
+       uint8_t *buffer)
 {
        return arm11_read_memory_inner(target, address, size, count, buffer, false);
 }
@@ -924,19 +886,21 @@ static int arm11_read_memory(struct target *target, uint32_t address, uint32_t s
 * read memory address for some peripheral.
 */
 static int arm11_write_memory_inner(struct target *target,
-               uint32_t address, uint32_t size,
-               uint32_t count, const uint8_t *buffer,
-               bool no_increment)
+       uint32_t address, uint32_t size,
+       uint32_t count, const uint8_t *buffer,
+       bool no_increment)
 {
        int retval;
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target was not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
+       LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
+               address,
+               size,
+               count);
 
        struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -944,8 +908,8 @@ static int arm11_write_memory_inner(struct target *target,
        if (retval != ERROR_OK)
                return retval;
 
-       /* load r0 with buffer address */
-       /* MRC p14,0,r0,c0,c5,0 */
+       /* load r0 with buffer address
+        * MRC p14,0,r0,c0,c5,0 */
        retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
        if (retval != ERROR_OK)
                return retval;
@@ -959,14 +923,12 @@ static int arm11_write_memory_inner(struct target *target,
         */
        bool burst = arm11->memwrite_burst && (count > 1);
 
-       switch (size)
-       {
-       case 1:
+       switch (size) {
+               case 1:
                {
                        arm11->arm.core_cache->reg_list[1].dirty = true;
 
-                       for (size_t i = 0; i < count; i++)
-                       {
+                       for (size_t i = 0; i < count; i++) {
                                /* load r1 from DCC with byte data */
                                /* MRC p14,0,r1,c0,c5,0 */
                                retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
@@ -977,9 +939,7 @@ static int arm11_write_memory_inner(struct target *target,
                                /* strb    r1, [r0], #1 */
                                /* strb    r1, [r0] */
                                retval = arm11_run_instr_no_data1(arm11,
-                                       !no_increment
-                                               ? 0xe4c01001
-                                               : 0xe5c01000);
+                                               !no_increment ? 0xe4c01001 : 0xe5c01000);
                                if (retval != ERROR_OK)
                                        return retval;
                        }
@@ -987,12 +947,11 @@ static int arm11_write_memory_inner(struct target *target,
                        break;
                }
 
-       case 2:
+               case 2:
                {
                        arm11->arm.core_cache->reg_list[1].dirty = true;
 
-                       for (size_t i = 0; i < count; i++)
-                       {
+                       for (size_t i = 0; i < count; i++) {
                                uint16_t value;
                                memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
 
@@ -1006,9 +965,7 @@ static int arm11_write_memory_inner(struct target *target,
                                /* strh    r1, [r0], #2 */
                                /* strh    r1, [r0] */
                                retval = arm11_run_instr_no_data1(arm11,
-                                       !no_increment
-                                               ? 0xe0c010b2
-                                               : 0xe1c010b0);
+                                               !no_increment ? 0xe0c010b2 : 0xe1c010b0);
                                if (retval != ERROR_OK)
                                        return retval;
                        }
@@ -1016,35 +973,34 @@ static int arm11_write_memory_inner(struct target *target,
                        break;
                }
 
-       case 4: {
-               /* stream word data through DCC directly to memory */
-               /* increment:           STC p14,c5,[R0],#4 */
-               /* no increment:        STC p14,c5,[R0]*/
-               uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
+               case 4: {
+                       /* stream word data through DCC directly to memory */
+                       /* increment:           STC p14,c5,[R0],#4 */
+                       /* no increment:        STC p14,c5,[R0]*/
+                       uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
 
-               /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
-               uint32_t *words = (uint32_t*)(void *)buffer;
+                       /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
+                       uint32_t *words = (uint32_t *)(void *)buffer;
 
-               /* "burst" here just means trusting each instruction executes
-                * fully before we run the next one:  per-word roundtrips, to
-                * check the Ready flag, are not used.
-                */
-               if (!burst)
-                       retval = arm11_run_instr_data_to_core(arm11,
-                                       instr, words, count);
-               else
-                       retval = arm11_run_instr_data_to_core_noack(arm11,
-                                       instr, words, count);
-               if (retval != ERROR_OK)
-                       return retval;
+                       /* "burst" here just means trusting each instruction executes
+                        * fully before we run the next one:  per-word roundtrips, to
+                        * check the Ready flag, are not used.
+                        */
+                       if (!burst)
+                               retval = arm11_run_instr_data_to_core(arm11,
+                                               instr, words, count);
+                       else
+                               retval = arm11_run_instr_data_to_core_noack(arm11,
+                                               instr, words, count);
+                       if (retval != ERROR_OK)
+                               return retval;
 
-               break;
-       }
+                       break;
+               }
        }
 
        /* r0 verification */
-       if (!no_increment)
-       {
+       if (!no_increment) {
                uint32_t r0;
 
                /* MCR p14,0,R0,c0,c5,0 */
@@ -1052,15 +1008,16 @@ static int arm11_write_memory_inner(struct target *target,
                if (retval != ERROR_OK)
                        return retval;
 
-               if (address + size * count != r0)
-               {
+               if (address + size * count != r0) {
                        LOG_ERROR("Data transfer failed. Expected end "
-                                       "address 0x%08x, got 0x%08x",
-                                       (unsigned) (address + size * count),
-                                       (unsigned) r0);
+                               "address 0x%08x, got 0x%08x",
+                               (unsigned) (address + size * count),
+                               (unsigned) r0);
 
                        if (burst)
-                               LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
+                               LOG_ERROR(
+                                       "use 'arm11 memwrite burst disable' to disable fast burst mode");
+
 
                        if (arm11->memwrite_error_fatal)
                                return ERROR_FAIL;
@@ -1071,22 +1028,21 @@ static int arm11_write_memory_inner(struct target *target,
 }
 
 static int arm11_write_memory(struct target *target,
-               uint32_t address, uint32_t size,
-               uint32_t count, const uint8_t *buffer)
+       uint32_t address, uint32_t size,
+       uint32_t count, const uint8_t *buffer)
 {
        /* pointer increment matters only for multi-unit writes ...
         * not e.g. to a "reset the chip" controller.
         */
        return arm11_write_memory_inner(target, address, size,
-                       count, buffer, count == 1);
+               count, buffer, count == 1);
 }
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 static int arm11_bulk_write_memory(struct target *target,
-               uint32_t address, uint32_t count, const uint8_t *buffer)
+       uint32_t address, uint32_t count, const uint8_t *buffer)
 {
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target was not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -1098,26 +1054,23 @@ static int arm11_bulk_write_memory(struct target *target,
 * rw: 0 = write, 1 = read, 2 = access
 */
 static int arm11_add_breakpoint(struct target *target,
-               struct breakpoint *breakpoint)
+       struct breakpoint *breakpoint)
 {
        struct arm11_common *arm11 = target_to_arm11(target);
 
 #if 0
-       if (breakpoint->type == BKPT_SOFT)
-       {
+       if (breakpoint->type == BKPT_SOFT) {
                LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 #endif
 
-       if (!arm11->free_brps)
-       {
+       if (!arm11->free_brps) {
                LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 
-       if (breakpoint->length != 4)
-       {
+       if (breakpoint->length != 4) {
                LOG_DEBUG("only breakpoints of four bytes length supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
@@ -1128,7 +1081,7 @@ static int arm11_add_breakpoint(struct target *target,
 }
 
 static int arm11_remove_breakpoint(struct target *target,
-               struct breakpoint *breakpoint)
+       struct breakpoint *breakpoint)
 {
        struct arm11_common *arm11 = target_to_arm11(target);
 
@@ -1144,8 +1097,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
        if (target->tap == NULL)
                return ERROR_FAIL;
 
-       if (target->tap->ir_length != 5)
-       {
+       if (target->tap->ir_length != 5) {
                LOG_ERROR("'target arm11' expects IR LENGTH = 5");
                return ERROR_COMMAND_SYNTAX_ERROR;
        }
@@ -1169,7 +1121,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
 }
 
 static int arm11_init_target(struct command_context *cmd_ctx,
-               struct target *target)
+       struct target *target)
 {
        /* Initialize anything we can set up without talking to the target */
        return ERROR_OK;
@@ -1190,7 +1142,7 @@ static int arm11_examine(struct target *target)
 
        arm11_add_IR(arm11, ARM11_IDCODE, ARM11_TAP_DEFAULT);
 
-       struct scan_field               idcode_field;
+       struct scan_field idcode_field;
 
        arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
 
@@ -1202,46 +1154,46 @@ static int arm11_examine(struct target *target)
 
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field               chain0_fields[2];
+       struct scan_field chain0_fields[2];
 
        arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
        arm11_setup_field(arm11,  8, NULL, &implementor, chain0_fields + 1);
 
-       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
+       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                       chain0_fields), chain0_fields, TAP_IDLE);
 
        CHECK_RETVAL(jtag_execute_queue());
 
        /* assume the manufacturer id is ok; check the part # */
-       switch ((device_id >> 12) & 0xFFFF)
-       {
-       case 0x7B36:
-               type = "ARM1136";
-               break;
-       case 0x7B37:
-               type = "ARM11 MPCore";
-               break;
-       case 0x7B56:
-               type = "ARM1156";
-               break;
-       case 0x7B76:
-               arm11->arm.core_type = ARM_MODE_MON;
-               /* NOTE: could default arm11->hardware_step to true */
-               type = "ARM1176";
-               break;
-       default:
-               LOG_ERROR("unexpected ARM11 ID code");
-               return ERROR_FAIL;
+       switch ((device_id >> 12) & 0xFFFF) {
+               case 0x7B36:
+                       type = "ARM1136";
+                       break;
+               case 0x7B37:
+                       type = "ARM11 MPCore";
+                       break;
+               case 0x7B56:
+                       type = "ARM1156";
+                       break;
+               case 0x7B76:
+                       arm11->arm.core_type = ARM_MODE_MON;
+                       /* NOTE: could default arm11->hardware_step to true */
+                       type = "ARM1176";
+                       break;
+               default:
+                       LOG_ERROR("unexpected ARM11 ID code");
+                       return ERROR_FAIL;
        }
        LOG_INFO("found %s", type);
 
        /* unlikely this could ever fail, but ... */
        switch ((didr >> 16) & 0x0F) {
-       case ARM11_DEBUG_V6:
-       case ARM11_DEBUG_V61:           /* supports security extensions */
-               break;
-       default:
-               LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
-               return ERROR_FAIL;
+               case ARM11_DEBUG_V6:
+               case ARM11_DEBUG_V61:   /* supports security extensions */
+                       break;
+               default:
+                       LOG_ERROR("Only ARM v6 and v6.1 debug supported.");
+                       return ERROR_FAIL;
        }
 
        arm11->brp = ((didr >> 24) & 0x0F) + 1;
@@ -1250,7 +1202,7 @@ static int arm11_examine(struct target *target)
        arm11->free_brps = arm11->brp;
 
        LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32,
-                       device_id, implementor, didr);
+               device_id, implementor, didr);
 
        /* as a side-effect this reads DSCR and thus
         * clears the ARM11_DSCR_STICKY_PRECISE_DATA_ABORT / Sticky Precise Data Abort Flag
@@ -1271,7 +1223,7 @@ static int arm11_examine(struct target *target)
        if (arm11->arm.etm && !target_was_examined(target)) {
                *register_get_last_cache_p(&target->reg_cache) =
                        etm_build_reg_cache(target, &arm11->jtag_info,
-                                       arm11->arm.etm);
+                               arm11->arm.etm);
                CHECK_RETVAL(etm_setup(target));
        }
 
@@ -1280,15 +1232,14 @@ static int arm11_examine(struct target *target)
        return ERROR_OK;
 }
 
-
 #define ARM11_BOOL_WRAPPER(name, print_name)   \
-       COMMAND_HANDLER(arm11_handle_bool_##name) \
+       COMMAND_HANDLER(arm11_handle_bool_ ## name) \
        { \
                struct target *target = get_current_target(CMD_CTX); \
                struct arm11_common *arm11 = target_to_arm11(target); \
                \
                return CALL_COMMAND_HANDLER(handle_command_parse_bool, \
-                               &arm11->name, print_name); \
+                       &arm11->name, print_name); \
        }
 
 ARM11_BOOL_WRAPPER(memwrite_burst, "memory write burst mode")
@@ -1306,13 +1257,13 @@ COMMAND_HANDLER(arm11_handle_vcr)
        struct arm11_common *arm11 = target_to_arm11(target);
 
        switch (CMD_ARGC) {
-       case 0:
-               break;
-       case 1:
-               COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
-               break;
-       default:
-               return ERROR_COMMAND_SYNTAX_ERROR;
+               case 0:
+                       break;
+               case 1:
+                       COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr);
+                       break;
+               default:
+                       return ERROR_COMMAND_SYNTAX_ERROR;
        }
 
        LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
@@ -1395,38 +1346,38 @@ static const struct command_registration arm11_command_handlers[] = {
 
 /** Holds methods for ARM11xx targets. */
 struct target_type arm11_target = {
-       .name =                 "arm11",
+       .name = "arm11",
 
-       .poll =                 arm11_poll,
-       .arch_state =           arm11_arch_state,
+       .poll = arm11_poll,
+       .arch_state = arm11_arch_state,
 
-       .target_request_data =  arm11_target_request_data,
+       .target_request_data = arm11_target_request_data,
 
-       .halt =                 arm11_halt,
-       .resume =               arm11_resume,
-       .step =                 arm11_step,
+       .halt = arm11_halt,
+       .resume = arm11_resume,
+       .step = arm11_step,
 
-       .assert_reset =         arm11_assert_reset,
-       .deassert_reset =       arm11_deassert_reset,
-       .soft_reset_halt =      arm11_soft_reset_halt,
+       .assert_reset = arm11_assert_reset,
+       .deassert_reset = arm11_deassert_reset,
+       .soft_reset_halt = arm11_soft_reset_halt,
 
-       .get_gdb_reg_list =     arm_get_gdb_reg_list,
+       .get_gdb_reg_list = arm_get_gdb_reg_list,
 
-       .read_memory =          arm11_read_memory,
-       .write_memory =         arm11_write_memory,
+       .read_memory = arm11_read_memory,
+       .write_memory = arm11_write_memory,
 
-       .bulk_write_memory =    arm11_bulk_write_memory,
+       .bulk_write_memory = arm11_bulk_write_memory,
 
-       .checksum_memory =      arm_checksum_memory,
-       .blank_check_memory =   arm_blank_check_memory,
+       .checksum_memory = arm_checksum_memory,
+       .blank_check_memory = arm_blank_check_memory,
 
-       .add_breakpoint =       arm11_add_breakpoint,
-       .remove_breakpoint =    arm11_remove_breakpoint,
+       .add_breakpoint = arm11_add_breakpoint,
+       .remove_breakpoint = arm11_remove_breakpoint,
 
-       .run_algorithm =        armv4_5_run_algorithm,
+       .run_algorithm = armv4_5_run_algorithm,
 
-       .commands =             arm11_command_handlers,
-       .target_create =        arm11_target_create,
-       .init_target =          arm11_init_target,
-       .examine =              arm11_examine,
+       .commands = arm11_command_handlers,
+       .target_create = arm11_target_create,
+       .init_target = arm11_init_target,
+       .examine = arm11_examine,
 };
index 9edadee..fd7af15 100644 (file)
 #include "arm.h"
 #include "arm_dpm.h"
 
-#define ARM11_TAP_DEFAULT                      TAP_INVALID
+#define ARM11_TAP_DEFAULT                       TAP_INVALID
 
 #define CHECK_RETVAL(action)                   \
        do {                                    \
                int __retval = (action);        \
                if (__retval != ERROR_OK) {     \
                        LOG_DEBUG("error while calling \"%s\"", \
-                               # action );     \
+                               # action);     \
                        return __retval;        \
                }                               \
        } while (0)
 
 /* bits from ARMv7 DIDR */
-enum arm11_debug_version
-{
-       ARM11_DEBUG_V6                  = 0x01,
-       ARM11_DEBUG_V61                 = 0x02,
-       ARM11_DEBUG_V7                  = 0x03,
-       ARM11_DEBUG_V7_CP14             = 0x04,
+enum arm11_debug_version {
+       ARM11_DEBUG_V6                  = 0x01,
+       ARM11_DEBUG_V61                 = 0x02,
+       ARM11_DEBUG_V7                  = 0x03,
+       ARM11_DEBUG_V7_CP14             = 0x04,
 };
 
-struct arm11_common
-{
-       struct arm      arm;
+struct arm11_common {
+       struct arm arm;
 
        /** Debug module state. */
        struct arm_dpm dpm;
        struct arm11_sc7_action *bpwp_actions;
        unsigned bpwp_n;
 
-       size_t  brp;                    /**< Number of Breakpoint Register Pairs from DIDR      */
-       size_t  free_brps;              /**< Number of breakpoints allocated */
+       size_t brp;                     /**< Number of Breakpoint Register Pairs from DIDR      */
+       size_t free_brps;               /**< Number of breakpoints allocated */
 
        uint32_t dscr;                  /**< Last retrieved DSCR value. */
 
@@ -67,7 +65,7 @@ struct arm11_common
        bool is_rdtr_saved;
        bool is_wdtr_saved;
 
-       bool    simulate_reset_on_next_halt;    /**< Perform cleanups of the ARM state on next halt */
+       bool simulate_reset_on_next_halt;       /**< Perform cleanups of the ARM state on next halt **/
 
        /* Per-core configurable options.
         * NOTE that several of these boolean options should not exist
@@ -86,8 +84,7 @@ struct arm11_common
 
 static inline struct arm11_common *target_to_arm11(struct target *target)
 {
-       return container_of(target->arch_info, struct arm11_common,
-                       arm);
+       return container_of(target->arch_info, struct arm11_common, arm);
 }
 
 /**
@@ -95,27 +92,25 @@ static inline struct arm11_common *target_to_arm11(struct target *target)
  *
  * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0301f/I1006229.html
  */
-enum arm11_instructions
-{
+enum arm11_instructions {
        ARM11_EXTEST    = 0x00,
        ARM11_SCAN_N    = 0x02,
        ARM11_RESTART   = 0x04,
-       ARM11_HALT          = 0x08,
+       ARM11_HALT          = 0x08,
        ARM11_INTEST    = 0x0C,
        ARM11_ITRSEL    = 0x1D,
        ARM11_IDCODE    = 0x1E,
        ARM11_BYPASS    = 0x1F,
 };
 
-enum arm11_sc7
-{
-       ARM11_SC7_NULL                          = 0,
-       ARM11_SC7_VCR                           = 7,
-       ARM11_SC7_PC                            = 8,
-       ARM11_SC7_BVR0                          = 64,
-       ARM11_SC7_BCR0                          = 80,
-       ARM11_SC7_WVR0                          = 96,
-       ARM11_SC7_WCR0                          = 112,
+enum arm11_sc7 {
+       ARM11_SC7_NULL                          = 0,
+       ARM11_SC7_VCR                           = 7,
+       ARM11_SC7_PC                            = 8,
+       ARM11_SC7_BVR0                          = 64,
+       ARM11_SC7_BCR0                          = 80,
+       ARM11_SC7_WVR0                          = 96,
+       ARM11_SC7_WCR0                          = 112,
 };
 
-#endif /* ARM11_H */
+#endif /* ARM11_H */
index a5dc376..e190e29 100644 (file)
 #include <helper/time_support.h>
 
 #if 0
-#define JTAG_DEBUG(expr ...)   do { if (1) LOG_DEBUG(expr); } while (0)
+#define JTAG_DEBUG(expr ...)    do { if (1) \
+                                            LOG_DEBUG(expr); } while (0)
 #else
-#define JTAG_DEBUG(expr ...)   do { if (0) LOG_DEBUG(expr); } while (0)
+#define JTAG_DEBUG(expr ...)    do { if (0) \
+                                            LOG_DEBUG(expr); } while (0)
 #endif
 
 /*
@@ -42,33 +44,32 @@ behavior of the FTDI driver IIRC was to go via RTI.
 Conversely there may be other places in this code where the ARM11 code relies
 on the driver to hit through RTI when coming from Update-?R.
 */
-static const tap_state_t arm11_move_pi_to_si_via_ci[] =
-{
-    TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
+static const tap_state_t arm11_move_pi_to_si_via_ci[] = {
+       TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
 };
 
-
 /* REVISIT no error handling here! */
 static void arm11_add_ir_scan_vc(struct jtag_tap *tap, struct scan_field *fields,
-               tap_state_t state)
+       tap_state_t state)
 {
        if (cmd_queue_cur_state == TAP_IRPAUSE)
-               jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
+               jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci),
+                       arm11_move_pi_to_si_via_ci);
 
        jtag_add_ir_scan(tap, fields, state);
 }
 
-static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
-{
+static const tap_state_t arm11_move_pd_to_sd_via_cd[] = {
        TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
 };
 
 /* REVISIT no error handling here! */
 void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
-               tap_state_t state)
+       tap_state_t state)
 {
        if (cmd_queue_cur_state == TAP_DRPAUSE)
-               jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
+               jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd),
+                       arm11_move_pd_to_sd_via_cd);
 
        jtag_add_dr_scan(tap, num_fields, fields, state);
 }
@@ -85,11 +86,11 @@ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_fiel
  * \param field                        target data structure that will be initialized
  */
 void arm11_setup_field(struct arm11_common *arm11, int num_bits,
-               void *out_data, void *in_data, struct scan_field *field)
+       void *out_data, void *in_data, struct scan_field *field)
 {
-       field->num_bits                 = num_bits;
-       field->out_value                = out_data;
-       field->in_value                 = in_data;
+       field->num_bits                 = num_bits;
+       field->out_value                = out_data;
+       field->in_value                 = in_data;
 }
 
 static const char *arm11_ir_to_string(uint8_t ir)
@@ -97,30 +98,30 @@ static const char *arm11_ir_to_string(uint8_t ir)
        const char *s = "unknown";
 
        switch (ir) {
-       case ARM11_EXTEST:
-               s = "EXTEST";
-               break;
-       case ARM11_SCAN_N:
-               s = "SCAN_N";
-               break;
-       case ARM11_RESTART:
-               s = "RESTART";
-               break;
-       case ARM11_HALT:
-               s = "HALT";
-               break;
-       case ARM11_INTEST:
-               s = "INTEST";
-               break;
-       case ARM11_ITRSEL:
-               s = "ITRSEL";
-               break;
-       case ARM11_IDCODE:
-               s = "IDCODE";
-               break;
-       case ARM11_BYPASS:
-               s = "BYPASS";
-               break;
+               case ARM11_EXTEST:
+                       s = "EXTEST";
+                       break;
+               case ARM11_SCAN_N:
+                       s = "SCAN_N";
+                       break;
+               case ARM11_RESTART:
+                       s = "RESTART";
+                       break;
+               case ARM11_HALT:
+                       s = "HALT";
+                       break;
+               case ARM11_INTEST:
+                       s = "INTEST";
+                       break;
+               case ARM11_ITRSEL:
+                       s = "ITRSEL";
+                       break;
+               case ARM11_IDCODE:
+                       s = "IDCODE";
+                       break;
+               case ARM11_BYPASS:
+                       s = "BYPASS";
+                       break;
        }
        return s;
 }
@@ -133,12 +134,11 @@ static const char *arm11_ir_to_string(uint8_t ir)
  *
  * \remarks                    This adds to the JTAG command queue but does \em not execute it.
  */
-void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
+void arm11_add_IR(struct arm11_common *arm11, uint8_t instr, tap_state_t state)
 {
        struct jtag_tap *tap = arm11->arm.target->tap;
 
-       if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
-       {
+       if (buf_get_u32(tap->cur_instr, 0, 5) == instr) {
                JTAG_DEBUG("IR <= 0x%02x SKIPPED", instr);
                return;
        }
@@ -149,7 +149,9 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
 
        arm11_setup_field(arm11, 5, &instr, NULL, &field);
 
-       arm11_add_ir_scan_vc(arm11->arm.target->tap, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
+       arm11_add_ir_scan_vc(arm11->arm.target->tap,
+               &field,
+               state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
 }
 
 /** Verify data shifted out from Scan Chain Register (SCREG). */
@@ -158,8 +160,7 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
        /* Don't expect JTAG layer to modify bits we didn't ask it to read */
        uint8_t v = *in_value & 0x1F;
 
-       if (v != 0x10)
-       {
+       if (v != 0x10) {
                LOG_ERROR("'arm11 target' JTAG error SCREG OUT 0x%02x", v);
                jtag_set_error(ERROR_FAIL);
        }
@@ -193,33 +194,36 @@ static void arm11_in_handler_SCAN_N(uint8_t *in_value)
  */
 
 int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
-               uint8_t chain, tap_state_t state)
+       uint8_t chain, tap_state_t state)
 {
        /* Don't needlessly switch the scan chain.
         * NOTE:  the ITRSEL instruction fakes SCREG changing;
         * but leaves its actual value unchanged.
         */
 #if 0
-       // FIX!!! the optimization below is broken because we do not
-       // invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c
-       // for example on how to invalidate cur_scan_chain. Tested patches gladly
-       // accepted!
+       /* FIX!!! the optimization below is broken because we do not */
+       /* invalidate the cur_scan_chain upon a TRST/TMS. See arm_jtag.c */
+       /* for example on how to invalidate cur_scan_chain. Tested patches gladly */
+       /* accepted! */
        if (arm11->jtag_info.cur_scan_chain == chain) {
                JTAG_DEBUG("SCREG <= %d SKIPPED", chain);
                return jtag_add_statemove((state == ARM11_TAP_DEFAULT)
-                                       ? TAP_DRPAUSE : state);
+                       ? TAP_DRPAUSE : state);
        }
 #endif
        JTAG_DEBUG("SCREG <= %d", chain);
 
        arm11_add_IR(arm11, ARM11_SCAN_N, ARM11_TAP_DEFAULT);
 
-       struct scan_field               field;
+       struct scan_field field;
 
        uint8_t tmp[1];
        arm11_setup_field(arm11, 5, &chain, &tmp, &field);
 
-       arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
+       arm11_add_dr_scan_vc(arm11->arm.target->tap,
+               1,
+               &field,
+               state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
 
        jtag_execute_queue_noclear();
 
@@ -248,15 +252,15 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
  * is properly set up.  Depending on the instruction, you may also need
  * to ensure that the rDTR is ready before that Run-Test/Idle state.
  */
-static void arm11_add_debug_INST(struct arm11_common * arm11,
-               uint32_t inst, uint8_t * flag, tap_state_t state)
+static void arm11_add_debug_INST(struct arm11_common *arm11,
+       uint32_t inst, uint8_t *flag, tap_state_t state)
 {
        JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
 
-       struct scan_field               itr[2];
+       struct scan_field itr[2];
 
-       arm11_setup_field(arm11, 32,    &inst,  NULL, itr + 0);
-       arm11_setup_field(arm11, 1,         NULL,       flag, itr + 1);
+       arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
+       arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
 
        arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(itr), itr, state);
 }
@@ -281,8 +285,8 @@ int arm11_read_DSCR(struct arm11_common *arm11)
 
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-       uint32_t                                dscr;
-       struct scan_field       chain1_field;
+       uint32_t dscr;
+       struct scan_field chain1_field;
 
        arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
 
@@ -292,8 +296,8 @@ int arm11_read_DSCR(struct arm11_common *arm11)
 
        if (arm11->dscr != dscr)
                JTAG_DEBUG("DSCR  = %08x (OLD %08x)",
-                               (unsigned) dscr,
-                               (unsigned) arm11->dscr);
+                       (unsigned) dscr,
+                       (unsigned) arm11->dscr);
 
        arm11->dscr = dscr;
 
@@ -309,7 +313,7 @@ int arm11_read_DSCR(struct arm11_common *arm11)
  *
  * \remarks                    This is a stand-alone function that executes the JTAG command queue.
  */
-int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
+int arm11_write_DSCR(struct arm11_common *arm11, uint32_t dscr)
 {
        int retval;
        retval = arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -318,7 +322,7 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
 
        arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field                   chain1_field;
+       struct scan_field chain1_field;
 
        arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
 
@@ -327,8 +331,8 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
        CHECK_RETVAL(jtag_execute_queue());
 
        JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
-                       (unsigned) dscr,
-                       (unsigned) arm11->dscr);
+               (unsigned) dscr,
+               (unsigned) arm11->dscr);
 
        arm11->dscr = dscr;
 
@@ -349,7 +353,7 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
  * \param arm11                Target state variable.
  *
  */
-int arm11_run_instr_data_prepare(struct arm11_common * arm11)
+int arm11_run_instr_data_prepare(struct arm11_common *arm11)
 {
        return arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
 }
@@ -368,13 +372,11 @@ int arm11_run_instr_data_prepare(struct arm11_common * arm11)
  * \param arm11                Target state variable.
  *
  */
-int arm11_run_instr_data_finish(struct arm11_common * arm11)
+int arm11_run_instr_data_finish(struct arm11_common *arm11)
 {
        return arm11_add_debug_SCAN_N(arm11, 0x00, ARM11_TAP_DEFAULT);
 }
 
-
-
 /**
  * Execute one or more instructions via ITR.
  * Caller guarantees that processor is in debug state, that DSCR_ITR_EN
@@ -389,18 +391,16 @@ int arm11_run_instr_data_finish(struct arm11_common * arm11)
  *
  */
 static
-int arm11_run_instr_no_data(struct arm11_common * arm11,
-               uint32_t * opcode, size_t count)
+int arm11_run_instr_no_data(struct arm11_common *arm11,
+       uint32_t *opcode, size_t count)
 {
        arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
 
-       while (count--)
-       {
+       while (count--) {
                arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
 
                int i = 0;
-               while (1)
-               {
+               while (1) {
                        uint8_t flag;
 
                        arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
@@ -413,14 +413,11 @@ int arm11_run_instr_no_data(struct arm11_common * arm11,
                        long long then = 0;
 
                        if (i == 1000)
-                       {
                                then = timeval_ms();
-                       }
-                       if (i >= 1000)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
-                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                       if (i >= 1000) {
+                               if ((timeval_ms()-then) > 1000) {
+                                       LOG_WARNING(
+                                               "Timeout (1000ms) waiting for instructions to complete");
                                        return ERROR_FAIL;
                                }
                        }
@@ -440,7 +437,7 @@ int arm11_run_instr_no_data(struct arm11_common * arm11,
  * \param opcode       ARM opcode
  *
  */
-int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode)
+int arm11_run_instr_no_data1(struct arm11_common *arm11, uint32_t opcode)
 {
        return arm11_run_instr_no_data(arm11, &opcode, 1);
 }
@@ -463,7 +460,10 @@ int arm11_run_instr_no_data1(struct arm11_common * arm11, uint32_t opcode)
  * \param count                Number of data words and instruction repetitions
  *
  */
-int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core(struct arm11_common *arm11,
+       uint32_t opcode,
+       uint32_t *data,
+       size_t count)
 {
        arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
 
@@ -471,24 +471,23 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
 
        arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field       chain5_fields[3];
+       struct scan_field chain5_fields[3];
 
-       uint32_t                                Data;
-       uint8_t                         Ready;
-       uint8_t                         nRetry;
+       uint32_t Data;
+       uint8_t Ready;
+       uint8_t nRetry;
 
-       arm11_setup_field(arm11, 32,    &Data,  NULL,           chain5_fields + 0);
-       arm11_setup_field(arm11,  1,    NULL,   &Ready,         chain5_fields + 1);
-       arm11_setup_field(arm11,  1,    NULL,   &nRetry,        chain5_fields + 2);
+       arm11_setup_field(arm11, 32,    &Data,  NULL,           chain5_fields + 0);
+       arm11_setup_field(arm11,  1,    NULL,   &Ready,         chain5_fields + 1);
+       arm11_setup_field(arm11,  1,    NULL,   &nRetry,        chain5_fields + 2);
 
-       while (count--)
-       {
+       while (count--) {
                int i = 0;
-               do
-               {
-                       Data        = *data;
+               do {
+                       Data        = *data;
 
-                       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
+                       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                                       chain5_fields), chain5_fields, TAP_IDLE);
 
                        CHECK_RETVAL(jtag_execute_queue());
 
@@ -497,21 +496,17 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
                        long long then = 0;
 
                        if (i == 1000)
-                       {
                                then = timeval_ms();
-                       }
-                       if (i >= 1000)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
-                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                       if (i >= 1000) {
+                               if ((timeval_ms()-then) > 1000) {
+                                       LOG_WARNING(
+                                               "Timeout (1000ms) waiting for instructions to complete");
                                        return ERROR_FAIL;
                                }
                        }
 
                        i++;
-               }
-               while (!Ready);
+               } while (!Ready);
 
                data++;
        }
@@ -519,35 +514,30 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
        int i = 0;
-       do
-       {
-               Data        = 0;
+       do {
+               Data        = 0;
 
-               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+               arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                               chain5_fields), chain5_fields, TAP_DRPAUSE);
 
                CHECK_RETVAL(jtag_execute_queue());
 
                JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d",
-                               (unsigned) Data, Ready, nRetry);
+                       (unsigned) Data, Ready, nRetry);
 
                long long then = 0;
 
                if (i == 1000)
-               {
                        then = timeval_ms();
-               }
-               if (i >= 1000)
-               {
-                       if ((timeval_ms()-then) > 1000)
-                       {
+               if (i >= 1000) {
+                       if ((timeval_ms()-then) > 1000) {
                                LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
                                return ERROR_FAIL;
                        }
                }
 
                i++;
-       }
-       while (!Ready);
+       } while (!Ready);
 
        return ERROR_OK;
 }
@@ -569,74 +559,68 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
  *  https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
  *  https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
  */
-static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
-{
-       TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
+static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = {
+       TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE,
+       TAP_DRSHIFT
 };
 
 /* This inner loop can be implemented by the minidriver, oftentimes in hardware... The
  * minidriver can call the default implementation as a fallback or implement it
  * from scratch.
  */
-int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *tap,
+       uint32_t opcode,
+       uint32_t *data,
+       size_t count)
 {
-       struct scan_field       chain5_fields[3];
+       struct scan_field chain5_fields[3];
 
-       chain5_fields[0].num_bits               = 32;
-       chain5_fields[0].out_value              = NULL; /*&Data*/
-       chain5_fields[0].in_value               = NULL;
+       chain5_fields[0].num_bits               = 32;
+       chain5_fields[0].out_value              = NULL; /*&Data*/
+       chain5_fields[0].in_value               = NULL;
 
-       chain5_fields[1].num_bits               = 1;
-       chain5_fields[1].out_value              = NULL;
-       chain5_fields[1].in_value               = NULL; /*&Ready*/
+       chain5_fields[1].num_bits               = 1;
+       chain5_fields[1].out_value              = NULL;
+       chain5_fields[1].in_value               = NULL; /*&Ready*/
 
-       chain5_fields[2].num_bits               = 1;
-       chain5_fields[2].out_value              = NULL;
-       chain5_fields[2].in_value               = NULL;
+       chain5_fields[2].num_bits               = 1;
+       chain5_fields[2].out_value              = NULL;
+       chain5_fields[2].in_value               = NULL;
 
-       uint8_t                 *Readies;
+       uint8_t *Readies;
        unsigned readiesNum = count;
        unsigned bytes = sizeof(*Readies)*readiesNum;
 
        Readies = (uint8_t *) malloc(bytes);
-       if (Readies == NULL)
-       {
+       if (Readies == NULL) {
                LOG_ERROR("Out of memory allocating %u bytes", bytes);
                return ERROR_FAIL;
        }
 
-       uint8_t *               ReadyPos                        = Readies;
-       while (count--)
-       {
-               chain5_fields[0].out_value      = (void *)(data++);
-               chain5_fields[1].in_value       = ReadyPos++;
+       uint8_t *ReadyPos                        = Readies;
+       while (count--) {
+               chain5_fields[0].out_value      = (void *)(data++);
+               chain5_fields[1].in_value       = ReadyPos++;
 
-               if (count > 0)
-               {
-                       jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+               if (count > 0) {
+                       jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields,
+                               TAP_DRPAUSE);
                        jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
                                arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
                } else
-               {
                        jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
-               }
        }
 
        int retval = jtag_execute_queue();
-       if (retval == ERROR_OK)
-       {
+       if (retval == ERROR_OK) {
                unsigned error_count = 0;
 
-               for (size_t i = 0; i < readiesNum; i++)
-               {
+               for (size_t i = 0; i < readiesNum; i++) {
                        if (Readies[i] != 1)
-                       {
                                error_count++;
-                       }
                }
 
-               if (error_count > 0 )
-               {
+               if (error_count > 0) {
                        LOG_ERROR("%u words out of %u not transferred",
                                error_count, readiesNum);
                        retval = ERROR_FAIL;
@@ -647,10 +631,16 @@ int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint
        return retval;
 }
 
-int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count);
+int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
+                                            uint32_t opcode,
+                                            uint32_t *data,
+                                            size_t count);
 
 #ifndef HAVE_JTAG_MINIDRIVER_H
-int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
+       uint32_t opcode,
+       uint32_t *data,
+       size_t count)
 {
        return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
 }
@@ -675,7 +665,10 @@ int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap * tap, uint32_t opc
  * \param count                Number of data words and instruction repetitions
  *
  */
-int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_to_core_noack(struct arm11_common *arm11,
+       uint32_t opcode,
+       uint32_t *data,
+       size_t count)
 {
        arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
 
@@ -683,29 +676,43 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opc
 
        arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-       int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap, opcode, data, count);
+       int retval = arm11_run_instr_data_to_core_noack_inner(arm11->arm.target->tap,
+                       opcode,
+                       data,
+                       count);
 
        if (retval != ERROR_OK)
                return retval;
 
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field       chain5_fields[3];
-
-       arm11_setup_field(arm11, 32,    NULL/*&Data*/,  NULL,                           chain5_fields + 0);
-       arm11_setup_field(arm11,  1,    NULL,                   NULL /*&Ready*/,        chain5_fields + 1);
-       arm11_setup_field(arm11,  1,    NULL,                   NULL,                           chain5_fields + 2);
+       struct scan_field chain5_fields[3];
+
+       arm11_setup_field(arm11,
+               32,
+               NULL /*&Data*/,
+               NULL,
+               chain5_fields + 0);
+       arm11_setup_field(arm11,
+               1,
+               NULL,
+               NULL /*&Ready*/,
+               chain5_fields + 1);
+       arm11_setup_field(arm11,
+               1,
+               NULL,
+               NULL,
+               chain5_fields + 2);
 
        uint8_t ready_flag;
        chain5_fields[1].in_value   = &ready_flag;
 
-       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
+       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                       chain5_fields), chain5_fields, TAP_DRPAUSE);
 
        retval = jtag_execute_queue();
-       if (retval == ERROR_OK)
-       {
-               if (ready_flag != 1)
-               {
+       if (retval == ERROR_OK) {
+               if (ready_flag != 1) {
                        LOG_ERROR("last word not transferred");
                        retval = ERROR_FAIL;
                }
@@ -726,7 +733,7 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opc
  * \param data         Data word to be passed to the core via DTR
  *
  */
-int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
+int arm11_run_instr_data_to_core1(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
 {
        return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
 }
@@ -749,7 +756,10 @@ int arm11_run_instr_data_to_core1(struct arm11_common * arm11, uint32_t opcode,
  * \param count                Number of data words and instruction repetitions
  *
  */
-int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode, uint32_t * data, size_t count)
+int arm11_run_instr_data_from_core(struct arm11_common *arm11,
+       uint32_t opcode,
+       uint32_t *data,
+       size_t count)
 {
        arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
 
@@ -757,46 +767,42 @@ int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode,
 
        arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field       chain5_fields[3];
+       struct scan_field chain5_fields[3];
 
-       uint32_t                        Data;
-       uint8_t                 Ready;
-       uint8_t                 nRetry;
+       uint32_t Data;
+       uint8_t Ready;
+       uint8_t nRetry;
 
-       arm11_setup_field(arm11, 32,    NULL,   &Data,      chain5_fields + 0);
-       arm11_setup_field(arm11,  1,    NULL,   &Ready,     chain5_fields + 1);
-       arm11_setup_field(arm11,  1,    NULL,   &nRetry,    chain5_fields + 2);
+       arm11_setup_field(arm11, 32,    NULL,   &Data,      chain5_fields + 0);
+       arm11_setup_field(arm11,  1,    NULL,   &Ready,     chain5_fields + 1);
+       arm11_setup_field(arm11,  1,    NULL,   &nRetry,    chain5_fields + 2);
 
-       while (count--)
-       {
+       while (count--) {
                int i = 0;
-               do
-               {
-                       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
+               do {
+                       arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(
+                                       chain5_fields), chain5_fields,
+                               count ? TAP_IDLE : TAP_DRPAUSE);
 
                        CHECK_RETVAL(jtag_execute_queue());
 
                        JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d",
-                                       (unsigned) Data, Ready, nRetry);
+                               (unsigned) Data, Ready, nRetry);
 
                        long long then = 0;
 
                        if (i == 1000)
-                       {
                                then = timeval_ms();
-                       }
-                       if (i >= 1000)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
-                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                       if (i >= 1000) {
+                               if ((timeval_ms()-then) > 1000) {
+                                       LOG_WARNING(
+                                               "Timeout (1000ms) waiting for instructions to complete");
                                        return ERROR_FAIL;
                                }
                        }
 
                        i++;
-               }
-               while (!Ready);
+               } while (!Ready);
 
                *data++ = Data;
        }
@@ -816,7 +822,9 @@ int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode,
  * \param data         Pointer to a data word that receives the value from r0 after \p opcode was executed.
  *
  */
-int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t * data)
+int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11,
+       uint32_t opcode,
+       uint32_t *data)
 {
        int retval;
        retval = arm11_run_instr_no_data1(arm11, opcode);
@@ -841,7 +849,7 @@ int arm11_run_instr_data_from_core_via_r0(struct arm11_common * arm11, uint32_t
  * \param data         Data word that will be written to r0 before \p opcode is executed
  *
  */
-int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t opcode, uint32_t data)
+int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11, uint32_t opcode, uint32_t data)
 {
        int retval;
        /* MRC p14,0,r0,c0,c5,0 */
@@ -865,7 +873,7 @@ int arm11_run_instr_data_to_core_via_r0(struct arm11_common * arm11, uint32_t op
  * \param count                Number of instructions in the list.
  *
  */
-int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions, size_t count)
+int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions, size_t count)
 {
        int retval;
 
@@ -875,45 +883,40 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
 
        arm11_add_IR(arm11, ARM11_EXTEST, ARM11_TAP_DEFAULT);
 
-       struct scan_field       chain7_fields[3];
-
-       uint8_t                         nRW;
-       uint32_t                                DataOut;
-       uint8_t                         AddressOut;
-       uint8_t                         Ready;
-       uint32_t                                DataIn;
-       uint8_t                         AddressIn;
-
-       arm11_setup_field(arm11,  1, &nRW,                      &Ready,         chain7_fields + 0);
-       arm11_setup_field(arm11, 32, &DataOut,          &DataIn,        chain7_fields + 1);
-       arm11_setup_field(arm11,  7, &AddressOut,       &AddressIn,     chain7_fields + 2);
-
-       for (size_t i = 0; i < count + 1; i++)
-       {
-               if (i < count)
-               {
-                       nRW                     = actions[i].write ? 1 : 0;
-                       DataOut         = actions[i].value;
-                       AddressOut      = actions[i].address;
-               }
-               else
-               {
-                       nRW                     = 1;
-                       DataOut         = 0;
-                       AddressOut      = 0;
+       struct scan_field chain7_fields[3];
+
+       uint8_t nRW;
+       uint32_t DataOut;
+       uint8_t AddressOut;
+       uint8_t Ready;
+       uint32_t DataIn;
+       uint8_t AddressIn;
+
+       arm11_setup_field(arm11,  1, &nRW,                      &Ready,         chain7_fields + 0);
+       arm11_setup_field(arm11, 32, &DataOut,          &DataIn,        chain7_fields + 1);
+       arm11_setup_field(arm11,  7, &AddressOut,       &AddressIn,     chain7_fields + 2);
+
+       for (size_t i = 0; i < count + 1; i++) {
+               if (i < count) {
+                       nRW                     = actions[i].write ? 1 : 0;
+                       DataOut         = actions[i].value;
+                       AddressOut      = actions[i].address;
+               } else {
+                       nRW                     = 1;
+                       DataOut         = 0;
+                       AddressOut      = 0;
                }
 
                /* Timeout here so we don't get stuck. */
                int i_n = 0;
-               while (1)
-               {
+               while (1) {
                        JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
-                                       (unsigned) AddressOut,
-                                       (unsigned) DataOut,
-                                       nRW ? "write" : "read");
+                               (unsigned) AddressOut,
+                               (unsigned) DataOut,
+                               nRW ? "write" : "read");
 
                        arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
-                                       chain7_fields, TAP_DRPAUSE);
+                               chain7_fields, TAP_DRPAUSE);
 
                        CHECK_RETVAL(jtag_execute_queue());
 
@@ -924,14 +927,11 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
                        long long then = 0;
 
                        if (i_n == 1000)
-                       {
                                then = timeval_ms();
-                       }
-                       if (i_n >= 1000)
-                       {
-                               if ((timeval_ms()-then) > 1000)
-                               {
-                                       LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+                       if (i_n >= 1000) {
+                               if ((timeval_ms()-then) > 1000) {
+                                       LOG_WARNING(
+                                               "Timeout (1000ms) waiting for instructions to complete");
                                        return ERROR_FAIL;
                                }
                        }
@@ -942,23 +942,15 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
                if (!nRW)
                        JTAG_DEBUG("SC7 => Data %08x", (unsigned) DataIn);
 
-               if (i > 0)
-               {
+               if (i > 0) {
                        if (actions[i - 1].address != AddressIn)
-                       {
                                LOG_WARNING("Scan chain 7 shifted out unexpected address");
-                       }
 
                        if (!actions[i - 1].write)
-                       {
                                actions[i - 1].value = DataIn;
-                       }
-                       else
-                       {
+                       else {
                                if (actions[i - 1].value != DataIn)
-                               {
                                        LOG_WARNING("Scan chain 7 shifted out unexpected data");
-                               }
                        }
                }
        }
@@ -970,16 +962,15 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
  * \param arm11                Target state variable.
  *
  */
-int arm11_sc7_clear_vbw(struct arm11_common * arm11)
+int arm11_sc7_clear_vbw(struct arm11_common *arm11)
 {
        size_t clear_bw_size = arm11->brp + 1;
-       struct arm11_sc7_action         *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
-       struct arm11_sc7_action *       pos = clear_bw;
+       struct arm11_sc7_action *clear_bw = malloc(sizeof(struct arm11_sc7_action) * clear_bw_size);
+       struct arm11_sc7_action *pos = clear_bw;
 
-       for (size_t i = 0; i < clear_bw_size; i++)
-       {
-               clear_bw[i].write       = true;
-               clear_bw[i].value       = 0;
+       for (size_t i = 0; i < clear_bw_size; i++) {
+               clear_bw[i].write       = true;
+               clear_bw[i].value       = 0;
        }
 
        for (size_t i = 0; i < arm11->brp; i++)
@@ -990,7 +981,7 @@ int arm11_sc7_clear_vbw(struct arm11_common * arm11)
        int retval;
        retval = arm11_sc7_run(arm11, clear_bw, clear_bw_size);
 
-       free (clear_bw);
+       free(clear_bw);
 
        return retval;
 }
@@ -1000,19 +991,17 @@ int arm11_sc7_clear_vbw(struct arm11_common * arm11)
  * \param arm11                Target state variable.
  * \param value                Value to be written
  */
-int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
+int arm11_sc7_set_vcr(struct arm11_common *arm11, uint32_t value)
 {
-       struct arm11_sc7_action         set_vcr;
+       struct arm11_sc7_action set_vcr;
 
-       set_vcr.write           = true;
-       set_vcr.address         = ARM11_SC7_VCR;
-       set_vcr.value           = value;
+       set_vcr.write           = true;
+       set_vcr.address         = ARM11_SC7_VCR;
+       set_vcr.value           = value;
 
        return arm11_sc7_run(arm11, &set_vcr, 1);
 }
 
-
-
 /** Read word from address
  *
  * \param arm11                Target state variable.
@@ -1020,7 +1009,7 @@ int arm11_sc7_set_vcr(struct arm11_common * arm11, uint32_t value)
  * \param result       Pointer where to store result
  *
  */
-int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32_t * result)
+int arm11_read_memory_word(struct arm11_common *arm11, uint32_t address, uint32_t *result)
 {
        int retval;
        retval = arm11_run_instr_data_prepare(arm11);
@@ -1036,7 +1025,6 @@ int arm11_read_memory_word(struct arm11_common * arm11, uint32_t address, uint32
        return arm11_run_instr_data_finish(arm11);
 }
 
-
 /************************************************************************/
 
 /*
@@ -1060,31 +1048,31 @@ static int arm11_dpm_finish(struct arm_dpm *dpm)
 }
 
 static int arm11_dpm_instr_write_data_dcc(struct arm_dpm *dpm,
-               uint32_t opcode, uint32_t data)
+       uint32_t opcode, uint32_t data)
 {
        return arm11_run_instr_data_to_core(dpm_to_arm11(dpm),
-                       opcode, &data, 1);
+               opcode, &data, 1);
 }
 
 static int arm11_dpm_instr_write_data_r0(struct arm_dpm *dpm,
-               uint32_t opcode, uint32_t data)
+       uint32_t opcode, uint32_t data)
 {
        return arm11_run_instr_data_to_core_via_r0(dpm_to_arm11(dpm),
-                       opcode, data);
+               opcode, data);
 }
 
 static int arm11_dpm_instr_read_data_dcc(struct arm_dpm *dpm,
-               uint32_t opcode, uint32_t *data)
+       uint32_t opcode, uint32_t *data)
 {
        return arm11_run_instr_data_from_core(dpm_to_arm11(dpm),
-                       opcode, data, 1);
+               opcode, data, 1);
 }
 
 static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
-               uint32_t opcode, uint32_t *data)
+       uint32_t opcode, uint32_t *data)
 {
        return arm11_run_instr_data_from_core_via_r0(dpm_to_arm11(dpm),
-                       opcode, data);
+               opcode, data);
 }
 
 /* Because arm11_sc7_run() takes a vector of actions, we batch breakpoint
@@ -1092,7 +1080,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
  * pre-allocated our vector, we don't need to worry about space.
  */
 static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
-               uint32_t addr, uint32_t control)
+       uint32_t addr, uint32_t control)
 {
        struct arm11_common *arm11 = dpm_to_arm11(dpm);
        struct arm11_sc7_action *action;
@@ -1110,17 +1098,17 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
        action[1].value = control;
 
        switch (index_t) {
-       case 0 ... 15:
-               action[0].address = ARM11_SC7_BVR0 + index_t;
-               action[1].address = ARM11_SC7_BCR0 + index_t;
-               break;
-       case 16 ... 32:
-               index_t -= 16;
-               action[0].address = ARM11_SC7_WVR0 + index_t;
-               action[1].address = ARM11_SC7_WCR0 + index_t;
-               break;
-       default:
-               return ERROR_FAIL;
+           case 0 ... 15:
+                   action[0].address = ARM11_SC7_BVR0 + index_t;
+                   action[1].address = ARM11_SC7_BCR0 + index_t;
+                   break;
+           case 16 ... 32:
+                   index_t -= 16;
+                   action[0].address = ARM11_SC7_WVR0 + index_t;
+                   action[1].address = ARM11_SC7_WCR0 + index_t;
+                   break;
+           default:
+                   return ERROR_FAIL;
        }
 
        arm11->bpwp_n += 2;
@@ -1139,15 +1127,15 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
        action[0].value = 0;
 
        switch (index_t) {
-       case 0 ... 15:
-               action[0].address = ARM11_SC7_BCR0 + index_t;
-               break;
-       case 16 ... 32:
-               index_t -= 16;
-               action[0].address = ARM11_SC7_WCR0 + index_t;
-               break;
-       default:
-               return ERROR_FAIL;
+           case 0 ... 15:
+                   action[0].address = ARM11_SC7_BCR0 + index_t;
+                   break;
+           case 16 ... 32:
+                   index_t -= 16;
+                   action[0].address = ARM11_SC7_WCR0 + index_t;
+                   break;
+           default:
+                   return ERROR_FAIL;
        }
 
        arm11->bpwp_n += 1;
index e45bdc2..22d9dec 100644 (file)
@@ -1,3 +1,25 @@
+/***************************************************************************
+ *   Copyright (C) 2008 digenius technology GmbH.                          *
+ *   Michael Bruck                                                         *
+ *                                                                         *
+ *   Copyright (C) 2008,2009 Oyvind Harboe oyvind.harboe@zylin.com         *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
 #ifndef ARM11_DBGTAP_H
 #define ARM11_DBGTAP_H
 
@@ -37,10 +59,9 @@ void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_fiel
  * Used with arm11_sc7_run to make a list of read/write commands for
  * scan chain 7
  */
-struct arm11_sc7_action
-{
-       bool write; /**< Access mode: true for write, false for read. */
-       uint8_t address; /**< Register address mode. Use enum #arm11_sc7 */
+struct arm11_sc7_action {
+       bool write;     /**< Access mode: true for write, false for read. */
+       uint8_t address;/**< Register address mode. Use enum #arm11_sc7 */
        /**
         * If write then set this to value to be written.  In read mode
         * this receives the read value when the function returns.
@@ -61,4 +82,4 @@ int arm11_read_memory_word(struct arm11_common *arm11,
 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr);
 int arm11_bpwp_flush(struct arm11_common *arm11);
 
-#endif // ARM11_DBGTAP_H
+#endif /* ARM11_DBGTAP_H */
index 94af0f7..a061a11 100644 (file)
@@ -20,6 +20,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -54,14 +55,12 @@ static int arm720t_scan_cp15(struct target *target,
 
        buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
-       if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
-       {
+       retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
+       if (retval != ERROR_OK)
                return retval;
-       }
-       if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
-       {
+       retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        fields[0].num_bits = 1;
        fields[0].out_value = &instruction_buf;
@@ -71,24 +70,20 @@ static int arm720t_scan_cp15(struct target *target,
        fields[1].out_value = out_buf;
        fields[1].in_value = NULL;
 
-       if (in)
-       {
+       if (in) {
                fields[1].in_value = (uint8_t *)in;
                jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
                jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
        } else
-       {
                jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
-       }
 
        if (clock_arg)
                jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        if (in)
                LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
@@ -254,8 +249,7 @@ static int arm720t_arch_state(struct target *target)
 {
        struct arm720t_common *arm720t = target_to_arm720(target);
 
-       static const char *state[] =
-       {
+       static const char *state[] = {
                "disabled", "enabled"
        };
 
@@ -300,16 +294,14 @@ static int arm720t_read_memory(struct target *target,
        struct arm720t_common *arm720t = target_to_arm720(target);
 
        /* disable cache, but leave MMU enabled */
-       if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-       {
+       if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
                retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
                if (retval != ERROR_OK)
                        return retval;
        }
        retval = arm7_9_read_memory(target, address, size, count, buffer);
 
-       if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-       {
+       if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
                retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
                if (retval != ERROR_OK)
                        return retval;
@@ -342,36 +334,26 @@ static int arm720t_soft_reset_halt(struct target *target)
                        .eice_cache->reg_list[EICE_DBG_STAT];
        struct arm *arm = &arm720t->arm7_9_common.arm;
 
-       if ((retval = target_halt(target)) != ERROR_OK)
-       {
+       retval = target_halt(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        long long then = timeval_ms();
        int timeout;
-       while (!(timeout = ((timeval_ms()-then) > 1000)))
-       {
-               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
-               {
+       while (!(timeout = ((timeval_ms()-then) > 1000))) {
+               if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
                        embeddedice_read_reg(dbg_stat);
-                       if ((retval = jtag_execute_queue()) != ERROR_OK)
-                       {
+                       retval = jtag_execute_queue();
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                } else
-               {
                        break;
-               }
                if (debug_level >= 3)
-               {
                        alive_sleep(100);
-               } else
-               {
+               else
                        keep_alive();
-               }
        }
-       if (timeout)
-       {
+       if (timeout) {
                LOG_ERROR("Failed to halt CPU after 1 sec");
                return ERROR_TARGET_TIMEOUT;
        }
@@ -399,10 +381,9 @@ static int arm720t_soft_reset_halt(struct target *target)
        arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
        arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
-       if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-       {
+       retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        return ERROR_OK;
 }
@@ -467,42 +448,35 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
        if (retval != ERROR_OK)
                return retval;
 
-
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
                return ERROR_OK;
        }
 
        /* one or more argument, access a single register (write if second argument is given */
-       if (CMD_ARGC >= 1)
-       {
+       if (CMD_ARGC >= 1) {
                uint32_t opcode;
                COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
 
-               if (CMD_ARGC == 1)
-               {
+               if (CMD_ARGC == 1) {
                        uint32_t value;
-                       if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
-                       {
+                       retval = arm720t_read_cp15(target, opcode, &value);
+                       if (retval != ERROR_OK) {
                                command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
 
-                       if ((retval = jtag_execute_queue()) != ERROR_OK)
-                       {
+                       retval = jtag_execute_queue();
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
 
                        command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
-               }
-               else if (CMD_ARGC == 2)
-               {
+               } else if (CMD_ARGC == 2) {
                        uint32_t value;
                        COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 
-                       if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
-                       {
+                       retval = arm720t_write_cp15(target, opcode, value);
+                       if (retval != ERROR_OK) {
                                command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
                                return ERROR_OK;
                        }
@@ -518,8 +492,7 @@ static int arm720t_mrc(struct target *target, int cpnum,
                uint32_t CRn, uint32_t CRm,
                uint32_t *value)
 {
-       if (cpnum!=15)
-       {
+       if (cpnum != 15) {
                LOG_ERROR("Only cp15 is supported");
                return ERROR_FAIL;
        }
@@ -536,8 +509,7 @@ static int arm720t_mcr(struct target *target, int cpnum,
                uint32_t CRn, uint32_t CRm,
                uint32_t value)
 {
-       if (cpnum!=15)
-       {
+       if (cpnum != 15) {
                LOG_ERROR("Only cp15 is supported");
                return ERROR_FAIL;
        }
@@ -576,8 +548,7 @@ static const struct command_registration arm720t_command_handlers[] = {
 };
 
 /** Holds methods for ARM720 targets. */
-struct target_type arm720t_target =
-{
+struct target_type arm720t_target = {
        .name = "arm720t",
 
        .poll = arm7_9_poll,
index e96f270..a3a6883 100644 (file)
@@ -17,6 +17,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef ARM720T_H
 #define ARM720T_H
 
@@ -25,8 +26,7 @@
 
 #define        ARM720T_COMMON_MAGIC 0xa720a720
 
-struct arm720t_common
-{
+struct arm720t_common {
        struct arm7_9_common arm7_9_common;
        uint32_t common_magic;
        struct armv4_5_mmu_common armv4_5_mmu;
@@ -35,11 +35,9 @@ struct arm720t_common
        uint32_t far_reg;
 };
 
-static inline struct arm720t_common *
-target_to_arm720(struct target *target)
+static inline struct arm720t_common *target_to_arm720(struct target *target)
 {
-       return container_of(target->arch_info, struct arm720t_common,
-                       arm7_9_common.arm);
+       return container_of(target->arch_info, struct arm720t_common, arm7_9_common.arm);
 }
 
 #endif /* ARM720T_H */
index a77004e..bf08194 100644 (file)
@@ -28,6 +28,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -43,7 +44,6 @@
 #include "register.h"
 #include "armv4_5.h"
 
-
 /**
  * @file
  * Hold common code supporting the ARM7 and ARM9 core generations.
@@ -93,26 +93,20 @@ static int arm7_9_clear_watchpoints(struct arm7_9_common *arm7_9)
  */
 static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *breakpoint)
 {
-       if (!arm7_9->wp0_used)
-       {
+       if (!arm7_9->wp0_used) {
                arm7_9->wp0_used = 1;
                breakpoint->set = 1;
                arm7_9->wp_available--;
-       }
-       else if (!arm7_9->wp1_used)
-       {
+       } else if (!arm7_9->wp1_used) {
                arm7_9->wp1_used = 1;
                breakpoint->set = 2;
                arm7_9->wp_available--;
-       }
-       else
-       {
+       } else
                LOG_ERROR("BUG: no hardware comparator available");
-       }
        LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
-                         breakpoint->unique_id,
-                         breakpoint->address,
-                         breakpoint->set );
+                       breakpoint->unique_id,
+                       breakpoint->address,
+                       breakpoint->set);
 }
 
 /**
@@ -120,60 +114,48 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br
  *
  * @param arm7_9 Pointer to common struct for ARM7/9 targets
  * @return Error codes if there is a problem finding a watchpoint or the result
- *         of executing the JTAG queue
+ * of executing the JTAG queue
  */
 static int arm7_9_set_software_breakpoints(struct arm7_9_common *arm7_9)
 {
        if (arm7_9->sw_breakpoints_added)
-       {
                return ERROR_OK;
-       }
-       if (arm7_9->wp_available < 1)
-       {
+       if (arm7_9->wp_available < 1) {
                LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
        arm7_9->wp_available--;
 
        /* pick a breakpoint unit */
-       if (!arm7_9->wp0_used)
-       {
+       if (!arm7_9->wp0_used) {
                arm7_9->sw_breakpoints_added = 1;
                arm7_9->wp0_used = 3;
-       } else if (!arm7_9->wp1_used)
-       {
+       } else if (!arm7_9->wp1_used) {
                arm7_9->sw_breakpoints_added = 2;
                arm7_9->wp1_used = 3;
-       }
-       else
-       {
+       } else {
                LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
                return ERROR_FAIL;
        }
 
-       if (arm7_9->sw_breakpoints_added == 1)
-       {
+       if (arm7_9->sw_breakpoints_added == 1) {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0x0);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffffu);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-       }
-       else if (arm7_9->sw_breakpoints_added == 2)
-       {
+       } else if (arm7_9->sw_breakpoints_added == 2) {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], arm7_9->arm_bkpt);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0x0);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0xffffffffu);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-       }
-       else
-       {
+       } else {
                LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
                return ERROR_FAIL;
        }
        LOG_DEBUG("SW BP using hw wp: %d",
-                         arm7_9->sw_breakpoints_added );
+               arm7_9->sw_breakpoints_added);
 
        return jtag_execute_queue();
 }
@@ -199,116 +181,99 @@ static int arm7_9_setup(struct target *target)
  * @param target Pointer to the target device to set the breakpoints on
  * @param breakpoint Pointer to the breakpoint to be set
  * @return For hardware breakpoints, this is the result of executing the JTAG
- *         queue.  For software breakpoints, this will be the status of the
- *         required memory reads and writes
+ * queue.  For software breakpoints, this will be the status of the
+ * required memory reads and writes
  */
 static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        int retval = ERROR_OK;
 
-       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
-                         breakpoint->unique_id,
-                         breakpoint->address,
-                         breakpoint->type);
+       LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d",
+               breakpoint->unique_id,
+               breakpoint->address,
+               breakpoint->type);
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (breakpoint->type == BKPT_HARD)
-       {
+       if (breakpoint->type == BKPT_HARD) {
                /* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
                uint32_t mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
 
                /* reassign a hw breakpoint */
                if (breakpoint->set == 0)
-               {
                        arm7_9_assign_wp(arm7_9, breakpoint);
-               }
 
-               if (breakpoint->set == 1)
-               {
+               if (breakpoint->set == 1) {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffffu);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               }
-               else if (breakpoint->set == 2)
-               {
+               } else if (breakpoint->set == 2) {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], breakpoint->address);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffffu);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               }
-               else
-               {
+               } else {
                        LOG_ERROR("BUG: no hardware comparator available");
                        return ERROR_OK;
                }
 
                retval = jtag_execute_queue();
-       }
-       else if (breakpoint->type == BKPT_SOFT)
-       {
+       } else if (breakpoint->type == BKPT_SOFT) {
                /* did we already set this breakpoint? */
                if (breakpoint->set)
                        return ERROR_OK;
 
-               if (breakpoint->length == 4)
-               {
+               if (breakpoint->length == 4) {
                        uint32_t verify = 0xffffffff;
                        /* keep the original instruction in target endianness */
-                       if ((retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
-                       {
+                       retval = target_read_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                       /* write the breakpoint instruction in target endianness (arm7_9->arm_bkpt is host endian) */
-                       if ((retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt)) != ERROR_OK)
-                       {
+                       /* write the breakpoint instruction in target
+                        * endianness (arm7_9->arm_bkpt is host endian) */
+                       retval = target_write_u32(target, breakpoint->address, arm7_9->arm_bkpt);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
 
-                       if ((retval = target_read_u32(target, breakpoint->address, &verify)) != ERROR_OK)
-                       {
+                       retval = target_read_u32(target, breakpoint->address, &verify);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                       if (verify != arm7_9->arm_bkpt)
-                       {
-                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
+                       if (verify != arm7_9->arm_bkpt) {
+                               LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32
+                                               " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
-               }
-               else
-               {
+               } else {
                        uint16_t verify = 0xffff;
                        /* keep the original instruction in target endianness */
-                       if ((retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
-                       {
+                       retval = target_read_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                       /* write the breakpoint instruction in target endianness (arm7_9->thumb_bkpt is host endian) */
-                       if ((retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt)) != ERROR_OK)
-                       {
+                       /* write the breakpoint instruction in target
+                        * endianness (arm7_9->thumb_bkpt is host endian) */
+                       retval = target_write_u16(target, breakpoint->address, arm7_9->thumb_bkpt);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
 
-                       if ((retval = target_read_u16(target, breakpoint->address, &verify)) != ERROR_OK)
-                       {
+                       retval = target_read_u16(target, breakpoint->address, &verify);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                       if (verify != arm7_9->thumb_bkpt)
-                       {
-                               LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
+                       if (verify != arm7_9->thumb_bkpt) {
+                               LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32
+                                               " - check that memory is read/writable", breakpoint->address);
                                return ERROR_OK;
                        }
                }
 
-               if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
+               retval = arm7_9_set_software_breakpoints(arm7_9);
+               if (retval != ERROR_OK)
                        return retval;
 
                arm7_9->sw_breakpoint_count++;
@@ -328,8 +293,8 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break
  * @param target Pointer to ARM7/9 target to unset the breakpoint from
  * @param breakpoint Pointer to breakpoint to be unset
  * @return For hardware breakpoints, this is the result of executing the JTAG
- *         queue.  For software breakpoints, this will be the status of the
- *         required memory reads and writes
+ * queue.  For software breakpoints, this will be the status of the
+ * required memory reads and writes
  */
 static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
@@ -337,80 +302,71 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
        LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
-                         breakpoint->unique_id,
-                         breakpoint->address );
+               breakpoint->unique_id,
+               breakpoint->address);
 
-       if (!breakpoint->set)
-       {
+       if (!breakpoint->set) {
                LOG_WARNING("breakpoint not set");
                return ERROR_OK;
        }
 
-       if (breakpoint->type == BKPT_HARD)
-       {
+       if (breakpoint->type == BKPT_HARD) {
                LOG_DEBUG("BPID: %d Releasing hw wp: %d",
-                                 breakpoint->unique_id,
-                                 breakpoint->set );
-               if (breakpoint->set == 1)
-               {
+                       breakpoint->unique_id,
+                       breakpoint->set);
+               if (breakpoint->set == 1) {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
                        arm7_9->wp0_used = 0;
                        arm7_9->wp_available++;
-               }
-               else if (breakpoint->set == 2)
-               {
+               } else if (breakpoint->set == 2) {
                        embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
                        arm7_9->wp1_used = 0;
                        arm7_9->wp_available++;
                }
                retval = jtag_execute_queue();
                breakpoint->set = 0;
-       }
-       else
-       {
+       } else {
                /* restore original instruction (kept in target endianness) */
-               if (breakpoint->length == 4)
-               {
+               if (breakpoint->length == 4) {
                        uint32_t current_instr;
                        /* check that user program as not modified breakpoint instruction */
-                       if ((retval = target_read_memory(target, breakpoint->address, 4, 1, (uint8_t*)&current_instr)) != ERROR_OK)
-                       {
+                       retval = target_read_memory(target,
+                                       breakpoint->address, 4, 1, (uint8_t *)&current_instr);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                        current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
-                       if (current_instr == arm7_9->arm_bkpt)
-                               if ((retval = target_write_memory(target, breakpoint->address, 4, 1, breakpoint->orig_instr)) != ERROR_OK)
-                               {
+                       current_instr = target_buffer_get_u32(target, (uint8_t *)&current_instr);
+                       if (current_instr == arm7_9->arm_bkpt) {
+                               retval = target_write_memory(target,
+                                               breakpoint->address, 4, 1, breakpoint->orig_instr);
+                               if (retval != ERROR_OK)
                                        return retval;
-                               }
-               }
-               else
-               {
+                       }
+
+               } else {
                        uint16_t current_instr;
                        /* check that user program as not modified breakpoint instruction */
-                       if ((retval = target_read_memory(target, breakpoint->address, 2, 1, (uint8_t*)&current_instr)) != ERROR_OK)
-                       {
+                       retval = target_read_memory(target,
+                                       breakpoint->address, 2, 1, (uint8_t *)&current_instr);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                        current_instr = target_buffer_get_u16(target, (uint8_t *)&current_instr);
                        if (current_instr == arm7_9->thumb_bkpt)
-                               if ((retval = target_write_memory(target, breakpoint->address, 2, 1, breakpoint->orig_instr)) != ERROR_OK)
-                               {
+                               retval = target_write_memory(target,
+                                               breakpoint->address, 2, 1, breakpoint->orig_instr);
+                               if (retval != ERROR_OK)
                                        return retval;
-                               }
+
                }
 
-               if (--arm7_9->sw_breakpoint_count==0)
-               {
-                       /* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
+               if (--arm7_9->sw_breakpoint_count == 0) {
+                       /* We have removed the last sw breakpoint, clear the hw breakpoint we used
+                        *to implement it */
                        if (arm7_9->sw_breakpoints_added == 1)
-                       {
-                               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
-                       }
+                               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[
+                                               EICE_W0_CONTROL_VALUE], 0);
                        else if (arm7_9->sw_breakpoints_added == 2)
-                       {
-                               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
-                       }
+                               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[
+                                               EICE_W1_CONTROL_VALUE], 0);
                }
 
                breakpoint->set = 0;
@@ -426,36 +382,31 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
  * @param target Pointer to the target ARM7/9 device to add a breakpoint to
  * @param breakpoint Pointer to the breakpoint to be added
  * @return An error status if there is a problem adding the breakpoint or the
- *         result of setting the breakpoint
+ * result of setting the breakpoint
  */
 int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (arm7_9->breakpoint_count == 0)
-       {
+       if (arm7_9->breakpoint_count == 0) {
                /* make sure we don't have any dangling breakpoints. This is vital upon
                 * GDB connect/disconnect
                 */
                arm7_9_clear_watchpoints(arm7_9);
        }
 
-       if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
-       {
+       if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1)) {
                LOG_INFO("no watchpoint unit available for hardware breakpoint");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 
-       if ((breakpoint->length != 2) && (breakpoint->length != 4))
-       {
+       if ((breakpoint->length != 2) && (breakpoint->length != 4)) {
                LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
        }
 
        if (breakpoint->type == BKPT_HARD)
-       {
                arm7_9_assign_wp(arm7_9, breakpoint);
-       }
 
        arm7_9->breakpoint_count++;
 
@@ -470,29 +421,26 @@ int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
  * @param target Pointer to the target to have a breakpoint removed
  * @param breakpoint Pointer to the breakpoint to be removed
  * @return Error status if there was a problem unsetting the breakpoint or the
- *         watchpoints could not be cleared
+ * watchpoints could not be cleared
  */
 int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
-       {
+       retval = arm7_9_unset_breakpoint(target, breakpoint);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        if (breakpoint->type == BKPT_HARD)
                arm7_9->wp_available++;
 
        arm7_9->breakpoint_count--;
-       if (arm7_9->breakpoint_count == 0)
-       {
+       if (arm7_9->breakpoint_count == 0) {
                /* make sure we don't have any dangling breakpoints */
-               if ((retval = arm7_9_clear_watchpoints(arm7_9)) != ERROR_OK)
-               {
+               retval = arm7_9_clear_watchpoints(arm7_9);
+               if (retval != ERROR_OK)
                        return retval;
-               }
        }
 
        return ERROR_OK;
@@ -506,7 +454,7 @@ int arm7_9_remove_breakpoint(struct target *target, struct breakpoint *breakpoin
  * @param target Pointer to an ARM7/9 target to set a watchpoint on
  * @param watchpoint Pointer to the watchpoint to be set
  * @return Error status if watchpoint set fails or the result of executing the
- *         JTAG queue
+ * JTAG queue
  */
 static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
@@ -517,8 +465,7 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch
 
        mask = watchpoint->length - 1;
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -528,42 +475,45 @@ static int arm7_9_set_watchpoint(struct target *target, struct watchpoint *watch
        else
                rw_mask = 1;
 
-       if (!arm7_9->wp0_used)
-       {
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
+       if (!arm7_9->wp0_used) {
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE],
+                       watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK],
+                       watchpoint->mask);
                if (watchpoint->mask != 0xffffffffu)
-                       embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
+                       embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE],
+                               watchpoint->value);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
+                       0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
+                       EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
                watchpoint->set = 1;
                arm7_9->wp0_used = 2;
-       }
-       else if (!arm7_9->wp1_used)
-       {
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
+       } else if (!arm7_9->wp1_used) {
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE],
+                       watchpoint->address);
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK],
+                       watchpoint->mask);
                if (watchpoint->mask != 0xffffffffu)
-                       embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
-               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
+                       embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE],
+                               watchpoint->value);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
+                       0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
+               embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
+                       EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
 
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
                watchpoint->set = 2;
                arm7_9->wp1_used = 2;
-       }
-       else
-       {
+       } else {
                LOG_ERROR("BUG: no hardware comparator available");
                return ERROR_OK;
        }
@@ -584,34 +534,27 @@ static int arm7_9_unset_watchpoint(struct target *target, struct watchpoint *wat
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (!watchpoint->set)
-       {
+       if (!watchpoint->set) {
                LOG_WARNING("breakpoint not set");
                return ERROR_OK;
        }
 
-       if (watchpoint->set == 1)
-       {
+       if (watchpoint->set == 1) {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
                arm7_9->wp0_used = 0;
-       }
-       else if (watchpoint->set == 2)
-       {
+       } else if (watchpoint->set == 2) {
                embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
                arm7_9->wp1_used = 0;
        }
        watchpoint->set = 0;
@@ -632,14 +575,10 @@ int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
        if (arm7_9->wp_available < 1)
-       {
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       }
 
        if ((watchpoint->length != 1) && (watchpoint->length != 2) && (watchpoint->length != 4))
-       {
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-       }
 
        arm7_9->wp_available--;
 
@@ -659,12 +598,10 @@ int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoin
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (watchpoint->set)
-       {
-               if ((retval = arm7_9_unset_watchpoint(target, watchpoint)) != ERROR_OK)
-               {
+       if (watchpoint->set) {
+               retval = arm7_9_unset_watchpoint(target, watchpoint);
+               if (retval != ERROR_OK)
                        return retval;
-               }
        }
 
        arm7_9->wp_available++;
@@ -679,7 +616,7 @@ int arm7_9_remove_watchpoint(struct target *target, struct watchpoint *watchpoin
  *
  * @param target Pointer to target to issue commands to
  * @return Error status if there is a timeout or a problem while executing the
- *         JTAG queue
+ * JTAG queue
  */
 int arm7_9_execute_sys_speed(struct target *target)
 {
@@ -701,26 +638,23 @@ int arm7_9_execute_sys_speed(struct target *target)
 
        long long then = timeval_ms();
        int timeout;
-       while (!(timeout = ((timeval_ms()-then) > 1000)))
-       {
+       while (!(timeout = ((timeval_ms()-then) > 1000))) {
                /* read debug status register */
                embeddedice_read_reg(dbg_stat);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
                if ((buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
-                                  && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
+                               && (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_SYSCOMP, 1)))
                        break;
                if (debug_level >= 3)
-               {
                        alive_sleep(100);
-               } else
-               {
+               else
                        keep_alive();
-               }
        }
-       if (timeout)
-       {
-               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
+       if (timeout) {
+               LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "",
+                       buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
                return ERROR_TARGET_TIMEOUT;
        }
 
@@ -737,7 +671,7 @@ int arm7_9_execute_sys_speed(struct target *target)
  */
 static int arm7_9_execute_fast_sys_speed(struct target *target)
 {
-       static int set = 0;
+       static int set;
        static uint8_t check_value[4], check_mask[4];
 
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -756,8 +690,7 @@ static int arm7_9_execute_fast_sys_speed(struct target *target)
        if (retval != ERROR_OK)
                return retval;
 
-       if (!set)
-       {
+       if (!set) {
                /* check for DBGACK and SYSCOMP set (others don't care) */
 
                /* NB! These are constants that must be available until after next jtag_execute() and
@@ -797,9 +730,7 @@ int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *bu
 
        /* return the 32-bit ints in the 8-bit array */
        for (i = 0; i < size; i++)
-       {
                h_u32_to_le(buffer + (i * 4), data[i]);
-       }
 
        free(data);
 
@@ -813,7 +744,7 @@ int arm7_9_target_request_data(struct target *target, uint32_t size, uint8_t *bu
  *
  * @param priv Void pointer expected to be a struct target pointer
  * @return ERROR_OK unless there are issues with the JTAG queue or when reading
- *                  from the Embedded ICE unit
+ * from the Embedded ICE unit
  */
 static int arm7_9_handle_target_request(void *priv)
 {
@@ -828,28 +759,23 @@ static int arm7_9_handle_target_request(void *priv)
        if (!target->dbg_msg_enabled)
                return ERROR_OK;
 
-       if (target->state == TARGET_RUNNING)
-       {
+       if (target->state == TARGET_RUNNING) {
                /* read DCC control register */
                embeddedice_read_reg(dcc_control);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
 
                /* check W bit */
-               if (buf_get_u32(dcc_control->value, 1, 1) == 1)
-               {
+               if (buf_get_u32(dcc_control->value, 1, 1) == 1) {
                        uint32_t request;
 
-                       if ((retval = embeddedice_receive(jtag_info, &request, 1)) != ERROR_OK)
-                       {
+                       retval = embeddedice_receive(jtag_info, &request, 1);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
-                       if ((retval = target_request(target, request)) != ERROR_OK)
-                       {
+                       retval = target_request(target, request);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                }
        }
 
@@ -862,11 +788,12 @@ static int arm7_9_handle_target_request(void *priv)
  * what happens:
  *
  * <table>
- *             <tr><th > State</th><th > Action</th></tr>
- *             <tr><td > TARGET_RUNNING | TARGET_RESET</td><td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
- *             <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
- *             <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
- *             <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
+ *   <tr><th > State</th><th > Action</th></tr>
+ *   <tr><td > TARGET_RUNNING | TARGET_RESET</td>
+ *     <td > Enters debug mode.  If TARGET_RESET, pc may be checked</td></tr>
+ *   <tr><td > TARGET_UNKNOWN</td><td > Warning is logged</td></tr>
+ *   <tr><td > TARGET_DEBUG_RUNNING</td><td > Enters debug mode</td></tr>
+ *   <tr><td > TARGET_HALTED</td><td > Nothing</td></tr>
  * </table>
  *
  * If the target does not end up in the halted state, a warning is produced.  If
@@ -884,53 +811,46 @@ int arm7_9_poll(struct target *target)
 
        /* read debug status register */
        embeddedice_read_reg(dbg_stat);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
-       }
 
-       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
-       {
-/*             LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));*/
-               if (target->state == TARGET_UNKNOWN)
-               {
+       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1)) {
+               /* LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, *32));*/
+               if (target->state == TARGET_UNKNOWN) {
                        /* Starting OpenOCD with target in debug-halt */
                        target->state = TARGET_RUNNING;
                        LOG_DEBUG("DBGACK already set during server startup.");
                }
-               if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
-               {
+               if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
                        target->state = TARGET_HALTED;
 
-                       if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
+                       retval = arm7_9_debug_entry(target);
+                       if (retval != ERROR_OK)
                                return retval;
 
                        if (arm_semihosting(target, &retval) != 0)
                                return retval;
 
-                       if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-                       {
+                       retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                }
-               if (target->state == TARGET_DEBUG_RUNNING)
-               {
+               if (target->state == TARGET_DEBUG_RUNNING) {
                        target->state = TARGET_HALTED;
-                       if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
+                       retval = arm7_9_debug_entry(target);
+                       if (retval != ERROR_OK)
                                return retval;
 
-                       if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED)) != ERROR_OK)
-                       {
+                       retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                }
                if (target->state != TARGET_HALTED)
-               {
-                       LOG_WARNING("DBGACK set, but the target did not end up in the halted state %d", target->state);
-               }
-       }
-       else
-       {
+                       LOG_WARNING(
+                               "DBGACK set, but the target did not end up in the halted state %d",
+                               target->state);
+       } else {
                if (target->state != TARGET_DEBUG_RUNNING)
                        target->state = TARGET_RUNNING;
        }
@@ -955,8 +875,7 @@ int arm7_9_assert_reset(struct target *target)
        enum reset_types jtag_reset_config = jtag_get_reset_config();
        bool use_event = false;
 
-       LOG_DEBUG("target->state: %s",
-                 target_state_name(target));
+       LOG_DEBUG("target->state: %s", target_state_name(target));
 
        if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
                use_event = true;
@@ -976,16 +895,13 @@ int arm7_9_assert_reset(struct target *target)
         */
        bool srst_asserted = false;
 
-       if (!use_event
-                       && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
-                       && (jtag_reset_config & RESET_SRST_NO_GATING))
-       {
+       if (!use_event && !(jtag_reset_config & RESET_SRST_PULLS_TRST)
+                       && (jtag_reset_config & RESET_SRST_NO_GATING)) {
                jtag_add_reset(0, 1);
                srst_asserted = true;
        }
 
-       if (target->reset_halt)
-       {
+       if (target->reset_halt) {
                /*
                 * For targets that don't support communication while SRST is
                 * asserted, we need to set up the reset vector catch first.
@@ -994,42 +910,30 @@ int arm7_9_assert_reset(struct target *target)
                 * reset, these settings may well be reset anyway; so setting
                 * them here won't matter.
                 */
-               if (arm7_9->has_vector_catch)
-               {
+               if (arm7_9->has_vector_catch) {
                        /* program vector catch register to catch reset */
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_VEC_CATCH], 0x1);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
 
                        /* extra runtest added as issues were found with
                         * certain ARM9 cores (maybe more) - AT91SAM9260
                         * and STR9
                         */
                        jtag_add_runtest(1, TAP_IDLE);
-               }
-               else
-               {
+               } else {
                        /* program watchpoint unit to match on reset vector
                         * address
                         */
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_W0_ADDR_VALUE], 0x0);
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_W0_ADDR_MASK], 0x3);
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_W0_DATA_MASK],
-                                               0xffffffff);
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_W0_CONTROL_VALUE],
-                                               EICE_W_CTRL_ENABLE);
-                       embeddedice_write_reg(&arm7_9->eice_cache
-                                       ->reg_list[EICE_W0_CONTROL_MASK],
-                                               ~EICE_W_CTRL_nOPC & 0xff);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
                }
        }
 
-       if (use_event) {
+       if (use_event)
                target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
-       else {
+       else {
                /* If we use SRST ... we'd like to issue just SRST, but the
                 * board or chip may be set up so we have to assert TRST as
                 * well.  On some chips that combination is equivalent to a
@@ -1046,10 +950,7 @@ int arm7_9_assert_reset(struct target *target)
        register_cache_invalidate(arm7_9->arm.core_cache);
 
        /* REVISIT why isn't standard debug entry logic sufficient?? */
-       if (target->reset_halt
-                       && (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
-                               || use_event))
-       {
+       if (target->reset_halt && (!(jtag_reset_config & RESET_SRST_PULLS_TRST) || use_event)) {
                /* debug entry was prepared above */
                target->debug_reason = DBG_REASON_DBGRQ;
        }
@@ -1069,8 +970,7 @@ int arm7_9_assert_reset(struct target *target)
 int arm7_9_deassert_reset(struct target *target)
 {
        int retval = ERROR_OK;
-       LOG_DEBUG("target->state: %s",
-               target_state_name(target));
+       LOG_DEBUG("target->state: %s", target_state_name(target));
 
        /* deassert reset lines */
        jtag_add_reset(0, 0);
@@ -1082,22 +982,21 @@ int arm7_9_deassert_reset(struct target *target)
         * error messages as halt will believe that reset is
         * still in effect.
         */
-       if ((retval = target_examine_one(target)) != ERROR_OK)
+       retval = target_examine_one(target);
+       if (retval != ERROR_OK)
                return retval;
 
-       if ((retval = target_poll(target)) != ERROR_OK)
-       {
+       retval = target_poll(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        enum reset_types jtag_reset_config = jtag_get_reset_config();
-       if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0)
-       {
-               LOG_WARNING("srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
-               if ((retval = target_halt(target)) != ERROR_OK)
-               {
+       if (target->reset_halt && (jtag_reset_config & RESET_SRST_PULLS_TRST) != 0) {
+               LOG_WARNING(
+                       "srst pulls trst - can not reset into halted mode. Issuing halt after reset.");
+               retval = target_halt(target);
+               if (retval != ERROR_OK)
                        return retval;
-               }
        }
        return retval;
 }
@@ -1117,36 +1016,31 @@ static int arm7_9_clear_halt(struct target *target)
        struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        /* we used DBGRQ only if we didn't come out of reset */
-       if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq)
-       {
+       if (!arm7_9->debug_entry_from_reset && arm7_9->use_dbgrq) {
                /* program EmbeddedICE Debug Control Register to deassert DBGRQ
                 */
                buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
                embeddedice_store_reg(dbg_ctrl);
-       }
-       else
-       {
-               if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch)
-               {
+       } else {
+               if (arm7_9->debug_entry_from_reset && arm7_9->has_vector_catch) {
                        /* if we came out of reset, and vector catch is supported, we used
                         * vector catch to enter debug state
                         * restore the register in that case
                         */
                        embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH]);
-               }
-               else
-               {
+               } else {
                        /* restore registers if watchpoint unit 0 was in use
                         */
-                       if (arm7_9->wp0_used)
-                       {
+                       if (arm7_9->wp0_used) {
                                if (arm7_9->debug_entry_from_reset)
-                               {
-                                       embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE]);
-                               }
-                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK]);
-                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK]);
-                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK]);
+                                       embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
+                                                       EICE_W0_ADDR_VALUE]);
+                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
+                                               EICE_W0_ADDR_MASK]);
+                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
+                                               EICE_W0_DATA_MASK]);
+                               embeddedice_store_reg(&arm7_9->eice_cache->reg_list[
+                                               EICE_W0_CONTROL_MASK]);
                        }
                        /* control value always has to be restored, as it was either disabled,
                         * or enabled with possibly different bits
@@ -1184,28 +1078,25 @@ int arm7_9_soft_reset_halt(struct target *target)
         *
         */
 
-       if ((retval = target_halt(target)) != ERROR_OK)
+       retval = target_halt(target);
+       if (retval != ERROR_OK)
                return retval;
 
        long long then = timeval_ms();
        int timeout;
-       while (!(timeout = ((timeval_ms()-then) > 1000)))
-       {
+       while (!(timeout = ((timeval_ms()-then) > 1000))) {
                if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) != 0)
                        break;
                embeddedice_read_reg(dbg_stat);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
                if (debug_level >= 3)
-               {
                        alive_sleep(100);
-               } else
-               {
+               else
                        keep_alive();
-               }
        }
-       if (timeout)
-       {
+       if (timeout) {
                LOG_ERROR("Failed to halt CPU after 1 sec");
                return ERROR_TARGET_TIMEOUT;
        }
@@ -1219,14 +1110,12 @@ int arm7_9_soft_reset_halt(struct target *target)
        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
        embeddedice_store_reg(dbg_ctrl);
 
-       if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
-       {
+       retval = arm7_9_clear_halt(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        /* if the target is in Thumb state, change to ARM state */
-       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
-       {
+       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) {
                uint32_t r0_thumb, pc_thumb;
                LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
                /* Entered debug from Thumb mode */
@@ -1254,8 +1143,7 @@ int arm7_9_soft_reset_halt(struct target *target)
        arm->pc->valid = 1;
 
        /* reset registers */
-       for (i = 0; i <= 14; i++)
-       {
+       for (i = 0; i <= 14; i++) {
                struct reg *r = arm_reg_current(arm, i);
 
                buf_set_u32(r->value, 0, 32, 0xffffffff);
@@ -1263,10 +1151,9 @@ int arm7_9_soft_reset_halt(struct target *target)
                r->valid = 1;
        }
 
-       if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-       {
+       retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        return ERROR_OK;
 }
@@ -1282,9 +1169,9 @@ int arm7_9_soft_reset_halt(struct target *target)
  */
 int arm7_9_halt(struct target *target)
 {
-       if (target->state == TARGET_RESET)
-       {
-               LOG_ERROR("BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
+       if (target->state == TARGET_RESET) {
+               LOG_ERROR(
+                       "BUG: arm7/9 does not support halt during reset. This is handled in arm7_9_assert_reset()");
                return ERROR_OK;
        }
 
@@ -1292,38 +1179,34 @@ int arm7_9_halt(struct target *target)
        struct reg *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
 
        LOG_DEBUG("target->state: %s",
-                 target_state_name(target));
+               target_state_name(target));
 
-       if (target->state == TARGET_HALTED)
-       {
+       if (target->state == TARGET_HALTED) {
                LOG_DEBUG("target was already halted");
                return ERROR_OK;
        }
 
        if (target->state == TARGET_UNKNOWN)
-       {
                LOG_WARNING("target was in unknown state when halt was requested");
-       }
 
-       if (arm7_9->use_dbgrq)
-       {
+       if (arm7_9->use_dbgrq) {
                /* program EmbeddedICE Debug Control Register to assert DBGRQ
                 */
-               if (arm7_9->set_special_dbgrq) {
+               if (arm7_9->set_special_dbgrq)
                        arm7_9->set_special_dbgrq(target);
-               else {
+               else {
                        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 1);
                        embeddedice_store_reg(dbg_ctrl);
                }
-       }
-       else
-       {
+       } else {
                /* program watchpoint unit to match on any address
                 */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
+                       EICE_W_CTRL_ENABLE);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
+                       ~EICE_W_CTRL_nOPC & 0xff);
        }
 
        target->debug_reason = DBG_REASON_DBGRQ;
@@ -1346,7 +1229,7 @@ static int arm7_9_debug_entry(struct target *target)
 {
        int i;
        uint32_t context[16];
-       uint32_tcontext_p[16];
+       uint32_t *context_p[16];
        uint32_t r0_thumb, pc_thumb;
        uint32_t cpsr, cpsr_mask = 0;
        int retval;
@@ -1367,29 +1250,25 @@ static int arm7_9_debug_entry(struct target *target)
        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 1);
        embeddedice_store_reg(dbg_ctrl);
 
-       if ((retval = arm7_9_clear_halt(target)) != ERROR_OK)
-       {
+       retval = arm7_9_clear_halt(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
-       }
 
-       if ((retval = arm7_9->examine_debug_reason(target)) != ERROR_OK)
+       retval = arm7_9->examine_debug_reason(target);
+       if (retval != ERROR_OK)
                return retval;
 
-
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        /* if the target is in Thumb state, change to ARM state */
-       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
-       {
+       if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1)) {
                LOG_DEBUG("target entered debug from Thumb state");
                /* Entered debug from Thumb mode */
                arm->core_state = ARM_STATE_THUMB;
@@ -1420,7 +1299,8 @@ static int arm7_9_debug_entry(struct target *target)
 
        arm7_9->read_xpsr(target, &cpsr, 0);
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
 
        /* Sync our CPSR copy with J or T bits EICE reported, but
@@ -1428,23 +1308,20 @@ static int arm7_9_debug_entry(struct target *target)
         */
        arm_set_cpsr(arm, cpsr | cpsr_mask);
 
-       if (!is_arm_mode(arm->core_mode))
-       {
+       if (!is_arm_mode(arm->core_mode)) {
                target->state = TARGET_UNKNOWN;
                LOG_ERROR("cpsr contains invalid mode value - communication failure");
                return ERROR_TARGET_FAILURE;
        }
 
        LOG_DEBUG("target entered debug state in %s mode",
-                        arm_mode_name(arm->core_mode));
+               arm_mode_name(arm->core_mode));
 
-       if (arm->core_state == ARM_STATE_THUMB)
-       {
+       if (arm->core_state == ARM_STATE_THUMB) {
                LOG_DEBUG("thumb state, applying fixups");
                context[0] = r0_thumb;
                context[15] = pc_thumb;
-       } else if (arm->core_state == ARM_STATE_ARM)
-       {
+       } else if (arm->core_state == ARM_STATE_ARM) {
                /* adjust value stored by STM */
                context[15] -= 3 * 4;
        }
@@ -1452,10 +1329,10 @@ static int arm7_9_debug_entry(struct target *target)
        if ((target->debug_reason != DBG_REASON_DBGRQ) || (!arm7_9->use_dbgrq))
                context[15] -= 3 * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
        else
-               context[15] -= arm7_9->dbgreq_adjust_pc * ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
+               context[15] -= arm7_9->dbgreq_adjust_pc *
+                       ((arm->core_state == ARM_STATE_ARM) ? 4 : 2);
 
-       for (i = 0; i <= 15; i++)
-       {
+       for (i = 0; i <= 15; i++) {
                struct reg *r = arm_reg_current(arm, i);
 
                LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
@@ -1472,20 +1349,19 @@ static int arm7_9_debug_entry(struct target *target)
        if (arm->spsr) {
                uint32_t spsr;
                arm7_9->read_xpsr(target, &spsr, 1);
-               if ((retval = jtag_execute_queue()) != ERROR_OK)
-               {
+               retval = jtag_execute_queue();
+               if (retval != ERROR_OK)
                        return retval;
-               }
                buf_set_u32(arm->spsr->value, 0, 32, spsr);
                arm->spsr->dirty = 0;
                arm->spsr->valid = 1;
        }
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
 
-       if (arm7_9->post_debug_entry)
-       {
+       if (arm7_9->post_debug_entry) {
                retval = arm7_9->post_debug_entry(target);
                if (retval != ERROR_OK)
                        return retval;
@@ -1512,14 +1388,12 @@ static int arm7_9_full_context(struct target *target)
 
        LOG_DEBUG("-");
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
-       if (!is_arm_mode(arm->core_mode))
-       {
+       if (!is_arm_mode(arm->core_mode)) {
                LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
        }
@@ -1527,41 +1401,43 @@ static int arm7_9_full_context(struct target *target)
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
         */
-       for (i = 0; i < 6; i++)
-       {
+       for (i = 0; i < 6; i++) {
                uint32_t mask = 0;
-               uint32_treg_p[16];
+               uint32_t *reg_p[16];
                int j;
                int valid = 1;
 
                /* check if there are invalid registers in the current mode
                 */
-               for (j = 0; j <= 16; j++)
-               {
+               for (j = 0; j <= 16; j++) {
                        if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
                                valid = 0;
                }
 
-               if (!valid)
-               {
+               if (!valid) {
                        uint32_t tmp_cpsr;
 
                        /* change processor mode (and mask T bit) */
                        tmp_cpsr = buf_get_u32(arm->cpsr->value, 0, 8)
-                                       & 0xe0;
+                               & 0xe0;
                        tmp_cpsr |= armv4_5_number_to_mode(i);
                        tmp_cpsr &= ~0x20;
                        arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 
-                       for (j = 0; j < 15; j++)
-                       {
-                               if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid == 0)
-                               {
-                                       reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
-                                                       armv4_5_number_to_mode(i), j).value;
+                       for (j = 0; j < 15; j++) {
+                               if (ARMV4_5_CORE_REG_MODE(arm->core_cache,
+                                               armv4_5_number_to_mode(i), j).valid == 0) {
+                                       reg_p[j] = (uint32_t *)ARMV4_5_CORE_REG_MODE(
+                                                       arm->core_cache,
+                                                       armv4_5_number_to_mode(i),
+                                                       j).value;
                                        mask |= 1 << j;
-                                       ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).valid = 1;
-                                       ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j).dirty = 0;
+                                       ARMV4_5_CORE_REG_MODE(arm->core_cache,
+                                               armv4_5_number_to_mode(i),
+                                               j).valid = 1;
+                                       ARMV4_5_CORE_REG_MODE(arm->core_cache,
+                                               armv4_5_number_to_mode(i),
+                                               j).dirty = 0;
                                }
                        }
 
@@ -1570,25 +1446,26 @@ static int arm7_9_full_context(struct target *target)
                                arm7_9->read_core_regs(target, mask, reg_p);
 
                        /* check if the PSR has to be read */
-                       if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid == 0)
-                       {
-                               arm7_9->read_xpsr(target, (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
+                       if (ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
+                                       16).valid == 0) {
+                               arm7_9->read_xpsr(target,
+                                       (uint32_t *)ARMV4_5_CORE_REG_MODE(arm->core_cache,
                                                armv4_5_number_to_mode(i), 16).value, 1);
-                               ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).valid = 1;
-                               ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16).dirty = 0;
+                               ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
+                                       16).valid = 1;
+                               ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i),
+                                       16).dirty = 0;
                        }
                }
        }
 
        /* restore processor mode (mask T bit) */
        arm7_9->write_xpsr_im8(target,
-                       buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20,
-                       0, 0);
+               buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0);
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
-       }
        return ERROR_OK;
 }
 
@@ -1602,7 +1479,7 @@ static int arm7_9_full_context(struct target *target)
  *
  * @param target Pointer to the ARM7/9 target to have its context restored
  * @return Error status if the target is not halted or the core mode in the
- *         armv4_5 struct is invalid.
+ * armv4_5 struct is invalid.
  */
 static int arm7_9_restore_context(struct target *target)
 {
@@ -1616,8 +1493,7 @@ static int arm7_9_restore_context(struct target *target)
 
        LOG_DEBUG("-");
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -1625,8 +1501,7 @@ static int arm7_9_restore_context(struct target *target)
        if (arm7_9->pre_restore_context)
                arm7_9->pre_restore_context(target);
 
-       if (!is_arm_mode(arm->core_mode))
-       {
+       if (!is_arm_mode(arm->core_mode)) {
                LOG_ERROR("not a valid arm core mode - communication failure?");
                return ERROR_FAIL;
        }
@@ -1634,51 +1509,42 @@ static int arm7_9_restore_context(struct target *target)
        /* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
         * SYS shares registers with User, so we don't touch SYS
         */
-       for (i = 0; i < 6; i++)
-       {
+       for (i = 0; i < 6; i++) {
                LOG_DEBUG("examining %s mode",
-                               arm_mode_name(arm->core_mode));
+                       arm_mode_name(arm->core_mode));
                dirty = 0;
                mode_change = 0;
                /* check if there are dirty registers in the current mode
                */
-               for (j = 0; j <= 16; j++)
-               {
+               for (j = 0; j <= 16; j++) {
                        reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
-                       if (reg->dirty == 1)
-                       {
-                               if (reg->valid == 1)
-                               {
+                       if (reg->dirty == 1) {
+                               if (reg->valid == 1) {
                                        dirty = 1;
                                        LOG_DEBUG("examining dirty reg: %s", reg->name);
                                        struct arm_reg *reg_arch_info;
                                        reg_arch_info = reg->arch_info;
                                        if ((reg_arch_info->mode != ARM_MODE_ANY)
-                                               && (reg_arch_info->mode != current_mode)
-                                               && !((reg_arch_info->mode == ARM_MODE_USR)
-                                               && (arm->core_mode == ARM_MODE_SYS))
-                                               && !((reg_arch_info->mode == ARM_MODE_SYS)
-                                               && (arm->core_mode == ARM_MODE_USR)))
-                                       {
+                                                       && (reg_arch_info->mode != current_mode)
+                                                       && !((reg_arch_info->mode == ARM_MODE_USR)
+                                                       && (arm->core_mode == ARM_MODE_SYS))
+                                                       && !((reg_arch_info->mode == ARM_MODE_SYS)
+                                                       && (arm->core_mode == ARM_MODE_USR))) {
                                                mode_change = 1;
                                                LOG_DEBUG("require mode change");
                                        }
-                               }
-                               else
-                               {
-                                       LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
-                               }
+                               } else
+                                       LOG_ERROR("BUG: dirty register '%s', but no valid data",
+                                               reg->name);
                        }
                }
 
-               if (dirty)
-               {
+               if (dirty) {
                        uint32_t mask = 0x0;
                        int num_regs = 0;
                        uint32_t regs[16];
 
-                       if (mode_change)
-                       {
+                       if (mode_change) {
                                uint32_t tmp_cpsr;
 
                                /* change processor mode (mask T bit) */
@@ -1690,12 +1556,12 @@ static int arm7_9_restore_context(struct target *target)
                                current_mode = armv4_5_number_to_mode(i);
                        }
 
-                       for (j = 0; j <= 14; j++)
-                       {
-                               reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), j);
+                       for (j = 0; j <= 14; j++) {
+                               reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
+                                               armv4_5_number_to_mode(i),
+                                               j);
 
-                               if (reg->dirty == 1)
-                               {
+                               if (reg->dirty == 1) {
                                        regs[j] = buf_get_u32(reg->value, 0, 32);
                                        mask |= 1 << j;
                                        num_regs++;
@@ -1709,16 +1575,17 @@ static int arm7_9_restore_context(struct target *target)
                        }
 
                        if (mask)
-                       {
                                arm7_9->write_core_regs(target, mask, regs);
-                       }
 
-                       reg = &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(i), 16);
+                       reg =
+                               &ARMV4_5_CORE_REG_MODE(arm->core_cache, armv4_5_number_to_mode(
+                                               i), 16);
                        struct arm_reg *reg_arch_info;
                        reg_arch_info = reg->arch_info;
-                       if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY))
-                       {
-                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
+                       if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) {
+                               LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
+                                       i,
+                                       buf_get_u32(reg->value, 0, 32));
                                arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
                        }
                }
@@ -1737,17 +1604,17 @@ static int arm7_9_restore_context(struct target *target)
        } else if (arm->cpsr->dirty) {
                /* CPSR has been changed, full restore necessary (mask T bit) */
                LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32,
-                               buf_get_u32(arm->cpsr->value, 0, 32));
+                       buf_get_u32(arm->cpsr->value, 0, 32));
                arm7_9->write_xpsr(target,
-                               buf_get_u32(arm->cpsr->value, 0, 32)
-                               & ~0x20, 0);
+                       buf_get_u32(arm->cpsr->value, 0, 32)
+                       & ~0x20, 0);
                arm->cpsr->dirty = 0;
                arm->cpsr->valid = 1;
        }
 
        /* restore PC */
        LOG_DEBUG("writing PC with value 0x%8.8" PRIx32,
-                       buf_get_u32(arm->pc->value, 0, 32));
+               buf_get_u32(arm->pc->value, 0, 32));
        arm7_9->write_pc(target, buf_get_u32(arm->pc->value, 0, 32));
        arm->pc->dirty = 0;
 
@@ -1794,8 +1661,7 @@ static void arm7_9_enable_watchpoints(struct target *target)
 {
        struct watchpoint *watchpoint = target->watchpoints;
 
-       while (watchpoint)
-       {
+       while (watchpoint) {
                if (watchpoint->set == 0)
                        arm7_9_set_watchpoint(target, watchpoint);
                watchpoint = watchpoint->next;
@@ -1813,14 +1679,17 @@ static void arm7_9_enable_breakpoints(struct target *target)
        struct breakpoint *breakpoint = target->breakpoints;
 
        /* set any pending breakpoints */
-       while (breakpoint)
-       {
+       while (breakpoint) {
                arm7_9_set_breakpoint(target, breakpoint);
                breakpoint = breakpoint->next;
        }
 }
 
-int arm7_9_resume(struct target *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
+int arm7_9_resume(struct target *target,
+       int current,
+       uint32_t address,
+       int handle_breakpoints,
+       int debug_execution)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *arm = &arm7_9->arm;
@@ -1829,16 +1698,13 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
 
        LOG_DEBUG("-");
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
 
        if (!debug_execution)
-       {
                target_free_all_working_areas(target);
-       }
 
        /* current = 1: continue on current pc, otherwise continue at <address> */
        if (!current)
@@ -1848,26 +1714,27 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
        current_pc = buf_get_u32(arm->pc->value, 0, 32);
 
        /* the front-end may request us not to handle breakpoints */
-       if (handle_breakpoints)
-       {
+       if (handle_breakpoints) {
                struct breakpoint *breakpoint;
                breakpoint = breakpoint_find(target,
                                buf_get_u32(arm->pc->value, 0, 32));
-               if (breakpoint != NULL)
-               {
-                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)", breakpoint->address, breakpoint->unique_id );
-                       if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
-                       {
+               if (breakpoint != NULL) {
+                       LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (id: %d)",
+                               breakpoint->address,
+                               breakpoint->unique_id);
+                       retval = arm7_9_unset_breakpoint(target, breakpoint);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
 
                        /* calculate PC of next instruction */
                        uint32_t next_pc;
-                       if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
-                       {
+                       retval = arm_simulate_step(target, &next_pc);
+                       if (retval != ERROR_OK) {
                                uint32_t current_opcode;
                                target_read_u32(target, current_pc, &current_opcode);
-                               LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+                               LOG_ERROR(
+                                       "Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
+                                       current_opcode);
                                return retval;
                        }
 
@@ -1876,7 +1743,8 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
 
                        target->debug_reason = DBG_REASON_SINGLESTEP;
 
-                       if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+                       retval = arm7_9_restore_context(target);
+                       if (retval != ERROR_OK)
                                return retval;
 
                        if (arm->core_state == ARM_STATE_ARM)
@@ -1889,18 +1757,17 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                        }
 
                        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
-                       embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
+                       embeddedice_write_reg(dbg_ctrl,
+                               buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
                        err = arm7_9_execute_sys_speed(target);
 
                        LOG_DEBUG("disable single-step");
                        arm7_9->disable_single_step(target);
 
-                       if (err != ERROR_OK)
-                       {
-                               if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
-                               {
+                       if (err != ERROR_OK) {
+                               retval = arm7_9_set_breakpoint(target, breakpoint);
+                               if (retval != ERROR_OK)
                                        return retval;
-                               }
                                target->state = TARGET_UNKNOWN;
                                return err;
                        }
@@ -1909,13 +1776,12 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                        if (retval != ERROR_OK)
                                return retval;
                        LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
-                                       buf_get_u32(arm->pc->value, 0, 32));
+                               buf_get_u32(arm->pc->value, 0, 32));
 
                        LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
-                       if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
-                       {
+                       retval = arm7_9_set_breakpoint(target, breakpoint);
+                       if (retval != ERROR_OK)
                                return retval;
-                       }
                }
        }
 
@@ -1923,7 +1789,8 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
        arm7_9_enable_breakpoints(target);
        arm7_9_enable_watchpoints(target);
 
-       if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+       retval = arm7_9_restore_context(target);
+       if (retval != ERROR_OK)
                return retval;
 
        if (arm->core_state == ARM_STATE_ARM)
@@ -1942,30 +1809,24 @@ int arm7_9_resume(struct target *target, int current, uint32_t address, int hand
                buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_INTDIS, 1, 0);
        embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
 
-       if ((retval = arm7_9_restart_core(target)) != ERROR_OK)
-       {
+       retval = arm7_9_restart_core(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        target->debug_reason = DBG_REASON_NOTHALTED;
 
-       if (!debug_execution)
-       {
+       if (!debug_execution) {
                /* registers are now invalid */
                register_cache_invalidate(arm->core_cache);
                target->state = TARGET_RUNNING;
-               if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
-               {
+               retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+               if (retval != ERROR_OK)
                        return retval;
-               }
-       }
-       else
-       {
+       } else {
                target->state = TARGET_DEBUG_RUNNING;
-               if ((retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED)) != ERROR_OK)
-               {
+               retval = target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+               if (retval != ERROR_OK)
                        return retval;
-               }
        }
 
        LOG_DEBUG("target resumed");
@@ -1980,24 +1841,25 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
        uint32_t current_pc;
        current_pc = buf_get_u32(arm->pc->value, 0, 32);
 
-       if (next_pc != current_pc)
-       {
+       if (next_pc != current_pc) {
                /* setup an inverse breakpoint on the current PC
                * - comparator 1 matches the current address
                * - rangeout from comparator 1 is connected to comparator 0 rangein
                * - comparator 0 matches any address, as long as rangein is low */
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], current_pc);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE],
+                       EICE_W_CTRL_ENABLE);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK],
+                       ~(EICE_W_CTRL_RANGE | EICE_W_CTRL_nOPC) & 0xff);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE],
+                       current_pc);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
-       }
-       else
-       {
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
+                       ~EICE_W_CTRL_nOPC & 0xff);
+       } else {
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -2005,8 +1867,10 @@ void arm7_9_enable_eice_step(struct target *target, uint32_t next_pc)
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], next_pc);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], 0);
                embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], 0xffffffff);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE],
+                       EICE_W_CTRL_ENABLE);
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK],
+                       ~EICE_W_CTRL_nOPC & 0xff);
        }
 }
 
@@ -2032,8 +1896,7 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
        struct breakpoint *breakpoint = NULL;
        int err, retval;
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -2057,15 +1920,18 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
 
        /* calculate PC of next instruction */
        uint32_t next_pc;
-       if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
-       {
+       retval = arm_simulate_step(target, &next_pc);
+       if (retval != ERROR_OK) {
                uint32_t current_opcode;
                target_read_u32(target, current_pc, &current_opcode);
-               LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+               LOG_ERROR(
+                       "Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
+                       current_opcode);
                return retval;
        }
 
-       if ((retval = arm7_9_restore_context(target)) != ERROR_OK)
+       retval = arm7_9_restore_context(target);
+       if (retval != ERROR_OK)
                return retval;
 
        arm7_9->enable_single_step(target, next_pc);
@@ -2079,10 +1945,9 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
                return ERROR_FAIL;
        }
 
-       if ((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
-       {
+       retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        err = arm7_9_execute_sys_speed(target);
        arm7_9->disable_single_step(target);
@@ -2091,32 +1956,30 @@ int arm7_9_step(struct target *target, int current, uint32_t address, int handle
        register_cache_invalidate(arm->core_cache);
 
        if (err != ERROR_OK)
-       {
                target->state = TARGET_UNKNOWN;
-       else {
+       else {
                retval = arm7_9_debug_entry(target);
                if (retval != ERROR_OK)
                        return retval;
-               if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
-               {
+               retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+               if (retval != ERROR_OK)
                        return retval;
-               }
                LOG_DEBUG("target stepped");
        }
 
-       if (breakpoint)
-               if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
-               {
+       if (breakpoint) {
+               retval = arm7_9_set_breakpoint(target, breakpoint);
+               if (retval != ERROR_OK)
                        return retval;
-               }
+       }
 
        return err;
 }
 
 static int arm7_9_read_core_reg(struct target *target, struct reg *r,
-               int num, enum arm_mode mode)
+       int num, enum arm_mode mode)
 {
-       uint32_treg_p[16];
+       uint32_t *reg_p[16];
        int retval;
        struct arm_reg *areg = r->arch_info;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -2127,10 +1990,8 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       if ((mode != ARM_MODE_ANY)
-                       && (mode != arm->core_mode)
-                       && (areg->mode != ARM_MODE_ANY))
-       {
+       if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
+                       && (areg->mode != ARM_MODE_ANY)) {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
@@ -2141,44 +2002,38 @@ static int arm7_9_read_core_reg(struct target *target, struct reg *r,
        }
 
        uint32_t value = 0;
-       if ((num >= 0) && (num <= 15))
-       {
+       if ((num >= 0) && (num <= 15)) {
                /* read a normal core register */
                reg_p[num] = &value;
 
                arm7_9->read_core_regs(target, 1 << num, reg_p);
-       }
-       else
-       {
+       } else {
                /* read a program status register
                 * if the register mode is MODE_ANY, we read the cpsr, otherwise a spsr
                 */
                arm7_9->read_xpsr(target, &value, areg->mode != ARM_MODE_ANY);
        }
 
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK)
                return retval;
-       }
 
        r->valid = 1;
        r->dirty = 0;
        buf_set_u32(r->value, 0, 32, value);
 
-       if ((mode != ARM_MODE_ANY)
-                       && (mode != arm->core_mode)
-                       && (areg->mode != ARM_MODE_ANY))        {
+       if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
+                       && (areg->mode != ARM_MODE_ANY)) {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
-                               buf_get_u32(arm->cpsr->value, 0, 8)
-                                       & ~0x20, 0, 0);
+                       buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0);
        }
 
        return ERROR_OK;
 }
 
 static int arm7_9_write_core_reg(struct target *target, struct reg *r,
-               int num, enum arm_mode mode, uint32_t value)
+       int num, enum arm_mode mode, uint32_t value)
 {
        uint32_t reg[16];
        struct arm_reg *areg = r->arch_info;
@@ -2190,9 +2045,8 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        if ((num < 0) || (num > 16))
                return ERROR_COMMAND_SYNTAX_ERROR;
 
-       if ((mode != ARM_MODE_ANY)
-                       && (mode != arm->core_mode)
-                       && (areg->mode != ARM_MODE_ANY))        {
+       if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
+                       && (areg->mode != ARM_MODE_ANY)) {
                uint32_t tmp_cpsr;
 
                /* change processor mode (mask T bit) */
@@ -2202,15 +2056,12 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
                arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
        }
 
-       if ((num >= 0) && (num <= 15))
-       {
+       if ((num >= 0) && (num <= 15)) {
                /* write a normal core register */
                reg[num] = value;
 
                arm7_9->write_core_regs(target, 1 << num, reg);
-       }
-       else
-       {
+       } else {
                /* write a program status register
                * if the register mode is MODE_ANY, we write the cpsr, otherwise a spsr
                */
@@ -2226,19 +2077,21 @@ static int arm7_9_write_core_reg(struct target *target, struct reg *r,
        r->valid = 1;
        r->dirty = 0;
 
-       if ((mode != ARM_MODE_ANY)
-                       && (mode != arm->core_mode)
-                       && (areg->mode != ARM_MODE_ANY))        {
+       if ((mode != ARM_MODE_ANY) && (mode != arm->core_mode)
+                       && (areg->mode != ARM_MODE_ANY)) {
                /* restore processor mode (mask T bit) */
                arm7_9->write_xpsr_im8(target,
-                               buf_get_u32(arm->cpsr->value, 0, 8)
-                                       & ~0x20, 0, 0);
+                               buf_get_u32(arm->cpsr->value, 0, 8) & ~0x20, 0, 0);
        }
 
        return jtag_execute_queue();
 }
 
-int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm7_9_read_memory(struct target *target,
+       uint32_t address,
+       uint32_t size,
+       uint32_t count,
+       uint8_t *buffer)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *arm = &arm7_9->arm;
@@ -2250,10 +2103,10 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
        int retval;
        int last_reg = 0;
 
-       LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
+       LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+               address, size, count);
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -2271,13 +2124,12 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 
        int j = 0;
 
-       switch (size)
-       {
+       switch (size) {
                case 4:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
                                if (last_reg <= thisrun_accesses)
@@ -2302,22 +2154,19 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                num_accesses += thisrun_accesses;
 
                                if ((j++%1024) == 0)
-                               {
                                        keep_alive();
-                               }
                        }
                        break;
                case 2:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        if (i > last_reg)
-                                               last_reg = i;
+                                           last_reg = i;
                                        arm7_9->load_hword_reg(target, i);
                                        /* fast memory reads are only safe when the target is running
                                         * from a sufficiently high clock (32 kHz is usually too slow)
@@ -2327,9 +2176,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
                                        if (retval != ERROR_OK)
-                                       {
                                                return retval;
-                                       }
 
                                }
 
@@ -2340,20 +2187,17 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                num_accesses += thisrun_accesses;
 
                                if ((j++%1024) == 0)
-                               {
                                        keep_alive();
-                               }
                        }
                        break;
                case 1:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        if (i > last_reg)
                                                last_reg = i;
                                        arm7_9->load_byte_reg(target, i);
@@ -2365,9 +2209,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                        else
                                                retval = arm7_9_execute_sys_speed(target);
                                        if (retval != ERROR_OK)
-                                       {
                                                return retval;
-                                       }
                                }
 
                                arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1);
@@ -2377,9 +2219,7 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
                                num_accesses += thisrun_accesses;
 
                                if ((j++%1024) == 0)
-                               {
                                        keep_alive();
-                               }
                        }
                        break;
        }
@@ -2389,24 +2229,26 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
 
        for (i = 0; i <= last_reg; i++) {
                struct reg *r = arm_reg_current(arm, i);
-
                r->dirty = r->valid;
        }
 
        arm7_9->read_xpsr(target, &cpsr, 0);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK) {
                LOG_ERROR("JTAG error while reading cpsr");
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT))
-       {
-               LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) {
+               LOG_WARNING(
+                       "memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
+                       address,
+                       size,
+                       count);
 
                arm7_9->write_xpsr_im8(target,
-                               buf_get_u32(arm->cpsr->value, 0, 8)
-                                       & ~0x20, 0, 0);
+                       buf_get_u32(arm->cpsr->value, 0, 8)
+                       & ~0x20, 0, 0);
 
                return ERROR_TARGET_DATA_ABORT;
        }
@@ -2414,7 +2256,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
        return ERROR_OK;
 }
 
-int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size, uint32_t count, const uint8_t *buffer)
+int arm7_9_write_memory(struct target *target,
+       uint32_t address,
+       uint32_t size,
+       uint32_t count,
+       const uint8_t *buffer)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
        struct arm *arm = &arm7_9->arm;
@@ -2432,8 +2278,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
        LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
 #endif
 
-       if (target->state != TARGET_HALTED)
-       {
+       if (target->state != TARGET_HALTED) {
                LOG_WARNING("target not halted");
                return ERROR_TARGET_NOT_HALTED;
        }
@@ -2453,17 +2298,15 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
        buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 0);
        embeddedice_store_reg(dbg_ctrl);
 
-       switch (size)
-       {
+       switch (size) {
                case 4:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        if (i > last_reg)
                                                last_reg = i;
                                        reg[i] = target_buffer_get_u32(target, buffer);
@@ -2479,8 +2322,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                                 */
                                if (arm7_9->fast_memory_access)
                                        retval = arm7_9_execute_fast_sys_speed(target);
-                               else
-                               {
+                               else {
                                        retval = arm7_9_execute_sys_speed(target);
 
                                        /*
@@ -2495,22 +2337,19 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                                }
 
                                if (retval != ERROR_OK)
-                               {
                                        return retval;
-                               }
 
                                num_accesses += thisrun_accesses;
                        }
                        break;
                case 2:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        if (i > last_reg)
                                                last_reg = i;
                                        reg[i] = target_buffer_get_u16(target, buffer) & 0xffff;
@@ -2519,8 +2358,7 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 
                                arm7_9->write_core_regs(target, reg_list, reg);
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        arm7_9->store_hword_reg(target, i);
 
                                        /* fast memory writes are only safe when the target is running
@@ -2528,39 +2366,35 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
                                         */
                                        if (arm7_9->fast_memory_access)
                                                retval = arm7_9_execute_fast_sys_speed(target);
-                                       else
-                                       {
+                                       else {
                                                retval = arm7_9_execute_sys_speed(target);
 
-                                               /*
-                                                * if memory writes are made when the clock is running slow
-                                                * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
-                                                * processor operations after a "reset halt" or "reset init",
-                                                * need to immediately stroke the keep alive or will end up with
-                                                * gdb "keep alive not sent error message" problem.
-                                                */     
+                                               /*
+                                                * if memory writes are made when the clock is running slow
+                                                * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+                                                * processor operations after a "reset halt" or "reset init",
+                                                * need to immediately stroke the keep alive or will end up with
+                                                * gdb "keep alive not sent error message" problem.
+                                                */
 
-                                               keep_alive();
+                                               keep_alive();
                                        }
 
                                        if (retval != ERROR_OK)
-                                       {
                                                return retval;
-                                       }
                                }
 
                                num_accesses += thisrun_accesses;
                        }
                        break;
                case 1:
-                       while (num_accesses < count)
-                       {
+                       while (num_accesses < count) {
                                uint32_t reg_list;
-                               thisrun_accesses = ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
+                               thisrun_accesses =
+                                               ((count - num_accesses) >= 14) ? 14 : (count - num_accesses);
                                reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe;
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        if (i > last_reg)
                                                last_reg = i;
                                        reg[i] = *buffer++ & 0xff;
@@ -2568,33 +2402,29 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 
                                arm7_9->write_core_regs(target, reg_list, reg);
 
-                               for (i = 1; i <= thisrun_accesses; i++)
-                               {
+                               for (i = 1; i <= thisrun_accesses; i++) {
                                        arm7_9->store_byte_reg(target, i);
                                        /* fast memory writes are only safe when the target is running
                                         * from a sufficiently high clock (32 kHz is usually too slow)
                                         */
                                        if (arm7_9->fast_memory_access)
                                                retval = arm7_9_execute_fast_sys_speed(target);
-                                       else
-                                        {
-                                                retval = arm7_9_execute_sys_speed(target);
+                                       else {
+                                               retval = arm7_9_execute_sys_speed(target);
 
-                                                /*
-                                                 * if memory writes are made when the clock is running slow
-                                                 * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
-                                                 * processor operations after a "reset halt" or "reset init",
-                                                 * need to immediately stroke the keep alive or will end up with
-                                                 * gdb "keep alive not sent error message" problem.
-                                                 */
+                                               /*
+                                                * if memory writes are made when the clock is running slow
+                                                * (i.e. 32 kHz) which is necessary in some scripts to reconfigure
+                                                * processor operations after a "reset halt" or "reset init",
+                                                * need to immediately stroke the keep alive or will end up with
+                                                * gdb "keep alive not sent error message" problem.
+                                                */
 
-                                                keep_alive();
-                                        }
+                                               keep_alive();
+                                       }
 
                                        if (retval != ERROR_OK)
-                                       {
                                                return retval;
-                                       }
 
                                }
 
@@ -2612,24 +2442,26 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 
        for (i = 0; i <= last_reg; i++) {
                struct reg *r = arm_reg_current(arm, i);
-
                r->dirty = r->valid;
        }
 
        arm7_9->read_xpsr(target, &cpsr, 0);
-       if ((retval = jtag_execute_queue()) != ERROR_OK)
-       {
+       retval = jtag_execute_queue();
+       if (retval != ERROR_OK) {
                LOG_ERROR("JTAG error while reading cpsr");
                return ERROR_TARGET_DATA_ABORT;
        }
 
-       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT))
-       {
-               LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
+       if (((cpsr & 0x1f) == ARM_MODE_ABT) && (arm->core_mode != ARM_MODE_ABT)) {
+               LOG_WARNING(
+                       "memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")",
+                       address,
+                       size,
+                       count);
 
                arm7_9->write_xpsr_im8(target,
-                               buf_get_u32(arm->cpsr->value, 0, 8)
-                                       & ~0x20, 0, 0);
+                       buf_get_u32(arm->cpsr->value, 0, 8)
+                       & ~0x20, 0, 0);
 
                return ERROR_TARGET_DATA_ABORT;
        }
@@ -2640,25 +2472,30 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
 static int dcc_count;
 static const uint8_t *dcc_buffer;
 
-static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info)
+static int arm7_9_dcc_completion(struct target *target,
+       uint32_t exit_point,
+       int timeout_ms,
+       void *arch_info)
 {
        int retval = ERROR_OK;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if ((retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500)) != ERROR_OK)
+       retval = target_wait_state(target, TARGET_DEBUG_RUNNING, 500);
+       if (retval != ERROR_OK)
                return retval;
 
        int little = target->endianness == TARGET_LITTLE_ENDIAN;
        int count = dcc_count;
        const uint8_t *buffer = dcc_buffer;
-       if (count > 2)
-       {
+       if (count > 2) {
                /* Handle first & last using standard embeddedice_write_reg and the middle ones w/the
                 * core function repeated. */
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+                       fast_target_buffer_get_u32(buffer, little));
                buffer += 4;
 
-               struct embeddedice_reg *ice_reg = arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
+               struct embeddedice_reg *ice_reg =
+                       arm7_9->eice_cache->reg_list[EICE_COMMS_DATA].arch_info;
                uint8_t reg_addr = ice_reg->addr & 0x1f;
                struct jtag_tap *tap;
                tap = ice_reg->jtag_info->tap;
@@ -2666,26 +2503,24 @@ static int arm7_9_dcc_completion(struct target *target, uint32_t exit_point, int
                embeddedice_write_dcc(tap, reg_addr, buffer, little, count-2);
                buffer += (count-2)*4;
 
-               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
-       } else
-       {
+               embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+                       fast_target_buffer_get_u32(buffer, little));
+       } else {
                int i;
-               for (i = 0; i < count; i++)
-               {
-                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], fast_target_buffer_get_u32(buffer, little));
+               for (i = 0; i < count; i++) {
+                       embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA],
+                               fast_target_buffer_get_u32(buffer, little));
                        buffer += 4;
                }
        }
 
-       if ((retval = target_halt(target))!= ERROR_OK)
-       {
+       retval = target_halt(target);
+       if (retval != ERROR_OK)
                return retval;
-       }
        return target_wait_state(target, TARGET_HALTED, 500);
 }
 
-static const uint32_t dcc_code[] =
-{
+static const uint32_t dcc_code[] = {
        /* r0 == input, points to memory buffer
         * r1 == scratch
         */
@@ -2703,7 +2538,10 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, const uint8_t *buffer)
+int arm7_9_bulk_write_memory(struct target *target,
+       uint32_t address,
+       uint32_t count,
+       const uint8_t *buffer)
 {
        int retval;
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
@@ -2713,28 +2551,24 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
                return target_write_memory(target, address, 4, count, buffer);
 
        /* regrab previously allocated working_area, or allocate a new one */
-       if (!arm7_9->dcc_working_area)
-       {
+       if (!arm7_9->dcc_working_area) {
                uint8_t dcc_code_buf[6 * 4];
 
                /* make sure we have a working area */
-               if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
-               {
+               if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK) {
                        LOG_INFO("no working area available, falling back to memory writes");
                        return target_write_memory(target, address, 4, count, buffer);
                }
 
                /* copy target instructions to target endianness */
                for (i = 0; i < 6; i++)
-               {
                        target_buffer_set_u32(target, dcc_code_buf + i*4, dcc_code[i]);
-               }
 
                /* write DCC code to working area */
-               if ((retval = target_write_memory(target, arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf)) != ERROR_OK)
-               {
+               retval = target_write_memory(target,
+                               arm7_9->dcc_working_area->address, 4, 6, dcc_code_buf);
+               if (retval != ERROR_OK)
                        return retval;
-               }
        }
 
        struct arm_algorithm armv4_5_info;
@@ -2752,15 +2586,16 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
        dcc_buffer = buffer;
        retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
                        arm7_9->dcc_working_area->address,
-                               arm7_9->dcc_working_area->address + 6*4,
+                       arm7_9->dcc_working_area->address + 6*4,
                        20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
-       if (retval == ERROR_OK)
-       {
+       if (retval == ERROR_OK) {
                uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
-               if (endaddress != (address + count*4))
-               {
-                       LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address + count*4), endaddress);
+               if (endaddress != (address + count*4)) {
+                       LOG_ERROR(
+                               "DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "",
+                               (address + count*4),
+                               endaddress);
                        retval = ERROR_FAIL;
                }
        }
@@ -2811,19 +2646,15 @@ int arm7_9_check_reset(struct target *target)
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
        if (get_target_reset_nag() && !arm7_9->dcc_downloads)
-       {
-               LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
-       }
+               LOG_WARNING(
+                       "NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
 
        if (get_target_reset_nag() && (target->working_area_size == 0))
-       {
                LOG_WARNING("NOTE! Severe performance degradation without working memory enabled.");
-       }
 
        if (get_target_reset_nag() && !arm7_9->fast_memory_access)
-       {
-               LOG_WARNING("NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
-       }
+               LOG_WARNING(
+                       "NOTE! Severe performance degradation without fast memory access enabled. Type 'help fast'.");
 
        return ERROR_OK;
 }
@@ -2833,16 +2664,17 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (!is_arm7_9(arm7_9))
-       {
+       if (!is_arm7_9(arm7_9)) {
                command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
                return ERROR_TARGET_INVALID;
        }
 
        if (CMD_ARGC > 0)
-               COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
+               COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->use_dbgrq);
 
-       command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
+       command_print(CMD_CTX,
+               "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s",
+               (arm7_9->use_dbgrq) ? "enabled" : "disabled");
 
        return ERROR_OK;
 }
@@ -2852,8 +2684,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (!is_arm7_9(arm7_9))
-       {
+       if (!is_arm7_9(arm7_9)) {
                command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
                return ERROR_TARGET_INVALID;
        }
@@ -2861,7 +2692,9 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
        if (CMD_ARGC > 0)
                COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
 
-       command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
+       command_print(CMD_CTX,
+               "fast memory access is %s",
+               (arm7_9->fast_memory_access) ? "enabled" : "disabled");
 
        return ERROR_OK;
 }
@@ -2871,8 +2704,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
        struct target *target = get_current_target(CMD_CTX);
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (!is_arm7_9(arm7_9))
-       {
+       if (!is_arm7_9(arm7_9)) {
                command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
                return ERROR_TARGET_INVALID;
        }
@@ -2880,7 +2712,9 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
        if (CMD_ARGC > 0)
                COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
 
-       command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");
+       command_print(CMD_CTX,
+               "dcc downloads are %s",
+               (arm7_9->dcc_downloads) ? "enabled" : "disabled");
 
        return ERROR_OK;
 }
@@ -2889,15 +2723,14 @@ static int arm7_9_setup_semihosting(struct target *target, int enable)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (!is_arm7_9(arm7_9))
-       {
+       if (!is_arm7_9(arm7_9)) {
                LOG_USER("current target isn't an ARM7/ARM9 target");
                return ERROR_TARGET_INVALID;
        }
 
        if (arm7_9->has_vector_catch) {
                struct reg *vector_catch = &arm7_9->eice_cache
-                               ->reg_list[EICE_VEC_CATCH];
+                       ->reg_list[EICE_VEC_CATCH];
 
                if (!vector_catch->valid)
                        embeddedice_read_reg(vector_catch);
@@ -2921,7 +2754,8 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
 
        arm7_9->common_magic = ARM7_9_COMMON_MAGIC;
 
-       if ((retval = arm_jtag_setup_connection(&arm7_9->jtag_info)) != ERROR_OK)
+       retval = arm_jtag_setup_connection(&arm7_9->jtag_info);
+       if (retval != ERROR_OK)
                return retval;
 
        /* caller must have allocated via calloc(), so everything's zeroed */
@@ -2942,7 +2776,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
                return retval;
 
        return target_register_timer_callback(arm7_9_handle_target_request,
-                       1, 1, target);
+               1, 1, target);
 }
 
 static const struct command_registration arm7_9_any_command_handlers[] = {
index 536f561..6f1b51f 100644 (file)
@@ -26,6 +26,7 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
 #ifndef ARM7_9_COMMON_H
 #define ARM7_9_COMMON_H
 
@@ -37,8 +38,7 @@
 /**
  * Structure for items that are common between both ARM7 and ARM9 targets.
  */
-struct arm7_9_common
-{
+struct arm7_9_common {
        struct arm arm;
        uint32_t common_magic;
 
@@ -71,16 +71,26 @@ struct arm7_9_common
 
        struct working_area *dcc_working_area;
 
-       int (*examine_debug_reason)(struct target *target); /**< Function for determining why debug state was entered */
+       int (*examine_debug_reason)(struct target *target);
+       /**< Function for determining why debug state was entered */
+
+       void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc);
+       /**< Function for changing from Thumb to ARM mode */
+
+       void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]);
+       /**< Function for reading the core registers */
 
-       void (*change_to_arm)(struct target *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */
+       void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask,
+                       void *buffer, int size);
+       void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr);
+       /**< Function for reading CPSR or SPSR */
 
-       void (*read_core_regs)(struct target *target, uint32_t mask, uint32_t *core_regs[16]); /**< Function for reading the core registers */
-       void (*read_core_regs_target_buffer)(struct target *target, uint32_t mask, void *buffer, int size);
-       void (*read_xpsr)(struct target *target, uint32_t *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
+       void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr);
+       /**< Function for writing to CPSR or SPSR */
+
+       void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr);
+       /**< Function for writing an immediate value to CPSR or SPSR */
 
-       void (*write_xpsr)(struct target *target, uint32_t xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
-       void (*write_xpsr_im8)(struct target *target, uint8_t xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
        void (*write_core_regs)(struct target *target, uint32_t mask, uint32_t core_regs[16]);
 
        void (*load_word_regs)(struct target *target, uint32_t mask);
@@ -91,25 +101,28 @@ struct arm7_9_common
        void (*store_hword_reg)(struct target *target, int num);
        void (*store_byte_reg)(struct target *target, int num);
 
-       void (*write_pc)(struct target *target, uint32_t pc); /**< Function for writing to the program counter */
+       void (*write_pc)(struct target *target, uint32_t pc);
+       /**< Function for writing to the program counter */
+
        void (*branch_resume)(struct target *target);
        void (*branch_resume_thumb)(struct target *target);
 
        void (*enable_single_step)(struct target *target, uint32_t next_pc);
        void (*disable_single_step)(struct target *target);
 
-       void (*set_special_dbgrq)(struct target *target); /**< Function for setting DBGRQ if the normal way won't work */
+       void (*set_special_dbgrq)(struct target *target);
+       /**< Function for setting DBGRQ if the normal way won't work */
 
-       int (*post_debug_entry)(struct target *target); /**< Callback function called after entering debug mode */
+       int (*post_debug_entry)(struct target *target);
+       /**< Callback function called after entering debug mode */
 
-       void (*pre_restore_context)(struct target *target); /**< Callback function called before restoring the processor context */
+       void (*pre_restore_context)(struct target *target);
+       /**< Callback function called before restoring the processor context */
 };
 
-static inline struct arm7_9_common *
-target_to_arm7_9(struct target *target)
+static inline struct arm7_9_common *target_to_arm7_9(struct target *target)
 {
-       return container_of(target->arch_info, struct arm7_9_common,
-          &n