Fix a bunch of typos.
Most are in code comments, so nothing should break. UNKOWN_COMMAND and
CMD_UNKOWN are not used elsewhere, so correcting the spelling should
also not break anything.
13 files changed:
mx2_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
mx2_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
- * testing host endianess
+ * testing host endianness
*/
x = 1;
if (*(char *) &x == 1)
*/
x = 1;
if (*(char *) &x == 1)
mx3_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
mx3_nf_info->flags.target_little_endian =
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
- * testing host endianess
+ * testing host endianness
(0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
} else {
(0 == strcmp("clear", CMD_ARGV[0]))) { // quietly accept both
r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
} else {
- command_print(CMD_CTX, "Unkown command: %s", CMD_ARGV[0]);
+ command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
r = ERROR_COMMAND_SYNTAX_ERROR;
}
return r;
r = ERROR_COMMAND_SYNTAX_ERROR;
}
return r;
* REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
* inadvisable ... it makes future mass erase operations fail.
*/
* REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
* inadvisable ... it makes future mass erase operations fail.
*/
- LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
+ LOG_WARNING("Flash protection cannot be removed once committed, commit is NOT executed !");
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
/* Wait until erase complete */
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
/* Wait until erase complete */
uint8_t *buffer, int scan_size, struct scan_command *command);
uint8_t *buffer, int scan_size, struct scan_command *command);
+#define CMD_UNKNOWN 0x00
#define CMD_PORT_MODE 0x01
#define CMD_FEATURE 0x02
#define CMD_READ_ADCS 0x03
#define CMD_PORT_MODE 0x01
#define CMD_FEATURE 0x02
#define CMD_READ_ADCS 0x03
static void usbprog_runtest(int num_cycles);
static void usbprog_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size);
static void usbprog_runtest(int num_cycles);
static void usbprog_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int scan_size);
-#define UNKOWN_COMMAND 0x00
+#define UNKNOWN_COMMAND 0x00
#define PORT_DIRECTION 0x01
#define PORT_SET 0x02
#define PORT_GET 0x03
#define PORT_DIRECTION 0x01
#define PORT_SET 0x02
#define PORT_GET 0x03
# Defines basic Tcl procs for OpenOCD server modules
# Defines basic Tcl procs for OpenOCD server modules
-# Handle GDB 'R' packet. Can be overriden by configuration script,
+# Handle GDB 'R' packet. Can be overridden by configuration script,
# but it's not something one would expect target scripts to do
# normally
proc ocd_gdb_restart {target_id} {
# but it's not something one would expect target scripts to do
# normally
proc ocd_gdb_restart {target_id} {
svf_buffer_index = 0;
// double the buffer size
svf_buffer_index = 0;
// double the buffer size
- // in case current command cannot be commited, and next command is a bit scan command
+ // in case current command cannot be committed, and next command is a bit scan command
// here is 32K bits for this big scan command, it should be enough
// buffer will be reallocated if buffer size is not enough
svf_tdi_buffer = (uint8_t *)malloc(2 * SVF_MAX_BUFFER_SIZE_TO_COMMIT);
// here is 32K bits for this big scan command, it should be enough
// buffer will be reallocated if buffer size is not enough
svf_tdi_buffer = (uint8_t *)malloc(2 * SVF_MAX_BUFFER_SIZE_TO_COMMIT);
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (exit_point && (pc != exit_point))
{
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
if (exit_point && (pc != exit_point))
{
- LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return ERROR_TARGET_TIMEOUT;
}
if ((elf->endianness != ELFDATA2LSB)
&&(elf->endianness != ELFDATA2MSB))
{
if ((elf->endianness != ELFDATA2LSB)
&&(elf->endianness != ELFDATA2MSB))
{
- LOG_ERROR("invalid ELF file, unknown endianess setting");
+ LOG_ERROR("invalid ELF file, unknown endianness setting");
return ERROR_IMAGE_FORMAT_ERROR;
}
return ERROR_IMAGE_FORMAT_ERROR;
}
pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
if (exit_point && (pc != exit_point))
{
pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
if (exit_point && (pc != exit_point))
{
- LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
+ LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
}
return ERROR_TARGET_TIMEOUT;
}
- /* convert to target endianess */
+ /* convert to target endianness */
for (i = 0; i < (size/sizeof(uint32_t)); i++)
{
uint32_t target_data;
for (i = 0; i < (size/sizeof(uint32_t)); i++)
{
uint32_t target_data;
DBG_REASON_UNDEFINED = 6
};
DBG_REASON_UNDEFINED = 6
};
{
TARGET_ENDIAN_UNKNOWN = 0,
TARGET_BIG_ENDIAN = 1, TARGET_LITTLE_ENDIAN = 2
{
TARGET_ENDIAN_UNKNOWN = 0,
TARGET_BIG_ENDIAN = 1, TARGET_LITTLE_ENDIAN = 2
uint32_t backup_working_area; /* whether the content of the working area has to be preserved */
struct working_area *working_areas;/* list of allocated working areas */
enum target_debug_reason debug_reason;/* reason why the target entered debug state */
uint32_t backup_working_area; /* whether the content of the working area has to be preserved */
struct working_area *working_areas;/* list of allocated working areas */
enum target_debug_reason debug_reason;/* reason why the target entered debug state */
- enum target_endianess endianness; /* target endianess */
+ enum target_endianness endianness; /* target endianness */
// also see: target_state_name()
enum target_state state; /* the current backend-state (running, halted, ...) */
struct reg_cache *reg_cache; /* the first register cache of the target (core regs) */
// also see: target_state_name()
enum target_state state; /* the current backend-state (running, halted, ...) */
struct reg_cache *reg_cache; /* the first register cache of the target (core regs) */
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