-/***************************************************************************\r
- * Copyright (C) 2009 by Marvell Semiconductors, Inc. *\r
- * Written by Nicolas Pitre <nico at marvell.com> *\r
- * *\r
- * This program is free software; you can redistribute it and/or modify *\r
- * it under the terms of the GNU General Public License as published by *\r
- * the Free Software Foundation; either version 2 of the License, or *\r
- * (at your option) any later version. *\r
- * *\r
- * This program is distributed in the hope that it will be useful, *\r
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *\r
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *\r
- * GNU General Public License for more details. *\r
- * *\r
- * You should have received a copy of the GNU General Public License *\r
- * along with this program; if not, write to the *\r
- * Free Software Foundation, Inc., *\r
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *\r
- ***************************************************************************/\r
-\r
-/*\r
- * NAND controller interface for Marvell Orion/Kirkwood SoCs.\r
- */\r
-\r
-#ifdef HAVE_CONFIG_H\r
-#include "config.h"\r
-#endif\r
-\r
-#include "replacements.h"\r
-#include "log.h"\r
-\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-#include "nand.h"\r
-#include "target.h"\r
-#include "armv4_5.h"\r
-#include "binarybuffer.h"\r
-\r
-typedef struct orion_nand_controller_s\r
-{\r
- struct target_s *target;\r
- working_area_t *copy_area;\r
-\r
- u32 cmd;\r
- u32 addr;\r
- u32 data;\r
-} orion_nand_controller_t;\r
-\r
-#define CHECK_HALTED \\r
- do { \\r
- if (target->state != TARGET_HALTED) { \\r
- LOG_ERROR("NAND flash access requires halted target"); \\r
- return ERROR_NAND_OPERATION_FAILED; \\r
- } \\r
- } while (0)\r
-\r
-int orion_nand_command(struct nand_device_s *device, u8 command)\r
-{\r
- orion_nand_controller_t *hw = device->controller_priv;\r
- target_t *target = hw->target;\r
-\r
- CHECK_HALTED;\r
- target_write_u8(target, hw->cmd, command);\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_address(struct nand_device_s *device, u8 address)\r
-{\r
- orion_nand_controller_t *hw = device->controller_priv;\r
- target_t *target = hw->target;\r
-\r
- CHECK_HALTED;\r
- target_write_u8(target, hw->addr, address);\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_read(struct nand_device_s *device, void *data)\r
-{\r
- orion_nand_controller_t *hw = device->controller_priv;\r
- target_t *target = hw->target;\r
-\r
- CHECK_HALTED;\r
- target_read_u8(target, hw->data, data);\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_write(struct nand_device_s *device, u16 data)\r
-{\r
- orion_nand_controller_t *hw = device->controller_priv;\r
- target_t *target = hw->target;\r
-\r
- CHECK_HALTED;\r
- target_write_u8(target, hw->data, data);\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)\r
-{\r
- while (size--)\r
- orion_nand_write(device, *data++);\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)\r
-{\r
- orion_nand_controller_t *hw = device->controller_priv;\r
- target_t *target = hw->target;\r
- armv4_5_algorithm_t algo;\r
- reg_param_t reg_params[3];\r
- u32 target_buf;\r
- int retval;\r
-\r
- static const u32 code[] = {\r
- 0xe4d13001, /* ldrb r3, [r1], #1 */\r
- 0xe5c03000, /* strb r3, [r0] */\r
- 0xe2522001, /* subs r2, r2, #1 */\r
- 0x1afffffb, /* bne 0 */\r
- 0xeafffffe, /* b . */\r
- };\r
- int code_size = sizeof(code);\r
-\r
- if (!hw->copy_area) {\r
- u8 code_buf[code_size];\r
- int i;\r
-\r
- /* make sure we have a working area */\r
- if (target_alloc_working_area(target,\r
- code_size + device->page_size,\r
- &hw->copy_area) != ERROR_OK)\r
- {\r
- return orion_nand_slow_block_write(device, data, size);\r
- }\r
-\r
- /* copy target instructions to target endianness */\r
- for (i = 0; i < code_size/4; i++)\r
- target_buffer_set_u32(target, code_buf + i*4, code[i]);\r
-\r
- /* write code to working area */\r
- retval = target->type->write_memory(target,\r
- hw->copy_area->address,\r
- 4, code_size/4, code_buf);\r
- if (retval != ERROR_OK)\r
- return retval;\r
- }\r
-\r
- /* copy data to target's memory */\r
- target_buf = hw->copy_area->address + code_size;\r
- retval = target->type->bulk_write_memory(target, target_buf,\r
- size/4, data);\r
- if (retval == ERROR_OK && size & 3) {\r
- retval = target->type->write_memory(target,\r
- target_buf + (size & ~3),\r
- 1, size & 3, data + (size & ~3));\r
- }\r
- if (retval != ERROR_OK)\r
- return retval;\r
-\r
- algo.common_magic = ARMV4_5_COMMON_MAGIC;\r
- algo.core_mode = ARMV4_5_MODE_SVC;\r
- algo.core_state = ARMV4_5_STATE_ARM;\r
-\r
- init_reg_param(®_params[0], "r0", 32, PARAM_IN);\r
- init_reg_param(®_params[1], "r1", 32, PARAM_IN);\r
- init_reg_param(®_params[2], "r2", 32, PARAM_IN);\r
-\r
- buf_set_u32(reg_params[0].value, 0, 32, hw->data);\r
- buf_set_u32(reg_params[1].value, 0, 32, target_buf);\r
- buf_set_u32(reg_params[2].value, 0, 32, size);\r
-\r
- retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,\r
- hw->copy_area->address,\r
- hw->copy_area->address + code_size - 4,\r
- 1000, &algo);\r
- if (retval != ERROR_OK)\r
- LOG_ERROR("error executing hosted NAND write");\r
-\r
- destroy_reg_param(®_params[0]);\r
- destroy_reg_param(®_params[1]);\r
- destroy_reg_param(®_params[2]);\r
- return retval;\r
-}\r
-\r
-int orion_nand_reset(struct nand_device_s *device)\r
-{\r
- return orion_nand_command(device, NAND_CMD_RESET);\r
-}\r
-\r
-int orion_nand_controller_ready(struct nand_device_s *device, int timeout)\r
-{\r
- return 1;\r
-}\r
-\r
-int orion_nand_register_commands(struct command_context_s *cmd_ctx)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,\r
- char **args, int argc,\r
- struct nand_device_s *device)\r
-{\r
- orion_nand_controller_t *hw;\r
- u32 base;\r
- u8 ale, cle;\r
-\r
- if (argc != 3) {\r
- LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");\r
- return ERROR_NAND_DEVICE_INVALID;\r
- }\r
-\r
- hw = calloc(1, sizeof(*hw));\r
- if (!hw) {\r
- LOG_ERROR("no memory for nand controller\n");\r
- return ERROR_NAND_DEVICE_INVALID;\r
- }\r
-\r
- device->controller_priv = hw;\r
- hw->target = get_target_by_num(strtoul(args[1], NULL, 0));\r
- if (!hw->target) {\r
- LOG_ERROR("no target '%s' configured", args[1]);\r
- free(hw);\r
- return ERROR_NAND_DEVICE_INVALID;\r
- }\r
-\r
- base = strtoul(args[2], NULL, 0);\r
- cle = 0;\r
- ale = 1;\r
-\r
- hw->data = base;\r
- hw->cmd = base + (1 << cle);\r
- hw->addr = base + (1 << ale);\r
-\r
- return ERROR_OK;\r
-}\r
-\r
-int orion_nand_init(struct nand_device_s *device)\r
-{\r
- return ERROR_OK;\r
-}\r
-\r
-nand_flash_controller_t orion_nand_controller =\r
-{\r
- .name = "orion",\r
- .command = orion_nand_command,\r
- .address = orion_nand_address,\r
- .read_data = orion_nand_read,\r
- .write_data = orion_nand_write,\r
- .write_block_data = orion_nand_fast_block_write,\r
- .reset = orion_nand_reset,\r
- .controller_ready = orion_nand_controller_ready,\r
- .nand_device_command = orion_nand_device_command,\r
- .register_commands = orion_nand_register_commands,\r
- .init = orion_nand_init,\r
-};\r
-\r
+/***************************************************************************
+ * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
+ * Written by Nicolas Pitre <nico at marvell.com> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * NAND controller interface for Marvell Orion/Kirkwood SoCs.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+#include "log.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include "nand.h"
+#include "target.h"
+#include "armv4_5.h"
+#include "binarybuffer.h"
+
+typedef struct orion_nand_controller_s
+{
+ struct target_s *target;
+ working_area_t *copy_area;
+
+ u32 cmd;
+ u32 addr;
+ u32 data;
+} orion_nand_controller_t;
+
+#define CHECK_HALTED \
+ do { \
+ if (target->state != TARGET_HALTED) { \
+ LOG_ERROR("NAND flash access requires halted target"); \
+ return ERROR_NAND_OPERATION_FAILED; \
+ } \
+ } while (0)
+
+int orion_nand_command(struct nand_device_s *device, u8 command)
+{
+ orion_nand_controller_t *hw = device->controller_priv;
+ target_t *target = hw->target;
+
+ CHECK_HALTED;
+ target_write_u8(target, hw->cmd, command);
+ return ERROR_OK;
+}
+
+int orion_nand_address(struct nand_device_s *device, u8 address)
+{
+ orion_nand_controller_t *hw = device->controller_priv;
+ target_t *target = hw->target;
+
+ CHECK_HALTED;
+ target_write_u8(target, hw->addr, address);
+ return ERROR_OK;
+}
+
+int orion_nand_read(struct nand_device_s *device, void *data)
+{
+ orion_nand_controller_t *hw = device->controller_priv;
+ target_t *target = hw->target;
+
+ CHECK_HALTED;
+ target_read_u8(target, hw->data, data);
+ return ERROR_OK;
+}
+
+int orion_nand_write(struct nand_device_s *device, u16 data)
+{
+ orion_nand_controller_t *hw = device->controller_priv;
+ target_t *target = hw->target;
+
+ CHECK_HALTED;
+ target_write_u8(target, hw->data, data);
+ return ERROR_OK;
+}
+
+int orion_nand_slow_block_write(struct nand_device_s *device, u8 *data, int size)
+{
+ while (size--)
+ orion_nand_write(device, *data++);
+ return ERROR_OK;
+}
+
+int orion_nand_fast_block_write(struct nand_device_s *device, u8 *data, int size)
+{
+ orion_nand_controller_t *hw = device->controller_priv;
+ target_t *target = hw->target;
+ armv4_5_algorithm_t algo;
+ reg_param_t reg_params[3];
+ u32 target_buf;
+ int retval;
+
+ static const u32 code[] = {
+ 0xe4d13001, /* ldrb r3, [r1], #1 */
+ 0xe5c03000, /* strb r3, [r0] */
+ 0xe2522001, /* subs r2, r2, #1 */
+ 0x1afffffb, /* bne 0 */
+ 0xeafffffe, /* b . */
+ };
+ int code_size = sizeof(code);
+
+ if (!hw->copy_area) {
+ u8 code_buf[code_size];
+ int i;
+
+ /* make sure we have a working area */
+ if (target_alloc_working_area(target,
+ code_size + device->page_size,
+ &hw->copy_area) != ERROR_OK)
+ {
+ return orion_nand_slow_block_write(device, data, size);
+ }
+
+ /* copy target instructions to target endianness */
+ for (i = 0; i < code_size/4; i++)
+ target_buffer_set_u32(target, code_buf + i*4, code[i]);
+
+ /* write code to working area */
+ retval = target->type->write_memory(target,
+ hw->copy_area->address,
+ 4, code_size/4, code_buf);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* copy data to target's memory */
+ target_buf = hw->copy_area->address + code_size;
+ retval = target->type->bulk_write_memory(target, target_buf,
+ size/4, data);
+ if (retval == ERROR_OK && size & 3) {
+ retval = target->type->write_memory(target,
+ target_buf + (size & ~3),
+ 1, size & 3, data + (size & ~3));
+ }
+ if (retval != ERROR_OK)
+ return retval;
+
+ algo.common_magic = ARMV4_5_COMMON_MAGIC;
+ algo.core_mode = ARMV4_5_MODE_SVC;
+ algo.core_state = ARMV4_5_STATE_ARM;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN);
+ init_reg_param(®_params[1], "r1", 32, PARAM_IN);
+ init_reg_param(®_params[2], "r2", 32, PARAM_IN);
+
+ buf_set_u32(reg_params[0].value, 0, 32, hw->data);
+ buf_set_u32(reg_params[1].value, 0, 32, target_buf);
+ buf_set_u32(reg_params[2].value, 0, 32, size);
+
+ retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params,
+ hw->copy_area->address,
+ hw->copy_area->address + code_size - 4,
+ 1000, &algo);
+ if (retval != ERROR_OK)
+ LOG_ERROR("error executing hosted NAND write");
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ return retval;
+}
+
+int orion_nand_reset(struct nand_device_s *device)
+{
+ return orion_nand_command(device, NAND_CMD_RESET);
+}
+
+int orion_nand_controller_ready(struct nand_device_s *device, int timeout)
+{
+ return 1;
+}
+
+int orion_nand_register_commands(struct command_context_s *cmd_ctx)
+{
+ return ERROR_OK;
+}
+
+int orion_nand_device_command(struct command_context_s *cmd_ctx, char *cmd,
+ char **args, int argc,
+ struct nand_device_s *device)
+{
+ orion_nand_controller_t *hw;
+ u32 base;
+ u8 ale, cle;
+
+ if (argc != 3) {
+ LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
+ return ERROR_NAND_DEVICE_INVALID;
+ }
+
+ hw = calloc(1, sizeof(*hw));
+ if (!hw) {
+ LOG_ERROR("no memory for nand controller\n");
+ return ERROR_NAND_DEVICE_INVALID;
+ }
+
+ device->controller_priv = hw;
+ hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
+ if (!hw->target) {
+ LOG_ERROR("no target '%s' configured", args[1]);
+ free(hw);
+ return ERROR_NAND_DEVICE_INVALID;
+ }
+
+ base = strtoul(args[2], NULL, 0);
+ cle = 0;
+ ale = 1;
+
+ hw->data = base;
+ hw->cmd = base + (1 << cle);
+ hw->addr = base + (1 << ale);
+
+ return ERROR_OK;
+}
+
+int orion_nand_init(struct nand_device_s *device)
+{
+ return ERROR_OK;
+}
+
+nand_flash_controller_t orion_nand_controller =
+{
+ .name = "orion",
+ .command = orion_nand_command,
+ .address = orion_nand_address,
+ .read_data = orion_nand_read,
+ .write_data = orion_nand_write,
+ .write_block_data = orion_nand_fast_block_write,
+ .reset = orion_nand_reset,
+ .controller_ready = orion_nand_controller_ready,
+ .nand_device_command = orion_nand_device_command,
+ .register_commands = orion_nand_register_commands,
+ .init = orion_nand_init,
+};
+
-# Marvell SheevaPlug \r
-\r
-source [find interface/sheevaplug.cfg]\r
-source [find target/feroceon.cfg]\r
-\r
-$_TARGETNAME configure -event reset-init { sheevaplug_init }\r
-\r
-$_TARGETNAME configure \\r
- -work-area-phys 0x10000000 \\r
- -work-area-size 65536 \\r
- -work-area-backup 0\r
-\r
-arm7_9 dcc_downloads enable\r
-\r
-# this assumes the hardware default peripherals location before u-Boot moves it\r
-nand device orion 0 0xd8000000\r
-\r
-proc sheevaplug_init { } {\r
-\r
- arm926ejs cp15 0 0 1 0 0x00052078\r
-\r
- mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register\r
- mww 0xD0001404 0x39543000 # Dunit Control Low Register\r
- mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register\r
- mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register\r
- mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register\r
- mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register\r
- mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register\r
- mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register\r
- mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register\r
- mww 0xD0001424 0x0000F17F # Dunit Control High Register\r
- mww 0xD0001428 0x00085520 # Dunit Control High Register\r
- mww 0xD000147c 0x00008552 # Dunit Control High Register\r
- mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register\r
- mww 0xD0001508 0x10000000 # CS1n Base Register\r
- mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register\r
- mww 0xD0001514 0x00000000 # CS2n Size Register\r
- mww 0xD000151C 0x00000000 # CS3n Size Register\r
- mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register\r
- mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister\r
- mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register\r
- mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register\r
- mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
- mww 0xD0020204 0x00000000 # "\r
-\r
- mww 0xD0010000 0x01111111 # MPP 0 to 7\r
- mww 0xD0010004 0x11113322 # MPP 8 to 15\r
- mww 0xD0010008 0x00001111 # MPP 16 to 23\r
-\r
- mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister\r
- mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register\r
- mww 0xD0010470 0x01C7D943 # NAND Flash Control Register\r
-\r
-}\r
-\r
-proc sheevaplug_reflash_uboot { } {\r
-\r
- # reflash the u-Boot binary\r
- #reset init\r
- nand probe 0\r
- nand erase 0 0 4\r
- nand write 0 uboot.bin 0\r
- reset run\r
-\r
-}\r
-\r
-proc sheevaplug_load_uboot { } {\r
-\r
- # load u-Boot into RAM\r
- #reset init\r
- load_image /tmp/uboot.elf\r
- verify_image uboot.elf\r
- resume 0x00600000\r
-\r
-}\r
-\r
+# Marvell SheevaPlug
+
+source [find interface/sheevaplug.cfg]
+source [find target/feroceon.cfg]
+
+$_TARGETNAME configure -event reset-init { sheevaplug_init }
+
+$_TARGETNAME configure \
+ -work-area-phys 0x10000000 \
+ -work-area-size 65536 \
+ -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+nand device orion 0 0xd8000000
+
+proc sheevaplug_init { } {
+
+ arm926ejs cp15 0 0 1 0 0x00052078
+
+ mww 0xD0001400 0x43000C30 # DDR SDRAM Configuration Register
+ mww 0xD0001404 0x39543000 # Dunit Control Low Register
+ mww 0xD0001408 0x22125451 # DDR SDRAM Timing (Low) Register
+ mww 0xD000140C 0x00000833 # DDR SDRAM Timing (High) Register
+ mww 0xD0001410 0x000000CC # DDR SDRAM Address Control Register
+ mww 0xD0001414 0x00000000 # DDR SDRAM Open Pages Control Register
+ mww 0xD0001418 0x00000000 # DDR SDRAM Operation Register
+ mww 0xD000141C 0x00000C52 # DDR SDRAM Mode Register
+ mww 0xD0001420 0x00000042 # DDR SDRAM Extended Mode Register
+ mww 0xD0001424 0x0000F17F # Dunit Control High Register
+ mww 0xD0001428 0x00085520 # Dunit Control High Register
+ mww 0xD000147c 0x00008552 # Dunit Control High Register
+ mww 0xD0001504 0x0FFFFFF1 # CS0n Size Register
+ mww 0xD0001508 0x10000000 # CS1n Base Register
+ mww 0xD000150C 0x0FFFFFF5 # CS1n Size Register
+ mww 0xD0001514 0x00000000 # CS2n Size Register
+ mww 0xD000151C 0x00000000 # CS3n Size Register
+ mww 0xD0001494 0x003C0000 # DDR2 SDRAM ODT Control (Low) Register
+ mww 0xD0001498 0x00000000 # DDR2 SDRAM ODT Control (High) REgister
+ mww 0xD000149C 0x0000F80F # DDR2 Dunit ODT Control Register
+ mww 0xD0001480 0x00000001 # DDR SDRAM Initialization Control Register
+ mww 0xD0020204 0x00000000 # Main IRQ Interrupt Mask Register
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+ mww 0xD0020204 0x00000000 # "
+
+ mww 0xD0010000 0x01111111 # MPP 0 to 7
+ mww 0xD0010004 0x11113322 # MPP 8 to 15
+ mww 0xD0010008 0x00001111 # MPP 16 to 23
+
+ mww 0xD0010418 0x003E07CF # NAND Read Parameters REgister
+ mww 0xD001041C 0x000F0F0F # NAND Write Parameters Register
+ mww 0xD0010470 0x01C7D943 # NAND Flash Control Register
+
+}
+
+proc sheevaplug_reflash_uboot { } {
+
+ # reflash the u-Boot binary
+ #reset init
+ nand probe 0
+ nand erase 0 0 4
+ nand write 0 uboot.bin 0
+ reset run
+
+}
+
+proc sheevaplug_load_uboot { } {
+
+ # load u-Boot into RAM
+ #reset init
+ load_image /tmp/uboot.elf
+ verify_image uboot.elf
+ resume 0x00600000
+
+}
+
Code Review / openocd.git / commitdiff