rtos: Add Cortex-R4 support for ThreadX 94/994/2
authorEvan Hunter <ehunter@broadcom.com>
Wed, 21 Nov 2012 07:00:36 +0000 (18:00 +1100)
committerSpencer Oliver <spen@spen-soft.co.uk>
Fri, 14 Dec 2012 20:45:22 +0000 (20:45 +0000)
Change-Id: I0b55af690ed917ca783d90d11dcf012f49792ed7
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/994
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
src/rtos/ThreadX.c
src/rtos/rtos_standard_stackings.c
src/rtos/rtos_standard_stackings.h

index 297f3fa8c05ed41fd14cc91cefd2ce9899b91327..714c6fef5df8ca98ccca9afcf35e48f1bffe3352 100644 (file)
@@ -80,7 +80,16 @@ const struct ThreadX_params ThreadX_params_list[] = {
        48,                                                     /* thread_state_offset; */
        136,                                            /* thread_next_offset */
        &rtos_standard_Cortex_M3_stacking,      /* stacking_info */
-       }
+       },
+       {
+       "cortex_r4",                            /* target_name */
+       4,                                                      /* pointer_width; */
+       8,                                                      /* thread_stack_offset; */
+       40,                                                     /* thread_name_offset; */
+       48,                                                     /* thread_state_offset; */
+       136,                                            /* thread_next_offset */
+       &rtos_standard_Cortex_R4_stacking,      /* stacking_info */
+       },
 };
 
 #define THREADX_NUM_PARAMS ((int)(sizeof(ThreadX_params_list)/sizeof(struct ThreadX_params)))
index 30d9cd963702314e7571fa223349f673780f6620..6b00cb754f2828ebb415c95bbaa03aed299d4ade 100644 (file)
@@ -53,6 +53,36 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[
        { 0x3c, 32 },           /* xPSR */
 };
 
+
+static const struct stack_register_offset rtos_standard_Cortex_R4_stack_offsets[] = {
+       { 0x08, 32 },           /* r0  (a1)   */
+       { 0x0c, 32 },           /* r1  (a2)  */
+       { 0x10, 32 },           /* r2  (a3)  */
+       { 0x14, 32 },           /* r3  (a4)  */
+       { 0x18, 32 },           /* r4  (v1)  */
+       { 0x1c, 32 },           /* r5  (v2)  */
+       { 0x20, 32 },           /* r6  (v3)  */
+       { 0x24, 32 },           /* r7  (v4)  */
+       { 0x28, 32 },           /* r8  (a1)  */
+       { 0x2c, 32 },           /* r9  (sb)  */
+       { 0x30, 32 },           /* r10 (sl) */
+       { 0x34, 32 },           /* r11 (fp) */
+       { 0x38, 32 },           /* r12 (ip) */
+       { -2,   32 },           /* sp   */
+       { 0x3c, 32 },           /* lr   */
+       { 0x40, 32 },           /* pc   */
+       { -1,   96 },           /* FPA1 */
+       { -1,   96 },           /* FPA2 */
+       { -1,   96 },           /* FPA3 */
+       { -1,   96 },           /* FPA4 */
+       { -1,   96 },           /* FPA5 */
+       { -1,   96 },           /* FPA6 */
+       { -1,   96 },           /* FPA7 */
+       { -1,   96 },           /* FPA8 */
+       { -1,   32 },           /* FPS  */
+       { 0x04, 32 },           /* CSPR */
+};
+
 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
        0x40,                                   /* stack_registers_size */
        -1,                                     /* stack_growth_direction */
@@ -60,3 +90,12 @@ const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
        8,                                      /* stack_alignment */
        rtos_standard_Cortex_M3_stack_offsets   /* register_offsets */
 };
+
+
+const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking = {
+       0x48,                                   /* stack_registers_size */
+       -1,                                     /* stack_growth_direction */
+       26,                                     /* num_output_registers */
+       8,                                      /* stack_alignment */
+       rtos_standard_Cortex_R4_stack_offsets   /* register_offsets */
+};
index 9f26b8e62c2fc3b558ac1734670beb9c43e6e70e..2713c0c6375d498985ec695f983458cbb33dc631 100644 (file)
@@ -28,5 +28,6 @@
 #include "rtos.h"
 
 extern const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking;
+extern const struct rtos_register_stacking rtos_standard_Cortex_R4_stacking;
 
 #endif /* ifndef INCLUDED_RTOS_STANDARD_STACKINGS_H_ */

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)