Add missing arm cmd handlers that enable semi hosting support to work as
expected.
Change-Id: I063d82c48b82b4f6aed4efc4b08ea752d78e9047
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/734
Tested-by: jenkins
Reviewed-by: Alan Bowman <alan.michael.bowman@gmail.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
return res;
target->state = TARGET_RUNNING;
return res;
target->state = TARGET_RUNNING;
+ target->debug_reason = DBG_REASON_NOTHALTED;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
return stm32_stlink_write_memory(target, address, 4, count, buffer);
}
return stm32_stlink_write_memory(target, address, 4, count, buffer);
}
+static const struct command_registration stm32_stlink_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
struct target_type stm32_stlink_target = {
.name = "stm32_stlink",
.init_target = stm32_stlink_init_target,
.target_create = stm32_stlink_target_create,
.examine = cortex_m3_examine,
struct target_type stm32_stlink_target = {
.name = "stm32_stlink",
.init_target = stm32_stlink_init_target,
.target_create = stm32_stlink_target_create,
.examine = cortex_m3_examine,
+ .commands = stm32_stlink_command_handlers,
.poll = stm32_stlink_poll,
.arch_state = armv7m_arch_state,
.poll = stm32_stlink_poll,
.arch_state = armv7m_arch_state,
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