target: arm: disassembler: decode v6T2 ARM ISB instruction

Change-Id: Iaaa54aee6a74f0b250b83c53e7a3fb7c17718920
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3895
Tested-by: jenkins

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 1536679367984fa65c8ae012888f47f89c41d070..f432f57ca42e69408e96586da0ab5e402ed8163c 100644 (file)
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -170,6 +170,18 @@ static int evaluate_pld(uint32_t opcode,
 
                return ERROR_OK;
        }
 
                return ERROR_OK;
        }

+       /* ISB */
+       if ((opcode & 0x07f000f0) == 0x05700060) {
+               instruction->type = ARM_ISB;
+
+               snprintf(instruction->text,
+                               128,
+                               "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tISB %s",
+                               address, opcode,
+                               ((opcode & 0x0000000f) == 0xf) ? "SY" : "UNK");
+
+               return ERROR_OK;
+       }

        return evaluate_unknown(opcode, address, instruction);
 }
 
        return evaluate_unknown(opcode, address, instruction);
 }
 

diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index b73f24a8914cc23b87e6243358fe3b2945df0928..e9f4d44cbb7066822483029bd7f5b129302f942c 100644 (file)
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -107,6 +107,7 @@ enum arm_instruction_type {
        ARM_MRRC,
        ARM_PLD,
        ARM_DSB,
        ARM_MRRC,
        ARM_PLD,
        ARM_DSB,

+       ARM_ISB,

        ARM_QADD,
        ARM_QDADD,
        ARM_QSUB,
        ARM_QADD,
        ARM_QDADD,
        ARM_QSUB,