aarch64: clean up scan-build errors 46/4346/4
authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>
Tue, 16 Jan 2018 12:05:04 +0000 (13:05 +0100)
committerMatthias Welwarsky <matthias@welwarsky.de>
Mon, 29 Jan 2018 08:24:17 +0000 (08:24 +0000)
scan-build reported a couple of problems with code in aarch64.c,
this patch cleans them up. No functional changes.

Change-Id: Ie210237ddc840a8bbcd535f86a3a5faf473132f2
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4346
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
src/target/aarch64.c

index bcfce65..14a2da6 100644 (file)
@@ -642,9 +642,11 @@ static int aarch64_prepare_restart_one(struct target *target)
                                armv8->debug_base + CPUV8_DBG_DSCR, dscr);
        }
 
-       /* clear sticky bits in PRSR, SDR is now 0 */
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_PRSR, &tmp);
+       if (retval == ERROR_OK) {
+               /* clear sticky bits in PRSR, SDR is now 0 */
+               retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                               armv8->debug_base + CPUV8_DBG_PRSR, &tmp);
+       }
 
        return retval;
 }
@@ -1815,6 +1817,8 @@ static int aarch64_write_cpu_memory(struct target *target,
        dscr = (dscr & ~DSCR_MA);
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        if (arm->core_state == ARM_STATE_AARCH64) {
                /* Write X0 with value 'address' using write procedure */
@@ -1826,10 +1830,13 @@ static int aarch64_write_cpu_memory(struct target *target,
                /* Write R0 with value 'address' using write procedure */
                /* Step 1.a+b - Write the address for read access into DBGDTRRX */
                /* Step 1.c   - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
-               dpm->instr_write_data_dcc(dpm,
+               retval = dpm->instr_write_data_dcc(dpm,
                                ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
        }
 
+       if (retval != ERROR_OK)
+               return retval;
+
        if (size == 4 && (address % 4) == 0)
                retval = aarch64_write_cpu_memory_fast(target, count, buffer, &dscr);
        else
@@ -1941,13 +1948,21 @@ static int aarch64_read_cpu_memory_fast(struct target *target,
                retval = dpm->instr_execute(dpm, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
        }
 
+       if (retval != ERROR_OK)
+               return retval;
+
        /* Step 1.e - Change DCC to memory mode */
        *dscr |= DSCR_MA;
        retval =  mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_DSCR, *dscr);
+       if (retval != ERROR_OK)
+               return retval;
+
        /* Step 1.f - read DBGDTRTX and discard the value */
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+       if (retval != ERROR_OK)
+               return retval;
 
        count--;
        /* Read the data - Each read of the DTRTX register causes the instruction to be reissued
@@ -2011,28 +2026,35 @@ static int aarch64_read_cpu_memory(struct target *target,
        /* Read DSCR */
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
                                armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        /* This algorithm comes from DDI0487A.g, chapter J9.1 */
 
        /* Set Normal access mode  */
        dscr &= ~DSCR_MA;
-       retval +=  mem_ap_write_atomic_u32(armv8->debug_ap,
+       retval =  mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+       if (retval != ERROR_OK)
+               return retval;
 
        if (arm->core_state == ARM_STATE_AARCH64) {
                /* Write X0 with value 'address' using write procedure */
                /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
                /* Step 1.c   - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
-               retval += dpm->instr_write_data_dcc_64(dpm,
+               retval = dpm->instr_write_data_dcc_64(dpm,
                                ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), address);
        } else {
                /* Write R0 with value 'address' using write procedure */
                /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
                /* Step 1.c   - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
-               retval += dpm->instr_write_data_dcc(dpm,
+               retval = dpm->instr_write_data_dcc(dpm,
                                ARMV4_5_MRC(14, 0, 0, 0, 5, 0), address);
        }
 
+       if (retval != ERROR_OK)
+               return retval;
+
        if (size == 4 && (address % 4) == 0)
                retval = aarch64_read_cpu_memory_fast(target, count, buffer, &dscr);
        else